Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and |
| 4 | * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) |
| 5 | * |
| 6 | * Modified for the at91rm9200dk board by |
| 7 | * (C) Copyright 2004 |
| 8 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <config.h> |
| 12 | |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 13 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 14 | |
| 15 | #include <asm/arch/hardware.h> |
| 16 | #include <asm/arch/at91_mc.h> |
| 17 | #include <asm/arch/at91_pmc.h> |
| 18 | #include <asm/arch/at91_pio.h> |
| 19 | |
| 20 | #define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */ |
| 21 | |
| 22 | _MTEXT_BASE: |
| 23 | #undef START_FROM_MEM |
| 24 | #ifdef START_FROM_MEM |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 25 | .word CONFIG_TEXT_BASE-PHYS_FLASH_1 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 26 | #else |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 27 | .word CONFIG_TEXT_BASE |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 28 | #endif |
| 29 | |
| 30 | .globl lowlevel_init |
| 31 | lowlevel_init: |
| 32 | ldr r1, =AT91_ASM_PMC_MOR |
| 33 | /* Main oscillator Enable register */ |
| 34 | #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR |
| 35 | ldr r0, =0x0000FF01 /* Enable main oscillator */ |
| 36 | #else |
| 37 | ldr r0, =0x0000FF00 /* Disable main oscillator */ |
| 38 | #endif |
| 39 | str r0, [r1] /*AT91C_CKGR_MOR] */ |
| 40 | /* Add loop to compensate Main Oscillator startup time */ |
| 41 | ldr r0, =0x00000010 |
| 42 | LoopOsc: |
| 43 | subs r0, r0, #1 |
| 44 | bhi LoopOsc |
| 45 | |
| 46 | /* memory control configuration */ |
| 47 | /* this isn't very elegant, but what the heck */ |
| 48 | ldr r0, =SMRDATA |
| 49 | ldr r1, _MTEXT_BASE |
| 50 | sub r0, r0, r1 |
Jens Scharsig | 36ff5f7 | 2010-12-18 02:30:04 +0000 | [diff] [blame] | 51 | ldr r2, =SMRDATAE |
| 52 | sub r2, r2, r1 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 53 | pllloop: |
| 54 | /* the address */ |
| 55 | ldr r1, [r0], #4 |
| 56 | /* the value */ |
| 57 | ldr r3, [r0], #4 |
| 58 | str r3, [r1] |
| 59 | cmp r2, r0 |
| 60 | bne pllloop |
| 61 | /* delay - this is all done by guess */ |
| 62 | ldr r0, =0x00010000 |
| 63 | /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ |
| 64 | lock: |
| 65 | subs r0, r0, #1 |
| 66 | bhi lock |
| 67 | ldr r0, =SMRDATA1 |
| 68 | ldr r1, _MTEXT_BASE |
| 69 | sub r0, r0, r1 |
Jens Scharsig | 36ff5f7 | 2010-12-18 02:30:04 +0000 | [diff] [blame] | 70 | ldr r2, =SMRDATA1E |
| 71 | sub r2, r2, r1 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 72 | sdinit: |
| 73 | /* the address */ |
| 74 | ldr r1, [r0], #4 |
| 75 | /* the value */ |
| 76 | ldr r3, [r0], #4 |
| 77 | str r3, [r1] |
| 78 | cmp r2, r0 |
| 79 | bne sdinit |
| 80 | |
| 81 | /* switch from FastBus to Asynchronous clock mode */ |
| 82 | mrc p15, 0, r0, c1, c0, 0 |
| 83 | orr r0, r0, #ARM920T_CONTROL |
| 84 | mcr p15, 0, r0, c1, c0, 0 |
| 85 | |
| 86 | /* everything is fine now */ |
| 87 | mov pc, lr |
| 88 | |
| 89 | .ltorg |
| 90 | |
| 91 | SMRDATA: |
| 92 | .word AT91_ASM_MC_EBI_CFG |
| 93 | .word CONFIG_SYS_EBI_CFGR_VAL |
| 94 | .word AT91_ASM_MC_SMC_CSR0 |
| 95 | .word CONFIG_SYS_SMC_CSR0_VAL |
| 96 | .word AT91_ASM_PMC_PLLAR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 97 | .word CFG_SYS_PLLAR_VAL |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 98 | .word AT91_ASM_PMC_PLLBR |
| 99 | .word CONFIG_SYS_PLLBR_VAL |
| 100 | .word AT91_ASM_PMC_MCKR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 101 | .word CFG_SYS_MCKR_VAL |
Jens Scharsig | 36ff5f7 | 2010-12-18 02:30:04 +0000 | [diff] [blame] | 102 | SMRDATAE: |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 103 | /* here there's a delay */ |
| 104 | SMRDATA1: |
| 105 | .word AT91_ASM_PIOC_ASR |
| 106 | .word CONFIG_SYS_PIOC_ASR_VAL |
| 107 | .word AT91_ASM_PIOC_BSR |
| 108 | .word CONFIG_SYS_PIOC_BSR_VAL |
| 109 | .word AT91_ASM_PIOC_PDR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 110 | .word CFG_SYS_PIOC_PDR_VAL |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 111 | .word AT91_ASM_MC_EBI_CSA |
| 112 | .word CONFIG_SYS_EBI_CSA_VAL |
| 113 | .word AT91_ASM_MC_SDRAMC_CR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 114 | .word CFG_SYS_SDRC_CR_VAL |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 115 | .word AT91_ASM_MC_SDRAMC_MR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 116 | .word CFG_SYS_SDRC_MR_VAL |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 117 | .word CFG_SYS_SDRAM |
| 118 | .word CFG_SYS_SDRAM_VAL |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 119 | .word AT91_ASM_MC_SDRAMC_MR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 120 | .word CFG_SYS_SDRC_MR_VAL1 |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 121 | .word CFG_SYS_SDRAM |
| 122 | .word CFG_SYS_SDRAM_VAL |
| 123 | .word CFG_SYS_SDRAM |
| 124 | .word CFG_SYS_SDRAM_VAL |
| 125 | .word CFG_SYS_SDRAM |
| 126 | .word CFG_SYS_SDRAM_VAL |
| 127 | .word CFG_SYS_SDRAM |
| 128 | .word CFG_SYS_SDRAM_VAL |
| 129 | .word CFG_SYS_SDRAM |
| 130 | .word CFG_SYS_SDRAM_VAL |
| 131 | .word CFG_SYS_SDRAM |
| 132 | .word CFG_SYS_SDRAM_VAL |
| 133 | .word CFG_SYS_SDRAM |
| 134 | .word CFG_SYS_SDRAM_VAL |
| 135 | .word CFG_SYS_SDRAM |
| 136 | .word CFG_SYS_SDRAM_VAL |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 137 | .word AT91_ASM_MC_SDRAMC_MR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 138 | .word CFG_SYS_SDRC_MR_VAL2 |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 139 | .word CFG_SYS_SDRAM1 |
| 140 | .word CFG_SYS_SDRAM_VAL |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 141 | .word AT91_ASM_MC_SDRAMC_TR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 142 | .word CFG_SYS_SDRC_TR_VAL |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 143 | .word CFG_SYS_SDRAM |
| 144 | .word CFG_SYS_SDRAM_VAL |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 145 | .word AT91_ASM_MC_SDRAMC_MR |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 146 | .word CFG_SYS_SDRC_MR_VAL3 |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 147 | .word CFG_SYS_SDRAM |
| 148 | .word CFG_SYS_SDRAM_VAL |
Jens Scharsig | 36ff5f7 | 2010-12-18 02:30:04 +0000 | [diff] [blame] | 149 | SMRDATA1E: |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 150 | /* SMRDATA1 is 176 bytes long */ |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 151 | #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ |