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git01.mediatek.com / filogic / uboot / 36ff5f7576414e01f00b06e1d2fa044839b74546 / . / arch / arm / cpu / arm920t / at91 / lowlevel_init.S
blob: 8b58ba9fa57c8255a499c8e3f1102fee5a0b3fbb [file] [log] [blame]
Jens Scharsig9bbaae32010-02-03 22:47:35 +0100[diff] [blame]1/*
2 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
3 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
4 *
5 * Modified for the at91rm9200dk board by
6 * (C) Copyright 2004
7 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29
30#ifndef CONFIG_SKIP_LOWLEVEL_INIT
31
32#include <asm/arch/hardware.h>
33#include <asm/arch/at91_mc.h>
34#include <asm/arch/at91_pmc.h>
35#include <asm/arch/at91_pio.h>
36
37#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
38
39_MTEXT_BASE:
40#undef START_FROM_MEM
41#ifdef START_FROM_MEM
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]42 .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
Jens Scharsig9bbaae32010-02-03 22:47:35 +0100[diff] [blame]43#else
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]44 .word CONFIG_SYS_TEXT_BASE
Jens Scharsig9bbaae32010-02-03 22:47:35 +0100[diff] [blame]45#endif
46
47.globl lowlevel_init
48lowlevel_init:
49 ldr r1, =AT91_ASM_PMC_MOR
50 /* Main oscillator Enable register */
51#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
52 ldr r0, =0x0000FF01 /* Enable main oscillator */
53#else
54 ldr r0, =0x0000FF00 /* Disable main oscillator */
55#endif
56 str r0, [r1] /*AT91C_CKGR_MOR] */
57 /* Add loop to compensate Main Oscillator startup time */
58 ldr r0, =0x00000010
59LoopOsc:
60 subs r0, r0, #1
61 bhi LoopOsc
62
63 /* memory control configuration */
64 /* this isn't very elegant, but what the heck */
65 ldr r0, =SMRDATA
66 ldr r1, _MTEXT_BASE
67 sub r0, r0, r1
Jens Scharsig36ff5f72010-12-18 02:30:04 +0000[diff] [blame^]68 ldr r2, =SMRDATAE
69 sub r2, r2, r1
Jens Scharsig9bbaae32010-02-03 22:47:35 +0100[diff] [blame]70pllloop:
71 /* the address */
72 ldr r1, [r0], #4
73 /* the value */
74 ldr r3, [r0], #4
75 str r3, [r1]
76 cmp r2, r0
77 bne pllloop
78 /* delay - this is all done by guess */
79 ldr r0, =0x00010000
80 /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
81lock:
82 subs r0, r0, #1
83 bhi lock
84 ldr r0, =SMRDATA1
85 ldr r1, _MTEXT_BASE
86 sub r0, r0, r1
Jens Scharsig36ff5f72010-12-18 02:30:04 +0000[diff] [blame^]87 ldr r2, =SMRDATA1E
88 sub r2, r2, r1
Jens Scharsig9bbaae32010-02-03 22:47:35 +0100[diff] [blame]89sdinit:
90 /* the address */
91 ldr r1, [r0], #4
92 /* the value */
93 ldr r3, [r0], #4
94 str r3, [r1]
95 cmp r2, r0
96 bne sdinit
97
98 /* switch from FastBus to Asynchronous clock mode */
99 mrc p15, 0, r0, c1, c0, 0
100 orr r0, r0, #ARM920T_CONTROL
101 mcr p15, 0, r0, c1, c0, 0
102
103 /* everything is fine now */
104 mov pc, lr
105
106 .ltorg
107
108SMRDATA:
109 .word AT91_ASM_MC_EBI_CFG
110 .word CONFIG_SYS_EBI_CFGR_VAL
111 .word AT91_ASM_MC_SMC_CSR0
112 .word CONFIG_SYS_SMC_CSR0_VAL
113 .word AT91_ASM_PMC_PLLAR
114 .word CONFIG_SYS_PLLAR_VAL
115 .word AT91_ASM_PMC_PLLBR
116 .word CONFIG_SYS_PLLBR_VAL
117 .word AT91_ASM_PMC_MCKR
118 .word CONFIG_SYS_MCKR_VAL
Jens Scharsig36ff5f72010-12-18 02:30:04 +0000[diff] [blame^]119SMRDATAE:
Jens Scharsig9bbaae32010-02-03 22:47:35 +0100[diff] [blame]120 /* here there's a delay */
121SMRDATA1:
122 .word AT91_ASM_PIOC_ASR
123 .word CONFIG_SYS_PIOC_ASR_VAL
124 .word AT91_ASM_PIOC_BSR
125 .word CONFIG_SYS_PIOC_BSR_VAL
126 .word AT91_ASM_PIOC_PDR
127 .word CONFIG_SYS_PIOC_PDR_VAL
128 .word AT91_ASM_MC_EBI_CSA
129 .word CONFIG_SYS_EBI_CSA_VAL
130 .word AT91_ASM_MC_SDRAMC_CR
131 .word CONFIG_SYS_SDRC_CR_VAL
132 .word AT91_ASM_MC_SDRAMC_MR
133 .word CONFIG_SYS_SDRC_MR_VAL
134 .word CONFIG_SYS_SDRAM
135 .word CONFIG_SYS_SDRAM_VAL
136 .word AT91_ASM_MC_SDRAMC_MR
137 .word CONFIG_SYS_SDRC_MR_VAL1
138 .word CONFIG_SYS_SDRAM
139 .word CONFIG_SYS_SDRAM_VAL
140 .word CONFIG_SYS_SDRAM
141 .word CONFIG_SYS_SDRAM_VAL
142 .word CONFIG_SYS_SDRAM
143 .word CONFIG_SYS_SDRAM_VAL
144 .word CONFIG_SYS_SDRAM
145 .word CONFIG_SYS_SDRAM_VAL
146 .word CONFIG_SYS_SDRAM
147 .word CONFIG_SYS_SDRAM_VAL
148 .word CONFIG_SYS_SDRAM
149 .word CONFIG_SYS_SDRAM_VAL
150 .word CONFIG_SYS_SDRAM
151 .word CONFIG_SYS_SDRAM_VAL
152 .word CONFIG_SYS_SDRAM
153 .word CONFIG_SYS_SDRAM_VAL
154 .word AT91_ASM_MC_SDRAMC_MR
155 .word CONFIG_SYS_SDRC_MR_VAL2
156 .word CONFIG_SYS_SDRAM1
157 .word CONFIG_SYS_SDRAM_VAL
158 .word AT91_ASM_MC_SDRAMC_TR
159 .word CONFIG_SYS_SDRC_TR_VAL
160 .word CONFIG_SYS_SDRAM
161 .word CONFIG_SYS_SDRAM_VAL
162 .word AT91_ASM_MC_SDRAMC_MR
163 .word CONFIG_SYS_SDRC_MR_VAL3
164 .word CONFIG_SYS_SDRAM
165 .word CONFIG_SYS_SDRAM_VAL
Jens Scharsig36ff5f72010-12-18 02:30:04 +0000[diff] [blame^]166SMRDATA1E:
Jens Scharsig9bbaae32010-02-03 22:47:35 +0100[diff] [blame]167 /* SMRDATA1 is 176 bytes long */
168#endif /* CONFIG_SKIP_LOWLEVEL_INIT */