| Minkyu Kang | ae6f0c6 | 2009-07-20 11:40:01 +0900 | [diff] [blame] | 1 | /* |
| Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 2 | * Board specific setup info |
| 3 | * |
| 4 | * (C) Copyright 2010 |
| 5 | * Texas Instruments, <www.ti.com> |
| 6 | * |
| 7 | * Author : |
| 8 | * Aneesh V <aneesh@ti.com> |
| Minkyu Kang | ae6f0c6 | 2009-07-20 11:40:01 +0900 | [diff] [blame] | 9 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
| Minkyu Kang | ae6f0c6 | 2009-07-20 11:40:01 +0900 | [diff] [blame] | 11 | */ |
| 12 | |
| Tom Rini | 8eb48ff | 2013-03-14 11:15:25 +0000 | [diff] [blame] | 13 | #include <config.h> |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 14 | #include <asm/arch/omap.h> |
| SRICHARAN R | 3f30b0a | 2013-04-24 00:41:24 +0000 | [diff] [blame] | 15 | #include <asm/omap_common.h> |
| Joel A Fernandes | b55759e | 2012-09-18 04:30:51 +0000 | [diff] [blame] | 16 | #include <asm/arch/spl.h> |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 17 | #include <linux/linkage.h> |
| Sricharan | 308fe92 | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 18 | |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 19 | ENTRY(save_boot_params) |
| SRICHARAN R | 3f30b0a | 2013-04-24 00:41:24 +0000 | [diff] [blame] | 20 | ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS |
| Sricharan | 308fe92 | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 21 | str r0, [r1] |
| Aneesh V | 13a74c1 | 2011-07-21 09:10:27 -0400 | [diff] [blame] | 22 | bx lr |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 23 | ENDPROC(save_boot_params) |
| Sricharan | 308fe92 | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 24 | |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 25 | ENTRY(set_pl310_ctrl_reg) |
| Aneesh V | e3405bd | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 26 | PUSH {r4-r11, lr} @ save registers - ROM code may pollute |
| 27 | @ our registers |
| 28 | LDR r12, =0x102 @ Set PL310 control register - value in R0 |
| 29 | .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 |
| 30 | @ call ROM Code API to set control register |
| 31 | POP {r4-r11, pc} |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 32 | ENDPROC(set_pl310_ctrl_reg) |