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git01.mediatek.com / filogic / uboot / 6fd4e0bab5e1b67b5e4c4230c8180a7e7ac41eed / . / arch / arm / dts / socfpga_stratix10_socdk.dts
blob: c5409df026ec1db7826841360c520853b53a43d2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]2/*
3 * Copyright (C) 2018 Intel Corporation
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]4 */
5
6#include "socfpga_stratix10.dtsi"
7
8/ {
9 model = "SoCFPGA Stratix 10 SoCDK";
10
11 aliases {
Ley Foon Tana14e34c2019-06-13 16:17:23 +0800[diff] [blame]12 i2c0 = &i2c1;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]13 serial0 = &uart0;
14 };
15
16 chosen {
17 stdout-path = "serial0:115200n8";
18 };
19
20 leds {
21 compatible = "gpio-leds";
22 hps0 {
23 label = "hps_led0";
24 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
25 };
26
27 hps1 {
28 label = "hps_led1";
29 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
30 };
31
32 hps2 {
33 label = "hps_led2";
34 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
35 };
36 };
37
38 memory {
39 device_type = "memory";
Ley Foon Tanb9ff1532019-03-22 01:24:03 +0800[diff] [blame]40 /* 4GB */
41 reg = <0 0x00000000 0 0x80000000>,
42 <1 0x80000000 0 0x80000000>;
Ley Foon Tanad259df2018-07-12 19:13:33 +0800[diff] [blame]43 u-boot,dm-pre-reloc;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]44 };
45};
46
47&gpio1 {
48 status = "okay";
49};
50
51&gmac0 {
52 status = "okay";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
55
56 max-frame-size = <3800>;
57
58 mdio0 {
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
62 phy0: ethernet-phy@0 {
63 reg = <4>;
64
65 txd0-skew-ps = <0>; /* -420ps */
66 txd1-skew-ps = <0>; /* -420ps */
67 txd2-skew-ps = <0>; /* -420ps */
68 txd3-skew-ps = <0>; /* -420ps */
69 rxd0-skew-ps = <420>; /* 0ps */
70 rxd1-skew-ps = <420>; /* 0ps */
71 rxd2-skew-ps = <420>; /* 0ps */
72 rxd3-skew-ps = <420>; /* 0ps */
73 txen-skew-ps = <0>; /* -420ps */
74 txc-skew-ps = <1860>; /* 960ps */
75 rxdv-skew-ps = <420>; /* 0ps */
76 rxc-skew-ps = <1680>; /* 780ps */
77 };
78 };
79};
80
Ley Foon Tana14e34c2019-06-13 16:17:23 +0800[diff] [blame]81&i2c1 {
82 status = "okay";
83};
84
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]85&mmc {
86 status = "okay";
87 cap-sd-highspeed;
Ley Foon Tan80a77ad2018-05-18 22:05:35 +0800[diff] [blame]88 cap-mmc-highspeed;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]89 broken-cd;
90 bus-width = <4>;
Ley Foon Tan80a77ad2018-05-18 22:05:35 +0800[diff] [blame]91 drvsel = <3>;
92 smplsel = <0>;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]93};
94
Ley Foon Tan2f59cf12019-04-03 13:45:02 +0800[diff] [blame]95&qspi {
96 flash0: flash@0 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "n25q00a";
100 reg = <0>;
101 spi-max-frequency = <50000000>;
102
103 m25p,fast-read;
104 cdns,page-size = <256>;
105 cdns,block-size = <16>;
106 cdns,read-delay = <1>;
107 cdns,tshsl-ns = <50>;
108 cdns,tsd2d-ns = <50>;
109 cdns,tchsh-ns = <4>;
110 cdns,tslch-ns = <4>;
111
112 partitions {
113 compatible = "fixed-partitions";
114 #address-cells = <1>;
115 #size-cells = <1>;
116
117 qspi_boot: partition@0 {
118 label = "Boot and fpga data";
119 reg = <0x0 0x4000000>;
120 };
121
122 qspi_rootfs: partition@4000000 {
123 label = "Root Filesystem - JFFS2";
124 reg = <0x4000000 0x4000000>;
125 };
126 };
127 };
128};
129
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]130&uart0 {
131 status = "okay";
132};
133
134&usb0 {
135 status = "okay";
136};