blob: f65a87a4e140a2fd9f5a4aa77f98a9a8210e2d8e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek0dd222b2013-04-22 14:56:49 +02002/*
Michal Simek9ecd2682015-11-30 16:13:03 +01003 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek0dd222b2013-04-22 14:56:49 +02004 *
5 * Xilinx Zynq SD Host Controller Interface
Michal Simek0dd222b2013-04-22 14:56:49 +02006 */
7
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +01008#include <clk.h>
Michal Simek0dd222b2013-04-22 14:56:49 +02009#include <common.h>
Michal Simek9ecd2682015-11-30 16:13:03 +010010#include <dm.h>
Michal Simekc57ba042014-02-24 11:16:31 +010011#include <fdtdec.h>
Simon Glassdbd79542020-05-10 11:40:11 -060012#include <linux/delay.h>
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053013#include "mmc_private.h"
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070016#include <linux/err.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090017#include <linux/libfdt.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020018#include <malloc.h>
19#include <sdhci.h>
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053020#include <zynqmp_tap_delay.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020021
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -060022#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
23#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
24#define SDHCI_ITAPDLY_CHGWIN 0x200
25#define SDHCI_ITAPDLY_ENABLE 0x100
26#define SDHCI_OTAPDLY_ENABLE 0x40
27
Michal Simek5b5101e2020-10-23 04:58:59 -060028#define SDHCI_TUNING_LOOP_COUNT 40
Michal Simek33a6b772020-10-23 04:59:00 -060029#define MMC_BANK2 0x2
30
31struct arasan_sdhci_clk_data {
32 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
33 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
34};
Michal Simek5b5101e2020-10-23 04:58:59 -060035
Simon Glass4cc87fb2016-07-05 17:10:15 -060036struct arasan_sdhci_plat {
37 struct mmc_config cfg;
38 struct mmc mmc;
39};
40
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053041struct arasan_sdhci_priv {
42 struct sdhci_host *host;
Michal Simek33a6b772020-10-23 04:59:00 -060043 struct arasan_sdhci_clk_data clk_data;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053044 u8 deviceid;
45 u8 bank;
Ashok Reddy Soma61e0df92020-10-23 04:58:57 -060046 u8 no_1p8;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053047};
48
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -060049#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
Michal Simek33a6b772020-10-23 04:59:00 -060050/* Default settings for ZynqMP Clock Phases */
51const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0};
52const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0};
53
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -060054/* Default settings for Versal Clock Phases */
55const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0};
56const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0};
57
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053058static const u8 mode2timing[] = {
Ashok Reddy Soma0afdfe32020-10-23 04:58:58 -060059 [MMC_LEGACY] = MMC_TIMING_LEGACY,
60 [MMC_HS] = MMC_TIMING_MMC_HS,
61 [SD_HS] = MMC_TIMING_SD_HS,
62 [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
63 [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
64 [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
65 [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
66 [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
67 [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
69 [MMC_HS_200] = MMC_TIMING_MMC_HS200,
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053070};
71
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053072static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
73{
74 u16 clk;
75 unsigned long timeout;
76
77 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
78 clk &= ~(SDHCI_CLOCK_CARD_EN);
79 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
80
81 /* Issue DLL Reset */
82 zynqmp_dll_reset(deviceid);
83
84 /* Wait max 20 ms */
85 timeout = 100;
86 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
87 & SDHCI_CLOCK_INT_STABLE)) {
88 if (timeout == 0) {
89 dev_err(mmc_dev(host->mmc),
90 ": Internal clock never stabilised.\n");
91 return;
92 }
93 timeout--;
94 udelay(1000);
95 }
96
97 clk |= SDHCI_CLOCK_CARD_EN;
98 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
99}
100
101static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
102{
103 struct mmc_cmd cmd;
104 struct mmc_data data;
105 u32 ctrl;
106 struct sdhci_host *host;
107 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
Michal Simek91e95ff2018-06-13 09:12:29 +0200108 char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530109 u8 deviceid;
110
111 debug("%s\n", __func__);
112
113 host = priv->host;
114 deviceid = priv->deviceid;
115
Faiz Abbas2eddc002019-06-11 00:43:40 +0530116 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530117 ctrl |= SDHCI_CTRL_EXEC_TUNING;
Faiz Abbas2eddc002019-06-11 00:43:40 +0530118 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530119
120 mdelay(1);
121
122 arasan_zynqmp_dll_reset(host, deviceid);
123
124 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
125 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
126
127 do {
128 cmd.cmdidx = opcode;
129 cmd.resp_type = MMC_RSP_R1;
130 cmd.cmdarg = 0;
131
132 data.blocksize = 64;
133 data.blocks = 1;
134 data.flags = MMC_DATA_READ;
135
136 if (tuning_loop_counter-- == 0)
137 break;
138
139 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
140 mmc->bus_width == 8)
141 data.blocksize = 128;
142
143 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
144 data.blocksize),
145 SDHCI_BLOCK_SIZE);
146 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
147 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
148
149 mmc_send_cmd(mmc, &cmd, NULL);
Faiz Abbas2eddc002019-06-11 00:43:40 +0530150 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530151
152 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
153 udelay(1);
154
155 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
156
157 if (tuning_loop_counter < 0) {
158 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
Faiz Abbas2eddc002019-06-11 00:43:40 +0530159 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530160 }
161
162 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
163 printf("%s:Tuning failed\n", __func__);
164 return -1;
165 }
166
167 udelay(1);
168 arasan_zynqmp_dll_reset(host, deviceid);
169
170 /* Enable only interrupts served by the SD controller */
171 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
172 SDHCI_INT_ENABLE);
173 /* Mask all sdhci interrupt sources */
174 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
175
176 return 0;
177}
178
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600179/**
180 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
181 *
182 * Set the SD Output Clock Tap Delays for Output path
183 *
184 * @host: Pointer to the sdhci_host structure.
185 * @degrees: The clock phase shift between 0 - 359.
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600186 * Return: 0
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600187 */
188static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
189 int degrees)
190{
191 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
192 struct mmc *mmc = (struct mmc *)host->mmc;
193 u8 tap_delay, tap_max = 0;
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600194 int timing = mode2timing[mmc->selected_mode];
195
196 /*
197 * This is applicable for SDHCI_SPEC_300 and above
198 * ZynqMP does not set phase for <=25MHz clock.
199 * If degrees is zero, no need to do anything.
200 */
Ashok Reddy Soma6f645382021-07-09 05:53:40 -0600201 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600202 return 0;
203
204 switch (timing) {
205 case MMC_TIMING_MMC_HS:
206 case MMC_TIMING_SD_HS:
207 case MMC_TIMING_UHS_SDR25:
208 case MMC_TIMING_UHS_DDR50:
209 case MMC_TIMING_MMC_DDR52:
210 /* For 50MHz clock, 30 Taps are available */
211 tap_max = 30;
212 break;
213 case MMC_TIMING_UHS_SDR50:
214 /* For 100MHz clock, 15 Taps are available */
215 tap_max = 15;
216 break;
217 case MMC_TIMING_UHS_SDR104:
218 case MMC_TIMING_MMC_HS200:
219 /* For 200MHz clock, 8 Taps are available */
220 tap_max = 8;
221 default:
222 break;
223 }
224
225 tap_delay = (degrees * tap_max) / 360;
226
227 arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
228
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600229 return 0;
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600230}
231
232/**
233 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
234 *
235 * Set the SD Input Clock Tap Delays for Input path
236 *
237 * @host: Pointer to the sdhci_host structure.
238 * @degrees: The clock phase shift between 0 - 359.
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600239 * Return: 0
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600240 */
241static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
242 int degrees)
243{
244 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
245 struct mmc *mmc = (struct mmc *)host->mmc;
246 u8 tap_delay, tap_max = 0;
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600247 int timing = mode2timing[mmc->selected_mode];
248
249 /*
250 * This is applicable for SDHCI_SPEC_300 and above
251 * ZynqMP does not set phase for <=25MHz clock.
252 * If degrees is zero, no need to do anything.
253 */
Ashok Reddy Soma6f645382021-07-09 05:53:40 -0600254 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600255 return 0;
256
257 switch (timing) {
258 case MMC_TIMING_MMC_HS:
259 case MMC_TIMING_SD_HS:
260 case MMC_TIMING_UHS_SDR25:
261 case MMC_TIMING_UHS_DDR50:
262 case MMC_TIMING_MMC_DDR52:
263 /* For 50MHz clock, 120 Taps are available */
264 tap_max = 120;
265 break;
266 case MMC_TIMING_UHS_SDR50:
267 /* For 100MHz clock, 60 Taps are available */
268 tap_max = 60;
269 break;
270 case MMC_TIMING_UHS_SDR104:
271 case MMC_TIMING_MMC_HS200:
272 /* For 200MHz clock, 30 Taps are available */
273 tap_max = 30;
274 default:
275 break;
276 }
277
278 tap_delay = (degrees * tap_max) / 360;
279
280 arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
281
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600282 return 0;
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600283}
284
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600285/**
286 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
287 *
288 * Set the SD Output Clock Tap Delays for Output path
289 *
290 * @host: Pointer to the sdhci_host structure.
291 * @degrees The clock phase shift between 0 - 359.
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600292 * Return: 0
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600293 */
294static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
295 int degrees)
296{
297 struct mmc *mmc = (struct mmc *)host->mmc;
298 u8 tap_delay, tap_max = 0;
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600299 int timing = mode2timing[mmc->selected_mode];
300
301 /*
302 * This is applicable for SDHCI_SPEC_300 and above
303 * Versal does not set phase for <=25MHz clock.
304 * If degrees is zero, no need to do anything.
305 */
Ashok Reddy Soma6f645382021-07-09 05:53:40 -0600306 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600307 return 0;
308
309 switch (timing) {
310 case MMC_TIMING_MMC_HS:
311 case MMC_TIMING_SD_HS:
312 case MMC_TIMING_UHS_SDR25:
313 case MMC_TIMING_UHS_DDR50:
314 case MMC_TIMING_MMC_DDR52:
315 /* For 50MHz clock, 30 Taps are available */
316 tap_max = 30;
317 break;
318 case MMC_TIMING_UHS_SDR50:
319 /* For 100MHz clock, 15 Taps are available */
320 tap_max = 15;
321 break;
322 case MMC_TIMING_UHS_SDR104:
323 case MMC_TIMING_MMC_HS200:
324 /* For 200MHz clock, 8 Taps are available */
325 tap_max = 8;
326 default:
327 break;
328 }
329
330 tap_delay = (degrees * tap_max) / 360;
331
332 /* Set the Clock Phase */
333 if (tap_delay) {
334 u32 regval;
335
336 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
337 regval |= SDHCI_OTAPDLY_ENABLE;
338 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
339 regval |= tap_delay;
340 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
341 }
342
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600343 return 0;
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600344}
345
346/**
347 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
348 *
349 * Set the SD Input Clock Tap Delays for Input path
350 *
351 * @host: Pointer to the sdhci_host structure.
352 * @degrees The clock phase shift between 0 - 359.
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600353 * Return: 0
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600354 */
355static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
356 int degrees)
357{
358 struct mmc *mmc = (struct mmc *)host->mmc;
359 u8 tap_delay, tap_max = 0;
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600360 int timing = mode2timing[mmc->selected_mode];
361
362 /*
363 * This is applicable for SDHCI_SPEC_300 and above
364 * Versal does not set phase for <=25MHz clock.
365 * If degrees is zero, no need to do anything.
366 */
Ashok Reddy Soma6f645382021-07-09 05:53:40 -0600367 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600368 return 0;
369
370 switch (timing) {
371 case MMC_TIMING_MMC_HS:
372 case MMC_TIMING_SD_HS:
373 case MMC_TIMING_UHS_SDR25:
374 case MMC_TIMING_UHS_DDR50:
375 case MMC_TIMING_MMC_DDR52:
376 /* For 50MHz clock, 120 Taps are available */
377 tap_max = 120;
378 break;
379 case MMC_TIMING_UHS_SDR50:
380 /* For 100MHz clock, 60 Taps are available */
381 tap_max = 60;
382 break;
383 case MMC_TIMING_UHS_SDR104:
384 case MMC_TIMING_MMC_HS200:
385 /* For 200MHz clock, 30 Taps are available */
386 tap_max = 30;
387 default:
388 break;
389 }
390
391 tap_delay = (degrees * tap_max) / 360;
392
393 /* Set the Clock Phase */
394 if (tap_delay) {
395 u32 regval;
396
397 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
398 regval |= SDHCI_ITAPDLY_CHGWIN;
399 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
400 regval |= SDHCI_ITAPDLY_ENABLE;
401 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
402 regval |= tap_delay;
403 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
404 regval &= ~SDHCI_ITAPDLY_CHGWIN;
405 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
406 }
407
Ashok Reddy Soma94a755d2021-07-09 05:53:39 -0600408 return 0;
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600409}
410
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530411static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
412{
413 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600414 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530415 struct mmc *mmc = (struct mmc *)host->mmc;
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600416 struct udevice *dev = mmc->dev;
417 u8 timing = mode2timing[mmc->selected_mode];
418 u32 iclk_phase = clk_data->clk_phase_in[timing];
419 u32 oclk_phase = clk_data->clk_phase_out[timing];
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530420
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600421 dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530422
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600423 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
424 device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
425 sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
426 sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600427 } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
428 device_is_compatible(dev, "xlnx,versal-8.9a")) {
429 sdhci_versal_sampleclk_set_phase(host, iclk_phase);
430 sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
Ashok Reddy Soma8f629862020-10-23 04:59:01 -0600431 }
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530432}
433
Michal Simek33a6b772020-10-23 04:59:00 -0600434static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
435 const char *prop)
436{
437 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
438 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
439 u32 clk_phase[2] = {0};
440
441 /*
442 * Read Tap Delay values from DT, if the DT does not contain the
443 * Tap Values then use the pre-defined values
444 */
445 if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
446 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
447 prop, clk_data->clk_phase_in[timing],
448 clk_data->clk_phase_out[timing]);
449 return;
450 }
451
452 /* The values read are Input and Output Clock Delays in order */
453 clk_data->clk_phase_in[timing] = clk_phase[0];
454 clk_data->clk_phase_out[timing] = clk_phase[1];
455}
456
457/**
458 * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
459 *
460 * Called at initialization to parse the values of Tap Delays.
461 *
462 * @dev: Pointer to our struct udevice.
463 */
464static void arasan_dt_parse_clk_phases(struct udevice *dev)
465{
466 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
467 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
468 int i;
469
470 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
471 device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
472 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
473 clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
474 clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
475 }
476
477 if (priv->bank == MMC_BANK2) {
478 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
479 clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
480 }
481 }
482
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600483 if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
484 device_is_compatible(dev, "xlnx,versal-8.9a")) {
485 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
486 clk_data->clk_phase_in[i] = versal_iclk_phases[i];
487 clk_data->clk_phase_out[i] = versal_oclk_phases[i];
488 }
489 }
490
Michal Simek33a6b772020-10-23 04:59:00 -0600491 arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
492 "clk-phase-legacy");
493 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
494 "clk-phase-mmc-hs");
495 arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
496 "clk-phase-sd-hs");
497 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
498 "clk-phase-uhs-sdr12");
499 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
500 "clk-phase-uhs-sdr25");
501 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
502 "clk-phase-uhs-sdr50");
503 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
504 "clk-phase-uhs-sdr104");
505 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
506 "clk-phase-uhs-ddr50");
507 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
508 "clk-phase-mmc-ddr52");
509 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
510 "clk-phase-mmc-hs200");
511 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
512 "clk-phase-mmc-hs400");
513}
514
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530515static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
516{
517 struct mmc *mmc = (struct mmc *)host->mmc;
518 u32 reg;
519
Siva Durga Prasad Paladugued9c0122018-05-29 20:03:11 +0530520 if (!IS_SD(mmc))
521 return;
522
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530523 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
Faiz Abbas2eddc002019-06-11 00:43:40 +0530524 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
525 reg |= SDHCI_CTRL_VDD_180;
526 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530527 }
528
529 if (mmc->selected_mode > SD_HS &&
Ashok Reddy Soma4179ee82020-10-23 04:59:03 -0600530 mmc->selected_mode <= MMC_HS_200)
Faiz Abbas2eddc002019-06-11 00:43:40 +0530531 sdhci_set_uhs_timing(host);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530532}
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530533
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530534const struct sdhci_ops arasan_ops = {
Michal Simeke232bd72020-09-14 13:00:40 +0200535 .platform_execute_tuning = &arasan_sdhci_execute_tuning,
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530536 .set_delay = &arasan_sdhci_set_tapdelay,
537 .set_control_reg = &arasan_sdhci_set_control_reg,
538};
539#endif
540
Michal Simek9ecd2682015-11-30 16:13:03 +0100541static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek0dd222b2013-04-22 14:56:49 +0200542{
Simon Glassfa20e932020-12-03 16:55:20 -0700543 struct arasan_sdhci_plat *plat = dev_get_plat(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +0100544 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530545 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
546 struct sdhci_host *host;
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100547 struct clk clk;
548 unsigned long clock;
Simon Glass4cc87fb2016-07-05 17:10:15 -0600549 int ret;
Michal Simek0dd222b2013-04-22 14:56:49 +0200550
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530551 host = priv->host;
552
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100553 ret = clk_get_by_index(dev, 0, &clk);
554 if (ret < 0) {
555 dev_err(dev, "failed to get clock\n");
556 return ret;
557 }
558
559 clock = clk_get_rate(&clk);
560 if (IS_ERR_VALUE(clock)) {
561 dev_err(dev, "failed to get rate\n");
562 return clock;
563 }
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530564
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100565 debug("%s: CLK %ld\n", __func__, clock);
566
567 ret = clk_enable(&clk);
Michal Simek41710952021-02-09 15:28:15 +0100568 if (ret) {
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100569 dev_err(dev, "failed to enable clock\n");
570 return ret;
571 }
572
Siva Durga Prasad Paladugu049e0032014-07-08 15:31:04 +0530573 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladugu0d6891b2014-01-22 09:17:09 +0100574 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugua1619fe2016-01-12 15:12:16 +0530575
576#ifdef CONFIG_ZYNQ_HISPD_BROKEN
Hannes Schmelzer94a5bbc2018-03-07 08:00:57 +0100577 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
Siva Durga Prasad Paladugua1619fe2016-01-12 15:12:16 +0530578#endif
579
Ashok Reddy Soma61e0df92020-10-23 04:58:57 -0600580 if (priv->no_1p8)
581 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
582
Benedikt Grassl529e6f02020-04-14 07:32:12 +0200583 plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
584
585 ret = mmc_of_parse(dev, &plat->cfg);
586 if (ret)
587 return ret;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530588
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100589 host->max_clk = clock;
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100590
Matwey V. Kornilov194b8602019-08-01 18:00:05 +0300591 host->mmc = &plat->mmc;
592 host->mmc->dev = dev;
593 host->mmc->priv = host;
594
Benedikt Grassl529e6f02020-04-14 07:32:12 +0200595 ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900596 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
Simon Glass4cc87fb2016-07-05 17:10:15 -0600597 if (ret)
598 return ret;
Simon Glass4cc87fb2016-07-05 17:10:15 -0600599 upriv->mmc = host->mmc;
Michal Simek9ecd2682015-11-30 16:13:03 +0100600
Simon Glass4cc87fb2016-07-05 17:10:15 -0600601 return sdhci_probe(dev);
Michal Simek0dd222b2013-04-22 14:56:49 +0200602}
Michal Simek9ecd2682015-11-30 16:13:03 +0100603
Simon Glassaad29ae2020-12-03 16:55:21 -0700604static int arasan_sdhci_of_to_plat(struct udevice *dev)
Michal Simek9ecd2682015-11-30 16:13:03 +0100605{
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530606 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +0100607
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530608 priv->host = calloc(1, sizeof(struct sdhci_host));
609 if (!priv->host)
610 return -1;
611
612 priv->host->name = dev->name;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530613
Ashok Reddy Soma568edfd2020-10-23 04:59:02 -0600614#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530615 priv->host->ops = &arasan_ops;
Michal Simek33a6b772020-10-23 04:59:00 -0600616 arasan_dt_parse_clk_phases(dev);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530617#endif
Michal Simek9ecd2682015-11-30 16:13:03 +0100618
Michal Simek921a8de2018-05-16 10:57:07 +0200619 priv->host->ioaddr = (void *)dev_read_addr(dev);
620 if (IS_ERR(priv->host->ioaddr))
621 return PTR_ERR(priv->host->ioaddr);
622
623 priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
Michal Simeke40ae572020-07-22 17:46:31 +0200624 priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
Ashok Reddy Soma61e0df92020-10-23 04:58:57 -0600625 priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +0100626
Michal Simek9ecd2682015-11-30 16:13:03 +0100627 return 0;
628}
629
Simon Glass4cc87fb2016-07-05 17:10:15 -0600630static int arasan_sdhci_bind(struct udevice *dev)
631{
Simon Glassfa20e932020-12-03 16:55:20 -0700632 struct arasan_sdhci_plat *plat = dev_get_plat(dev);
Simon Glass4cc87fb2016-07-05 17:10:15 -0600633
Masahiro Yamadacdb67f32016-09-06 22:17:32 +0900634 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass4cc87fb2016-07-05 17:10:15 -0600635}
636
Michal Simek9ecd2682015-11-30 16:13:03 +0100637static const struct udevice_id arasan_sdhci_ids[] = {
638 { .compatible = "arasan,sdhci-8.9a" },
639 { }
640};
641
642U_BOOT_DRIVER(arasan_sdhci_drv) = {
643 .name = "arasan_sdhci",
644 .id = UCLASS_MMC,
645 .of_match = arasan_sdhci_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700646 .of_to_plat = arasan_sdhci_of_to_plat,
Simon Glass4cc87fb2016-07-05 17:10:15 -0600647 .ops = &sdhci_ops,
648 .bind = arasan_sdhci_bind,
Michal Simek9ecd2682015-11-30 16:13:03 +0100649 .probe = arasan_sdhci_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700650 .priv_auto = sizeof(struct arasan_sdhci_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -0700651 .plat_auto = sizeof(struct arasan_sdhci_plat),
Michal Simek9ecd2682015-11-30 16:13:03 +0100652};