blob: 998a38450680ca0bf08ff0f72ffe2e4db9e6341b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek0dd222b2013-04-22 14:56:49 +02002/*
Michal Simek9ecd2682015-11-30 16:13:03 +01003 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek0dd222b2013-04-22 14:56:49 +02004 *
5 * Xilinx Zynq SD Host Controller Interface
Michal Simek0dd222b2013-04-22 14:56:49 +02006 */
7
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +01008#include <clk.h>
Michal Simek0dd222b2013-04-22 14:56:49 +02009#include <common.h>
Michal Simek9ecd2682015-11-30 16:13:03 +010010#include <dm.h>
Michal Simekc57ba042014-02-24 11:16:31 +010011#include <fdtdec.h>
Simon Glassdbd79542020-05-10 11:40:11 -060012#include <linux/delay.h>
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053013#include "mmc_private.h"
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070016#include <linux/err.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090017#include <linux/libfdt.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020018#include <malloc.h>
19#include <sdhci.h>
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053020#include <zynqmp_tap_delay.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020021
Michal Simek5b5101e2020-10-23 04:58:59 -060022#define SDHCI_TUNING_LOOP_COUNT 40
23
Simon Glass4cc87fb2016-07-05 17:10:15 -060024struct arasan_sdhci_plat {
25 struct mmc_config cfg;
26 struct mmc mmc;
27};
28
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053029struct arasan_sdhci_priv {
30 struct sdhci_host *host;
31 u8 deviceid;
32 u8 bank;
Ashok Reddy Soma61e0df92020-10-23 04:58:57 -060033 u8 no_1p8;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053034};
35
36#if defined(CONFIG_ARCH_ZYNQMP)
37static const u8 mode2timing[] = {
Ashok Reddy Soma0afdfe32020-10-23 04:58:58 -060038 [MMC_LEGACY] = MMC_TIMING_LEGACY,
39 [MMC_HS] = MMC_TIMING_MMC_HS,
40 [SD_HS] = MMC_TIMING_SD_HS,
41 [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
42 [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
43 [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
44 [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
45 [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
46 [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
47 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
48 [MMC_HS_200] = MMC_TIMING_MMC_HS200,
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053049};
50
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053051static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
52{
53 u16 clk;
54 unsigned long timeout;
55
56 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
57 clk &= ~(SDHCI_CLOCK_CARD_EN);
58 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
59
60 /* Issue DLL Reset */
61 zynqmp_dll_reset(deviceid);
62
63 /* Wait max 20 ms */
64 timeout = 100;
65 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
66 & SDHCI_CLOCK_INT_STABLE)) {
67 if (timeout == 0) {
68 dev_err(mmc_dev(host->mmc),
69 ": Internal clock never stabilised.\n");
70 return;
71 }
72 timeout--;
73 udelay(1000);
74 }
75
76 clk |= SDHCI_CLOCK_CARD_EN;
77 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
78}
79
80static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
81{
82 struct mmc_cmd cmd;
83 struct mmc_data data;
84 u32 ctrl;
85 struct sdhci_host *host;
86 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
Michal Simek91e95ff2018-06-13 09:12:29 +020087 char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053088 u8 deviceid;
89
90 debug("%s\n", __func__);
91
92 host = priv->host;
93 deviceid = priv->deviceid;
94
Faiz Abbas2eddc002019-06-11 00:43:40 +053095 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053096 ctrl |= SDHCI_CTRL_EXEC_TUNING;
Faiz Abbas2eddc002019-06-11 00:43:40 +053097 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +053098
99 mdelay(1);
100
101 arasan_zynqmp_dll_reset(host, deviceid);
102
103 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
104 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
105
106 do {
107 cmd.cmdidx = opcode;
108 cmd.resp_type = MMC_RSP_R1;
109 cmd.cmdarg = 0;
110
111 data.blocksize = 64;
112 data.blocks = 1;
113 data.flags = MMC_DATA_READ;
114
115 if (tuning_loop_counter-- == 0)
116 break;
117
118 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
119 mmc->bus_width == 8)
120 data.blocksize = 128;
121
122 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
123 data.blocksize),
124 SDHCI_BLOCK_SIZE);
125 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
126 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
127
128 mmc_send_cmd(mmc, &cmd, NULL);
Faiz Abbas2eddc002019-06-11 00:43:40 +0530129 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530130
131 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
132 udelay(1);
133
134 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
135
136 if (tuning_loop_counter < 0) {
137 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
Faiz Abbas2eddc002019-06-11 00:43:40 +0530138 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530139 }
140
141 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
142 printf("%s:Tuning failed\n", __func__);
143 return -1;
144 }
145
146 udelay(1);
147 arasan_zynqmp_dll_reset(host, deviceid);
148
149 /* Enable only interrupts served by the SD controller */
150 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
151 SDHCI_INT_ENABLE);
152 /* Mask all sdhci interrupt sources */
153 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
154
155 return 0;
156}
157
158static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
159{
160 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
161 struct mmc *mmc = (struct mmc *)host->mmc;
162 u8 uhsmode;
163
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530164 uhsmode = mode2timing[mmc->selected_mode];
165
166 if (uhsmode >= UHS_SDR25_BUS_SPEED)
167 arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
168 priv->bank);
169}
170
171static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
172{
173 struct mmc *mmc = (struct mmc *)host->mmc;
174 u32 reg;
175
Siva Durga Prasad Paladugued9c0122018-05-29 20:03:11 +0530176 if (!IS_SD(mmc))
177 return;
178
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530179 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
Faiz Abbas2eddc002019-06-11 00:43:40 +0530180 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
181 reg |= SDHCI_CTRL_VDD_180;
182 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530183 }
184
185 if (mmc->selected_mode > SD_HS &&
Faiz Abbas2eddc002019-06-11 00:43:40 +0530186 mmc->selected_mode <= UHS_DDR50)
187 sdhci_set_uhs_timing(host);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530188}
189#endif
190
Siva Durga Prasad Paladugu9a8ce6a2019-08-02 16:46:26 +0530191#if defined(CONFIG_ARCH_ZYNQMP)
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530192const struct sdhci_ops arasan_ops = {
Michal Simeke232bd72020-09-14 13:00:40 +0200193 .platform_execute_tuning = &arasan_sdhci_execute_tuning,
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530194 .set_delay = &arasan_sdhci_set_tapdelay,
195 .set_control_reg = &arasan_sdhci_set_control_reg,
196};
197#endif
198
Michal Simek9ecd2682015-11-30 16:13:03 +0100199static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek0dd222b2013-04-22 14:56:49 +0200200{
Simon Glass4cc87fb2016-07-05 17:10:15 -0600201 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +0100202 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530203 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
204 struct sdhci_host *host;
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100205 struct clk clk;
206 unsigned long clock;
Simon Glass4cc87fb2016-07-05 17:10:15 -0600207 int ret;
Michal Simek0dd222b2013-04-22 14:56:49 +0200208
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530209 host = priv->host;
210
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100211 ret = clk_get_by_index(dev, 0, &clk);
212 if (ret < 0) {
213 dev_err(dev, "failed to get clock\n");
214 return ret;
215 }
216
217 clock = clk_get_rate(&clk);
218 if (IS_ERR_VALUE(clock)) {
219 dev_err(dev, "failed to get rate\n");
220 return clock;
221 }
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530222
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100223 debug("%s: CLK %ld\n", __func__, clock);
224
225 ret = clk_enable(&clk);
226 if (ret && ret != -ENOSYS) {
227 dev_err(dev, "failed to enable clock\n");
228 return ret;
229 }
230
Siva Durga Prasad Paladugu049e0032014-07-08 15:31:04 +0530231 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladugu0d6891b2014-01-22 09:17:09 +0100232 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugua1619fe2016-01-12 15:12:16 +0530233
234#ifdef CONFIG_ZYNQ_HISPD_BROKEN
Hannes Schmelzer94a5bbc2018-03-07 08:00:57 +0100235 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
Siva Durga Prasad Paladugua1619fe2016-01-12 15:12:16 +0530236#endif
237
Ashok Reddy Soma61e0df92020-10-23 04:58:57 -0600238 if (priv->no_1p8)
239 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
240
Benedikt Grassl529e6f02020-04-14 07:32:12 +0200241 plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
242
243 ret = mmc_of_parse(dev, &plat->cfg);
244 if (ret)
245 return ret;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530246
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +0100247 host->max_clk = clock;
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100248
Matwey V. Kornilov194b8602019-08-01 18:00:05 +0300249 host->mmc = &plat->mmc;
250 host->mmc->dev = dev;
251 host->mmc->priv = host;
252
Benedikt Grassl529e6f02020-04-14 07:32:12 +0200253 ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900254 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
Simon Glass4cc87fb2016-07-05 17:10:15 -0600255 if (ret)
256 return ret;
Simon Glass4cc87fb2016-07-05 17:10:15 -0600257 upriv->mmc = host->mmc;
Michal Simek9ecd2682015-11-30 16:13:03 +0100258
Simon Glass4cc87fb2016-07-05 17:10:15 -0600259 return sdhci_probe(dev);
Michal Simek0dd222b2013-04-22 14:56:49 +0200260}
Michal Simek9ecd2682015-11-30 16:13:03 +0100261
262static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
263{
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530264 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +0100265
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530266 priv->host = calloc(1, sizeof(struct sdhci_host));
267 if (!priv->host)
268 return -1;
269
270 priv->host->name = dev->name;
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530271
Siva Durga Prasad Paladugu9a8ce6a2019-08-02 16:46:26 +0530272#if defined(CONFIG_ARCH_ZYNQMP)
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530273 priv->host->ops = &arasan_ops;
274#endif
Michal Simek9ecd2682015-11-30 16:13:03 +0100275
Michal Simek921a8de2018-05-16 10:57:07 +0200276 priv->host->ioaddr = (void *)dev_read_addr(dev);
277 if (IS_ERR(priv->host->ioaddr))
278 return PTR_ERR(priv->host->ioaddr);
279
280 priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
Michal Simeke40ae572020-07-22 17:46:31 +0200281 priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
Ashok Reddy Soma61e0df92020-10-23 04:58:57 -0600282 priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +0100283
Michal Simek9ecd2682015-11-30 16:13:03 +0100284 return 0;
285}
286
Simon Glass4cc87fb2016-07-05 17:10:15 -0600287static int arasan_sdhci_bind(struct udevice *dev)
288{
289 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Simon Glass4cc87fb2016-07-05 17:10:15 -0600290
Masahiro Yamadacdb67f32016-09-06 22:17:32 +0900291 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass4cc87fb2016-07-05 17:10:15 -0600292}
293
Michal Simek9ecd2682015-11-30 16:13:03 +0100294static const struct udevice_id arasan_sdhci_ids[] = {
295 { .compatible = "arasan,sdhci-8.9a" },
296 { }
297};
298
299U_BOOT_DRIVER(arasan_sdhci_drv) = {
300 .name = "arasan_sdhci",
301 .id = UCLASS_MMC,
302 .of_match = arasan_sdhci_ids,
303 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
Simon Glass4cc87fb2016-07-05 17:10:15 -0600304 .ops = &sdhci_ops,
305 .bind = arasan_sdhci_bind,
Michal Simek9ecd2682015-11-30 16:13:03 +0100306 .probe = arasan_sdhci_probe,
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530307 .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
Simon Glass4cc87fb2016-07-05 17:10:15 -0600308 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
Michal Simek9ecd2682015-11-30 16:13:03 +0100309};