Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000-2005 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 6 | */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/processor.h> |
Stefan Roese | a5d182e | 2007-08-14 14:44:41 +0200 | [diff] [blame] | 10 | #include <asm/io.h> |
| 11 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 12 | DECLARE_GLOBAL_DATA_PTR; |
| 13 | |
Stefan Roese | a5d182e | 2007-08-14 14:44:41 +0200 | [diff] [blame] | 14 | long int spd_sdram(void); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 15 | |
| 16 | int board_early_init_f(void) |
| 17 | { |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 18 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| 19 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ |
| 20 | mtdcr(UIC0CR, 0x00000010); |
| 21 | mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */ |
| 22 | mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ |
| 23 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 24 | |
Stefan Roese | a5d182e | 2007-08-14 14:44:41 +0200 | [diff] [blame] | 25 | /* |
| 26 | * Configure CPC0_PCI to enable PerWE as output |
| 27 | * and enable the internal PCI arbiter if selected |
| 28 | */ |
| 29 | if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 30 | mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); |
Stefan Roese | a5d182e | 2007-08-14 14:44:41 +0200 | [diff] [blame] | 31 | else |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 32 | mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN); |
Stefan Roese | a5d182e | 2007-08-14 14:44:41 +0200 | [diff] [blame] | 33 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 34 | return 0; |
| 35 | } |
| 36 | |
| 37 | /* |
| 38 | * Check Board Identity: |
| 39 | */ |
| 40 | int checkboard(void) |
| 41 | { |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 42 | char buf[64]; |
| 43 | int i = getenv_f("serial#", buf, sizeof(buf)); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 44 | |
| 45 | puts("Board: Bubinga - AMCC PPC405EP Evaluation Board"); |
| 46 | |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 47 | if (i > 0) { |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 48 | puts(", serial# "); |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 49 | puts(buf); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 50 | } |
| 51 | putc('\n'); |
| 52 | |
| 53 | return (0); |
| 54 | } |
| 55 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 56 | /* ------------------------------------------------------------------------- |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 57 | dram_init() reads EEPROM via I2c. EEPROM contains all of |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 58 | the necessary info for SDRAM controller configuration |
| 59 | ------------------------------------------------------------------------- */ |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 60 | int dram_init(void) |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 61 | { |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 62 | gd->ram_size = spd_sdram(); |
| 63 | |
| 64 | return 0; |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 65 | } |