blob: c73424d8c6f795b53adc044fd8968026b3606625 [file] [log] [blame]
Stefan Roese3e1f1b32005-08-01 16:49:12 +02001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese3e1f1b32005-08-01 16:49:12 +02006 */
Stefan Roese3e1f1b32005-08-01 16:49:12 +02007
8#include <common.h>
9#include <asm/processor.h>
Stefan Roesea5d182e2007-08-14 14:44:41 +020010#include <asm/io.h>
11
Simon Glass39f90ba2017-03-31 08:40:25 -060012DECLARE_GLOBAL_DATA_PTR;
13
Stefan Roesea5d182e2007-08-14 14:44:41 +020014long int spd_sdram(void);
Stefan Roese3e1f1b32005-08-01 16:49:12 +020015
16int board_early_init_f(void)
17{
Stefan Roese707fd362009-09-24 09:55:50 +020018 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
19 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
20 mtdcr(UIC0CR, 0x00000010);
21 mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */
22 mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
23 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
Stefan Roese3e1f1b32005-08-01 16:49:12 +020024
Stefan Roesea5d182e2007-08-14 14:44:41 +020025 /*
26 * Configure CPC0_PCI to enable PerWE as output
27 * and enable the internal PCI arbiter if selected
28 */
29 if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
Stefan Roese918010a2009-09-09 16:25:29 +020030 mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
Stefan Roesea5d182e2007-08-14 14:44:41 +020031 else
Stefan Roese918010a2009-09-09 16:25:29 +020032 mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
Stefan Roesea5d182e2007-08-14 14:44:41 +020033
Stefan Roese3e1f1b32005-08-01 16:49:12 +020034 return 0;
35}
36
37/*
38 * Check Board Identity:
39 */
40int checkboard(void)
41{
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000042 char buf[64];
43 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roese3e1f1b32005-08-01 16:49:12 +020044
45 puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
46
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000047 if (i > 0) {
Stefan Roese3e1f1b32005-08-01 16:49:12 +020048 puts(", serial# ");
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000049 puts(buf);
Stefan Roese3e1f1b32005-08-01 16:49:12 +020050 }
51 putc('\n');
52
53 return (0);
54}
55
Stefan Roese3e1f1b32005-08-01 16:49:12 +020056/* -------------------------------------------------------------------------
Simon Glassd35f3382017-04-06 12:47:05 -060057 dram_init() reads EEPROM via I2c. EEPROM contains all of
Stefan Roese3e1f1b32005-08-01 16:49:12 +020058 the necessary info for SDRAM controller configuration
59 ------------------------------------------------------------------------- */
Simon Glassd35f3382017-04-06 12:47:05 -060060int dram_init(void)
Stefan Roese3e1f1b32005-08-01 16:49:12 +020061{
Simon Glass39f90ba2017-03-31 08:40:25 -060062 gd->ram_size = spd_sdram();
63
64 return 0;
Stefan Roese3e1f1b32005-08-01 16:49:12 +020065}