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git01.mediatek.com / filogic / uboot / 6ec97d2ea4f105068ce4d553692e10399695ca26 / . / arch / powerpc / include / asm / cache.h
blob: 20c52fcddcff5a6bd239b9f1058c9760cb107380 [file] [log] [blame]
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]1/*
2 * include/asm-ppc/cache.h
3 */
4#ifndef __ARCH_PPC_CACHE_H
5#define __ARCH_PPC_CACHE_H
6
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]7#include <asm/processor.h>
8
9/* bytes per L1 cache line */
Heiko Schocher65d94db2017-06-07 17:33:09 +0200[diff] [blame]10#if defined(CONFIG_PPC64BRIDGE)
Stefan Roeseeff3a0a2007-10-31 17:55:58 +0100[diff] [blame]11#define L1_CACHE_SHIFT 7
Kumar Gala9f4a6892008-10-23 01:47:38 -0500[diff] [blame]12#elif defined(CONFIG_E500MC)
13#define L1_CACHE_SHIFT 6
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]14#else
Stefan Roeseeff3a0a2007-10-31 17:55:58 +0100[diff] [blame]15#define L1_CACHE_SHIFT 5
Kumar Gala938e14e2008-01-08 01:22:21 -0600[diff] [blame]16#endif
Stefan Roeseeff3a0a2007-10-31 17:55:58 +0100[diff] [blame]17
18#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
19
20/*
Anton Staaf265766c2011-10-17 16:46:06 -0700[diff] [blame]21 * Use the L1 data cache line size value for the minimum DMA buffer alignment
22 * on PowerPC.
23 */
24#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
25
26/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]27 * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
Stefan Roeseeff3a0a2007-10-31 17:55:58 +0100[diff] [blame]28 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]29#ifndef CONFIG_SYS_CACHELINE_SIZE
30#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
Stefan Roeseeff3a0a2007-10-31 17:55:58 +0100[diff] [blame]31#endif
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]32
33#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
34#define L1_CACHE_PAGES 8
35
36#define SMP_CACHE_BYTES L1_CACHE_BYTES
37
38#ifdef MODULE
39#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
40#else
41#define __cacheline_aligned \
42 __attribute__((__aligned__(L1_CACHE_BYTES), \
43 __section__(".data.cacheline_aligned")))
44#endif
45
46#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
47extern void flush_dcache_range(unsigned long start, unsigned long stop);
48extern void clean_dcache_range(unsigned long start, unsigned long stop);
49extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
Stefan Roeseeff3a0a2007-10-31 17:55:58 +0100[diff] [blame]50extern void flush_dcache(void);
51extern void invalidate_dcache(void);
Kumar Gala32090b32008-09-22 14:11:10 -0500[diff] [blame]52extern void invalidate_icache(void);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]53#ifdef CONFIG_SYS_INIT_RAM_LOCK
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]54extern void unlock_ram_in_cache(void);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]55#endif /* CONFIG_SYS_INIT_RAM_LOCK */
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]56#endif /* __ASSEMBLY__ */
57
Tang Yuantianefd6da62014-07-04 17:39:26 +0800[diff] [blame]58#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
59int l2cache_init(void);
60void enable_cpc(void);
61void disable_cpc_sram(void);
62#endif
63
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]64/* prep registers for L2 */
65#define CACHECRBA 0x80000823 /* Cache configuration register address */
66#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
67#define L2CACHE_512KB 0x00 /* 512KB */
68#define L2CACHE_256KB 0x01 /* 256KB */
69#define L2CACHE_1MB 0x02 /* 1MB */
70#define L2CACHE_NONE 0x03 /* NONE */
71#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
72
wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]73#endif