blob: 9ed6c1e67680ac4acc61a106712c3689bf797183 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard73ef2f02017-12-12 09:49:44 +01002/*
3 * Copyright (C) STMicroelectronics SA 2017
Patrice Chotard5d9950d2020-12-02 18:47:30 +01004 * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotard73ef2f02017-12-12 09:49:44 +01005 */
6
7#include <common.h>
8#include <dm.h>
Simon Glassed38aef2020-05-10 11:40:03 -06009#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Patrice Chotard73ef2f02017-12-12 09:49:44 +010013
14#include <asm/io.h>
15#include <asm/arch/stm32.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19int dram_init(void)
20{
21 int rv;
22 struct udevice *dev;
23
24 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
25 if (rv) {
26 debug("DRAM init failed: %d\n", rv);
27 return rv;
28 }
29
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053030 if (fdtdec_setup_mem_size_base() != 0)
Patrice Chotard73ef2f02017-12-12 09:49:44 +010031 rv = -EINVAL;
32
33 return rv;
34}
35
36int dram_init_banksize(void)
37{
38 fdtdec_setup_memory_banksize();
39
40 return 0;
41}
42
Patrice Chotard73ef2f02017-12-12 09:49:44 +010043int board_init(void)
44{
Patrice Chotard73ef2f02017-12-12 09:49:44 +010045 return 0;
46}
47
48#ifdef CONFIG_MISC_INIT_R
49int misc_init_r(void)
50{
51 char serialno[25];
52 u32 u_id_low, u_id_mid, u_id_high;
53
54 if (!env_get("serial#")) {
55 u_id_low = readl(&STM32_U_ID->u_id_low);
56 u_id_mid = readl(&STM32_U_ID->u_id_mid);
57 u_id_high = readl(&STM32_U_ID->u_id_high);
58 sprintf(serialno, "%08x%08x%08x",
59 u_id_high, u_id_mid, u_id_low);
60 env_set("serial#", serialno);
61 }
62
63 return 0;
64}
65#endif