blob: 74134b03ee6cafaa09d3e107dfcb3109797a41b5 [file] [log] [blame]
Green Wan2e5da522021-05-27 06:52:13 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2020-2021 SiFive, Inc
4 *
5 * Authors:
6 * Pragnesh Patel <pragnesh.patel@sifive.com>
7 */
8
9#include <init.h>
10#include <spl.h>
11#include <misc.h>
12#include <log.h>
Zong Li93b9de62021-06-30 23:23:50 +080013#include <fdtdec.h>
14#include <dm/root.h>
Green Wan2e5da522021-05-27 06:52:13 -070015#include <linux/delay.h>
16#include <linux/io.h>
17#include <asm/gpio.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/spl.h>
Zong Li93b9de62021-06-30 23:23:50 +080020#include <asm/arch/eeprom.h>
Green Wan2e5da522021-05-27 06:52:13 -070021
22#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
23
24#define MODE_SELECT_REG 0x1000
25#define MODE_SELECT_SD 0xb
26#define MODE_SELECT_MASK GENMASK(3, 0)
27
28int spl_board_init_f(void)
29{
30 int ret;
31
Zong Li93b9de62021-06-30 23:23:50 +080032#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
33 int rescan;
34
35 ret = fdtdec_resetup(&rescan);
36 if (!ret && rescan) {
37 dm_uninit();
38 dm_init_and_scan(true);
39 }
40#endif
41
Green Wan2e5da522021-05-27 06:52:13 -070042 ret = spl_soc_init();
43 if (ret) {
44 debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
45 return ret;
46 }
47
48 /*
49 * GEMGXL init VSC8541 PHY reset sequence;
50 * leave pull-down active for 2ms
51 */
52 udelay(2000);
53 ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
54 if (ret) {
55 debug("gem_phy_reset gpio request failed: %d\n", ret);
56 return ret;
57 }
58
59 /* Set GPIO 12 (PHY NRESET) */
60 ret = gpio_direction_output(GEM_PHY_RESET, 1);
61 if (ret) {
62 debug("gem_phy_reset gpio direction set failed: %d\n", ret);
63 return ret;
64 }
65
66 udelay(1);
67
68 /* Reset PHY again to enter unmanaged mode */
69 gpio_set_value(GEM_PHY_RESET, 0);
70 udelay(1);
71 gpio_set_value(GEM_PHY_RESET, 1);
72 mdelay(15);
73
74 return 0;
75}
76
77u32 spl_boot_device(void)
78{
79 u32 mode_select = readl((void *)MODE_SELECT_REG);
80 u32 boot_device = mode_select & MODE_SELECT_MASK;
81
82 switch (boot_device) {
83 case MODE_SELECT_SD:
84 return BOOT_DEVICE_MMC1;
85 default:
86 debug("Unsupported boot device 0x%x but trying MMC1\n",
87 boot_device);
88 return BOOT_DEVICE_MMC1;
89 }
90}
91
92#ifdef CONFIG_SPL_LOAD_FIT
93int board_fit_config_name_match(const char *name)
94{
Zong Li93b9de62021-06-30 23:23:50 +080095 /*
96 * Apply different DDR params on different board revision.
97 * Use PCB revision which is byte 0x7 in I2C platform EEPROM
98 * to distinguish that.
99 */
100 if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3 &&
101 !strcmp(name, "hifive-unmatched-a00"))
102 return 0;
103 else if (get_pcb_revision_from_eeprom() != PCB_REVISION_REV3 &&
104 !strcmp(name, "hifive-unmatched-a00-rev1"))
105 return 0;
106
107 return -1;
Green Wan2e5da522021-05-27 06:52:13 -0700108}
109#endif