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git01.mediatek.com / filogic / uboot / 6c7727723a4e930a5aa9c6e898f650774d66337a / . / configs / socfpga_sr1500_defconfig
blob: c48bbb0e9c340901c5449f69b72cb879722634f9 [file] [log] [blame]
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_SOCFPGA=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]3CONFIG_TARGET_SOCFPGA_SR1500=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]4CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]5CONFIG_SPL_TEXT_BASE=0xFFFF0000
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]6CONFIG_DISTRO_DEFAULTS=y
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]7CONFIG_FIT=y
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]8# CONFIG_USE_BOOTCOMMAND is not set
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]9CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Simon Glassac3ee422016-10-17 20:12:59 -0600[diff] [blame]10CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
Simon Glass217652f2016-10-17 20:12:58 -0600[diff] [blame]11CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]12CONFIG_SYS_CONSOLE_INFO_QUIET=y
Tom Rini79f4eea2017-05-01 11:41:11 -0400[diff] [blame]13CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]14CONFIG_VERSION_VARIABLE=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]15# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]16CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]17CONFIG_BOARD_EARLY_INIT_F=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]18CONFIG_SPL_SPI_LOAD=y
Hannes Schmelzer38df9972019-08-22 15:41:46 +0200[diff] [blame]19CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]20CONFIG_CMD_ASKENV=y
21CONFIG_CMD_GREPENV=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]22CONFIG_CMD_MEMTEST=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]23# CONFIG_CMD_FLASH is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]24CONFIG_CMD_GPIO=y
25CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]26CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]27CONFIG_CMD_SF=y
28CONFIG_CMD_SPI=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]29CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]30CONFIG_CMD_TIME=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]31CONFIG_CMD_EXT4_WRITE=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]32CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
33CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
Heiko Schocher09dbb852016-09-21 07:58:19 +0200[diff] [blame]34CONFIG_CMD_UBI=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]35# CONFIG_ISO_PARTITION is not set
36# CONFIG_EFI_PARTITION is not set
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]37CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]38CONFIG_ENV_IS_IN_SPI_FLASH=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]39CONFIG_SPL_DM_SEQ_ALIAS=y
Lukasz Majewski6dd8c902018-02-09 23:50:57 +0100[diff] [blame]40CONFIG_BOOTCOUNT_LIMIT=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]41CONFIG_DM_GPIO=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]42CONFIG_DWAPB_GPIO=y
Dinh Nguyena75fcc12018-04-04 17:18:21 -0500[diff] [blame]43CONFIG_DM_I2C=y
Stefan Roese78077b62016-04-28 09:47:18 +0200[diff] [blame]44CONFIG_SYS_I2C_DW=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]45CONFIG_DM_MMC=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]46CONFIG_MMC_DW=y
Adam Fordac44a302018-07-07 22:18:22 -0500[diff] [blame]47CONFIG_MTD_DEVICE=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]48CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]49CONFIG_SF_DEFAULT_SPEED=100000000
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]50CONFIG_SPI_FLASH_STMICRO=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]51# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
Frieder Schrempfd7be62c2019-10-23 07:41:20 +0000[diff] [blame]52CONFIG_SPI_FLASH_MTD=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]53CONFIG_PHY_MARVELL=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]54CONFIG_DM_ETH=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]55CONFIG_PHY_GIGE=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]56CONFIG_ETH_DESIGNWARE=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]57CONFIG_MII=y
Dinh Nguyenbfddbb22018-04-04 17:18:25 -0500[diff] [blame]58CONFIG_DM_RESET=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]59CONFIG_SPI=y
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]60CONFIG_CADENCE_QSPI=y
Simon Goldschmidtfe6275f2019-10-05 22:10:11 +0200[diff] [blame]61# CONFIG_SPL_WDT is not set