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git01.mediatek.com / filogic / uboot / 6bb8f55ae89ab1e245b84d6a96a85dc7813719f9 / . / configs / fennec-rk3288_defconfig
blob: 96a07defce642ec969e603e6572c8d024aa7c5b0 [file] [log] [blame]
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
Philipp Tomsich798370f2017-06-29 11:21:15 +0200[diff] [blame]5CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]6CONFIG_TARGET_FENNEC_RK3288=y
7CONFIG_SPL_STACK_R_ADDR=0x80000
8CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]9CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]10# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]11CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]12CONFIG_CONSOLE_MUX=y
13# CONFIG_DISPLAY_CPUINFO is not set
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]14CONFIG_SPL_STACK_R=y
15CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]16CONFIG_FASTBOOT_FLASH=y
17CONFIG_FASTBOOT_FLASH_MMC_DEV=0
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]18# CONFIG_CMD_IMLS is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]19CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]20CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]21CONFIG_CMD_I2C=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]22CONFIG_CMD_MMC=y
23CONFIG_CMD_SF=y
24CONFIG_CMD_SPI=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]25CONFIG_CMD_USB=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]26# CONFIG_CMD_SETEXPR is not set
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]27CONFIG_CMD_CACHE=y
28CONFIG_CMD_TIME=y
29CONFIG_CMD_PMIC=y
30CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]31# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]32# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]33# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]34CONFIG_SPL_PARTITION_UUIDS=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]35CONFIG_SPL_OF_CONTROL=y
36CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]37CONFIG_ENV_IS_IN_MMC=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]38CONFIG_REGMAP=y
39CONFIG_SPL_REGMAP=y
40CONFIG_SYSCON=y
41CONFIG_SPL_SYSCON=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]42# CONFIG_SPL_SIMPLE_BUS is not set
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]43CONFIG_CLK=y
44CONFIG_SPL_CLK=y
45CONFIG_ROCKCHIP_GPIO=y
46CONFIG_SYS_I2C_ROCKCHIP=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]47CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]48CONFIG_MMC_DW_ROCKCHIP=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]49CONFIG_DM_ETH=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]50CONFIG_ETH_DESIGNWARE=y
51CONFIG_GMAC_ROCKCHIP=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]52CONFIG_PINCTRL=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]53CONFIG_SPL_PINCTRL=y
54# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]55CONFIG_PINCTRL_ROCKCHIP_RK3288=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]56CONFIG_DM_PMIC=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]57CONFIG_PMIC_RK8XX=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]58CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]59CONFIG_REGULATOR_RK8XX=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]60CONFIG_PWM_ROCKCHIP=y
61CONFIG_RAM=y
62CONFIG_SPL_RAM=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]63CONFIG_DEBUG_UART_BASE=0xff690000
64CONFIG_DEBUG_UART_CLOCK=24000000
65CONFIG_DEBUG_UART_SHIFT=2
66CONFIG_SYS_NS16550=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]67CONFIG_SYSRESET=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]68CONFIG_USB=y
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]69CONFIG_USB_DWC2=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]70CONFIG_USB_STORAGE=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]71CONFIG_USB_GADGET=y
72CONFIG_USB_GADGET_DWC2_OTG=y
73CONFIG_USB_GADGET_DOWNLOAD=y
74CONFIG_G_DNL_MANUFACTURER="Rockchip"
75CONFIG_G_DNL_VENDOR_NUM=0x2207
76CONFIG_G_DNL_PRODUCT_NUM=0x320a
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]77CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]78CONFIG_USB_ETHER_ASIX=y
79CONFIG_USB_ETHER_SMSC95XX=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]80CONFIG_USE_TINY_PRINTF=y
81CONFIG_CMD_DHRYSTONE=y
82CONFIG_ERRNO_STR=y