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git01.mediatek.com / filogic / uboot / 732870909d2c87b4cbec213e824e2172726e8001 / . / configs / fennec-rk3288_defconfig
blob: a42cd9cb93cb7568375b58f67a9df007ed446f66 [file] [log] [blame]
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]5CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]6CONFIG_TARGET_FENNEC_RK3288=y
7CONFIG_SPL_STACK_R_ADDR=0x80000
8CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]9CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]10CONFIG_CONSOLE_MUX=y
11# CONFIG_DISPLAY_CPUINFO is not set
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]12CONFIG_SPL_STACK_R=y
13CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]14# CONFIG_CMD_IMLS is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame^]15CONFIG_CMD_GPT=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]16CONFIG_CMD_MMC=y
17CONFIG_CMD_SF=y
18CONFIG_CMD_SPI=y
19CONFIG_CMD_I2C=y
20CONFIG_CMD_GPIO=y
21# CONFIG_CMD_SETEXPR is not set
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]22CONFIG_CMD_CACHE=y
23CONFIG_CMD_TIME=y
24CONFIG_CMD_PMIC=y
25CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]26# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]27# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]28# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame^]29CONFIG_SPL_PARTITION_UUIDS=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]30CONFIG_SPL_OF_CONTROL=y
31CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
32CONFIG_REGMAP=y
33CONFIG_SPL_REGMAP=y
34CONFIG_SYSCON=y
35CONFIG_SPL_SYSCON=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]36# CONFIG_SPL_SIMPLE_BUS is not set
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]37CONFIG_CLK=y
38CONFIG_SPL_CLK=y
39CONFIG_ROCKCHIP_GPIO=y
40CONFIG_SYS_I2C_ROCKCHIP=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]41CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]42CONFIG_MMC_DW_ROCKCHIP=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]43CONFIG_PINCTRL=y
44# CONFIG_PINCTRL_FULL is not set
45CONFIG_SPL_PINCTRL=y
46# CONFIG_SPL_PINCTRL_FULL is not set
47CONFIG_ROCKCHIP_RK3288_PINCTRL=y
48CONFIG_DM_PMIC=y
49CONFIG_PMIC_RK808=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]50CONFIG_DM_REGULATOR_FIXED=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]51CONFIG_REGULATOR_RK808=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]52CONFIG_PWM_ROCKCHIP=y
53CONFIG_RAM=y
54CONFIG_SPL_RAM=y
55CONFIG_DEBUG_UART=y
56CONFIG_DEBUG_UART_BASE=0xff690000
57CONFIG_DEBUG_UART_CLOCK=24000000
58CONFIG_DEBUG_UART_SHIFT=2
59CONFIG_SYS_NS16550=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]60CONFIG_SYSRESET=y
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +0800[diff] [blame]61CONFIG_USE_TINY_PRINTF=y
62CONFIG_CMD_DHRYSTONE=y
63CONFIG_ERRNO_STR=y