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git01.mediatek.com / filogic / uboot / 6b731c9ae81d1dc180cb1c4ea5ad0c40cda6b69a / . / arch / arm / dts / rk3288.dtsi
blob: e51c75c150c6b8c7e940f108123f7ffea9d2e8f1 [file] [log] [blame]
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]1/*
2 * SPDX-License-Identifier: GPL-2.0+
3 */
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/pinctrl/rockchip.h>
9#include <dt-bindings/clock/rk3288-cru.h>
10#include <dt-bindings/power-domain/rk3288.h>
11#include <dt-bindings/thermal/thermal.h>
12#include "skeleton.dtsi"
13
14/ {
15 compatible = "rockchip,rk3288";
16
17 interrupt-parent = <&gic>;
18 aliases {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
23 gpio4 = &gpio4;
24 gpio5 = &gpio5;
25 gpio6 = &gpio6;
26 gpio7 = &gpio7;
27 gpio8 = &gpio8;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 i2c2 = &i2c2;
31 i2c3 = &i2c3;
32 i2c4 = &i2c4;
33 i2c5 = &i2c5;
34 mmc0 = &emmc;
35 mmc1 = &sdmmc;
36 mmc2 = &sdio0;
37 mmc3 = &sdio1;
38 mshc0 = &emmc;
39 mshc1 = &sdmmc;
40 mshc2 = &sdio0;
41 mshc3 = &sdio1;
42 serial0 = &uart0;
43 serial1 = &uart1;
44 serial2 = &uart2;
45 serial3 = &uart3;
46 serial4 = &uart4;
47 spi0 = &spi0;
48 spi1 = &spi1;
49 spi2 = &spi2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 enable-method = "rockchip,rk3066-smp";
56 rockchip,pmu = <&pmu>;
57
58 cpu0: cpu@500 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a12";
61 reg = <0x500>;
62 operating-points = <
63 /* KHz uV */
64 1800000 1400000
65 1704000 1350000
66 1608000 1300000
67 1512000 1250000
68 1416000 1200000
69 1200000 1100000
70 1008000 1050000
71 816000 1000000
72 696000 950000
73 600000 900000
74 408000 900000
75 216000 900000
76 126000 900000
77 >;
78 #cooling-cells = <2>; /* min followed by max */
79 clock-latency = <40000>;
80 clocks = <&cru ARMCLK>;
81 resets = <&cru SRST_CORE0>;
82 };
83 cpu@501 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a12";
86 reg = <0x501>;
87 resets = <&cru SRST_CORE1>;
88 };
89 cpu@502 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x502>;
93 resets = <&cru SRST_CORE2>;
94 };
95 cpu@503 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a12";
98 reg = <0x503>;
99 resets = <&cru SRST_CORE3>;
100 };
101 };
102
103 amba {
104 compatible = "arm,amba-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges;
108
109 dmac_peri: dma-controller@ff250000 {
110 compatible = "arm,pl330", "arm,primecell";
111 broken-no-flushp;
112 reg = <0xff250000 0x4000>;
113 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
115 #dma-cells = <1>;
116 clocks = <&cru ACLK_DMAC2>;
117 clock-names = "apb_pclk";
118 };
119
120 dmac_bus_ns: dma-controller@ff600000 {
121 compatible = "arm,pl330", "arm,primecell";
122 broken-no-flushp;
123 reg = <0xff600000 0x4000>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
126 #dma-cells = <1>;
127 clocks = <&cru ACLK_DMAC1>;
128 clock-names = "apb_pclk";
129 status = "disabled";
130 };
131
132 dmac_bus_s: dma-controller@ffb20000 {
133 compatible = "arm,pl330", "arm,primecell";
134 broken-no-flushp;
135 reg = <0xffb20000 0x4000>;
136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
138 #dma-cells = <1>;
139 clocks = <&cru ACLK_DMAC1>;
140 clock-names = "apb_pclk";
141 };
142 };
143
144 xin24m: oscillator {
145 compatible = "fixed-clock";
146 clock-frequency = <24000000>;
147 clock-output-names = "xin24m";
148 #clock-cells = <0>;
149 };
150
151 timer {
152 arm,use-physical-timer;
153 compatible = "arm,armv7-timer";
154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
158 clock-frequency = <24000000>;
159 always-on;
160 };
161
162 display-subsystem {
163 compatible = "rockchip,display-subsystem";
164 ports = <&vopl_out>, <&vopb_out>;
165 };
166
167 sdmmc: dwmmc@ff0c0000 {
168 compatible = "rockchip,rk3288-dw-mshc";
169 clock-freq-min-max = <400000 150000000>;
170 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
171 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
172 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
173 fifo-depth = <0x100>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 reg = <0xff0c0000 0x4000>;
176 status = "disabled";
177 };
178
179 sdio0: dwmmc@ff0d0000 {
180 compatible = "rockchip,rk3288-dw-mshc";
181 clock-freq-min-max = <400000 150000000>;
182 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
183 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
184 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
185 fifo-depth = <0x100>;
186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
187 reg = <0xff0d0000 0x4000>;
188 status = "disabled";
189 };
190
191 sdio1: dwmmc@ff0e0000 {
192 compatible = "rockchip,rk3288-dw-mshc";
193 clock-freq-min-max = <400000 150000000>;
194 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
195 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
196 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
197 fifo-depth = <0x100>;
198 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
199 reg = <0xff0e0000 0x4000>;
200 status = "disabled";
201 };
202
203 emmc: dwmmc@ff0f0000 {
204 compatible = "rockchip,rk3288-dw-mshc";
205 clock-freq-min-max = <400000 150000000>;
206 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
207 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
208 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
209 fifo-depth = <0x100>;
210 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
211 reg = <0xff0f0000 0x4000>;
212 status = "disabled";
213 };
214
215 saradc: saradc@ff100000 {
216 compatible = "rockchip,saradc";
217 reg = <0xff100000 0x100>;
218 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
219 #io-channel-cells = <1>;
220 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
221 clock-names = "saradc", "apb_pclk";
222 status = "disabled";
223 };
224
225 spi0: spi@ff110000 {
226 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
227 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
228 clock-names = "spiclk", "apb_pclk";
229 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
230 dma-names = "tx", "rx";
231 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
234 reg = <0xff110000 0x1000>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 status = "disabled";
238 };
239
240 spi1: spi@ff120000 {
241 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
242 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
243 clock-names = "spiclk", "apb_pclk";
244 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
245 dma-names = "tx", "rx";
246 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
249 reg = <0xff120000 0x1000>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 status = "disabled";
253 };
254
255 spi2: spi@ff130000 {
256 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
257 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
258 clock-names = "spiclk", "apb_pclk";
259 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
260 dma-names = "tx", "rx";
261 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
264 reg = <0xff130000 0x1000>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 i2c1: i2c@ff140000 {
271 compatible = "rockchip,rk3288-i2c";
272 reg = <0xff140000 0x1000>;
273 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
275 #size-cells = <0>;
276 clock-names = "i2c";
277 clocks = <&cru PCLK_I2C1>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c1_xfer>;
280 status = "disabled";
281 };
282
283 i2c3: i2c@ff150000 {
284 compatible = "rockchip,rk3288-i2c";
285 reg = <0xff150000 0x1000>;
286 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 clock-names = "i2c";
290 clocks = <&cru PCLK_I2C3>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c3_xfer>;
293 status = "disabled";
294 };
295
296 i2c4: i2c@ff160000 {
297 compatible = "rockchip,rk3288-i2c";
298 reg = <0xff160000 0x1000>;
299 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 clock-names = "i2c";
303 clocks = <&cru PCLK_I2C4>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c4_xfer>;
306 status = "disabled";
307 };
308
309 i2c5: i2c@ff170000 {
310 compatible = "rockchip,rk3288-i2c";
311 reg = <0xff170000 0x1000>;
312 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 clock-names = "i2c";
316 clocks = <&cru PCLK_I2C5>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&i2c5_xfer>;
319 status = "disabled";
320 };
321 uart0: serial@ff180000 {
322 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
323 reg = <0xff180000 0x100>;
324 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
325 reg-shift = <2>;
326 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]327 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]328 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
329 clock-names = "baudclk", "apb_pclk";
330 pinctrl-names = "default";
331 pinctrl-0 = <&uart0_xfer>;
332 status = "disabled";
333 };
334
335 uart1: serial@ff190000 {
336 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
337 reg = <0xff190000 0x100>;
338 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
339 reg-shift = <2>;
340 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]341 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]342 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
343 clock-names = "baudclk", "apb_pclk";
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart1_xfer>;
346 status = "disabled";
347 };
348
349 uart2: serial@ff690000 {
350 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
351 reg = <0xff690000 0x100>;
352 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
353 reg-shift = <2>;
354 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]355 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]356 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
357 clock-names = "baudclk", "apb_pclk";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart2_xfer>;
360 status = "disabled";
361 };
362 uart3: serial@ff1b0000 {
363 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
364 reg = <0xff1b0000 0x100>;
365 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
366 reg-shift = <2>;
367 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]368 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]369 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
370 clock-names = "baudclk", "apb_pclk";
371 pinctrl-names = "default";
372 pinctrl-0 = <&uart3_xfer>;
373 status = "disabled";
374 };
375
376 uart4: serial@ff1c0000 {
377 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
378 reg = <0xff1c0000 0x100>;
379 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
380 reg-shift = <2>;
381 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]382 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]383 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
384 clock-names = "baudclk", "apb_pclk";
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart4_xfer>;
387 status = "disabled";
388 };
389 thermal: thermal-zones {
390 #include "rk3288-thermal.dtsi"
391 };
392
393 tsadc: tsadc@ff280000 {
394 compatible = "rockchip,rk3288-tsadc";
395 reg = <0xff280000 0x100>;
396 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
398 clock-names = "tsadc", "apb_pclk";
399 resets = <&cru SRST_TSADC>;
400 reset-names = "tsadc-apb";
401 pinctrl-names = "otp_out";
402 pinctrl-0 = <&otp_out>;
403 #thermal-sensor-cells = <1>;
404 hw-shut-temp = <125000>;
405 status = "disabled";
406 };
407
408 gmac: ethernet@ff290000 {
409 compatible = "rockchip,rk3288-gmac";
410 reg = <0xff290000 0x10000>;
411 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
412 interrupt-names = "macirq";
413 rockchip,grf = <&grf>;
414 clocks = <&cru SCLK_MAC>,
415 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
416 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
417 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
418 clock-names = "stmmaceth",
419 "mac_clk_rx", "mac_clk_tx",
420 "clk_mac_ref", "clk_mac_refout",
421 "aclk_mac", "pclk_mac";
422 };
423
424 usb_host0_ehci: usb@ff500000 {
425 compatible = "generic-ehci";
426 reg = <0xff500000 0x100>;
427 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru HCLK_USBHOST0>;
429 clock-names = "usbhost";
430 phys = <&usbphy1>;
431 phy-names = "usb";
432 status = "disabled";
433 };
434
435 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
436
437 usb_host1: usb@ff540000 {
438 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
439 "snps,dwc2";
440 reg = <0xff540000 0x40000>;
441 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru HCLK_USBHOST1>;
443 clock-names = "otg";
444 phys = <&usbphy2>;
445 phy-names = "usb2-phy";
446 status = "disabled";
447 };
448
449 usb_otg: usb@ff580000 {
450 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
451 "snps,dwc2";
452 reg = <0xff580000 0x40000>;
453 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cru HCLK_OTG0>;
455 clock-names = "otg";
456 phys = <&usbphy0>;
457 phy-names = "usb2-phy";
458 status = "disabled";
459 };
460
461 usb_hsic: usb@ff5c0000 {
462 compatible = "generic-ehci";
463 reg = <0xff5c0000 0x100>;
464 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_HSIC>;
466 clock-names = "usbhost";
467 status = "disabled";
468 };
469
470 dmc: dmc@ff610000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]471 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]472 compatible = "rockchip,rk3288-dmc", "syscon";
473 rockchip,cru = <&cru>;
474 rockchip,grf = <&grf>;
475 rockchip,pmu = <&pmu>;
476 rockchip,sgrf = <&sgrf>;
477 rockchip,noc = <&noc>;
478 reg = <0xff610000 0x3fc
479 0xff620000 0x294
480 0xff630000 0x3fc
481 0xff640000 0x294>;
482 rockchip,sram = <&ddr_sram>;
483 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
484 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
485 <&cru ARMCLK>;
486 clock-names = "pclk_ddrupctl0", "pclk_publ0",
487 "pclk_ddrupctl1", "pclk_publ1",
488 "arm_clk";
489 };
490
491 i2c0: i2c@ff650000 {
492 compatible = "rockchip,rk3288-i2c";
493 reg = <0xff650000 0x1000>;
494 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
495 #address-cells = <1>;
496 #size-cells = <0>;
497 clock-names = "i2c";
498 clocks = <&cru PCLK_I2C0>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c0_xfer>;
501 status = "disabled";
502 };
503
504 i2c2: i2c@ff660000 {
505 compatible = "rockchip,rk3288-i2c";
506 reg = <0xff660000 0x1000>;
507 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clock-names = "i2c";
511 clocks = <&cru PCLK_I2C2>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2c2_xfer>;
514 status = "disabled";
515 };
516
517 pwm0: pwm@ff680000 {
518 compatible = "rockchip,rk3288-pwm";
519 reg = <0xff680000 0x10>;
520 #pwm-cells = <3>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pwm0_pin>;
523 clocks = <&cru PCLK_PWM>;
524 clock-names = "pwm";
525 rockchip,grf = <&grf>;
526 status = "disabled";
527 };
528
529 pwm1: pwm@ff680010 {
530 compatible = "rockchip,rk3288-pwm";
531 reg = <0xff680010 0x10>;
532 #pwm-cells = <3>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pwm1_pin>;
535 clocks = <&cru PCLK_PWM>;
536 clock-names = "pwm";
537 rockchip,grf = <&grf>;
538 status = "disabled";
539 };
540
541 pwm2: pwm@ff680020 {
542 compatible = "rockchip,rk3288-pwm";
543 reg = <0xff680020 0x10>;
544 #pwm-cells = <3>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pwm2_pin>;
547 clocks = <&cru PCLK_PWM>;
548 clock-names = "pwm";
549 rockchip,grf = <&grf>;
550 status = "disabled";
551 };
552
553 pwm3: pwm@ff680030 {
554 compatible = "rockchip,rk3288-pwm";
555 reg = <0xff680030 0x10>;
556 #pwm-cells = <2>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pwm3_pin>;
559 clocks = <&cru PCLK_PWM>;
560 clock-names = "pwm";
561 rockchip,grf = <&grf>;
562 status = "disabled";
563 };
564
565 bus_intmem@ff700000 {
566 compatible = "mmio-sram";
567 reg = <0xff700000 0x18000>;
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges = <0 0xff700000 0x18000>;
571 smp-sram@0 {
572 compatible = "rockchip,rk3066-smp-sram";
573 reg = <0x00 0x10>;
574 };
575 ddr_sram: ddr-sram@1000 {
576 compatible = "rockchip,rk3288-ddr-sram";
577 reg = <0x1000 0x4000>;
578 };
579 };
580
581 sram@ff720000 {
582 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
583 reg = <0xff720000 0x1000>;
584 };
585
586 pmu: power-management@ff730000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]587 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]588 compatible = "rockchip,rk3288-pmu", "syscon";
589 reg = <0xff730000 0x100>;
590 };
591
592 sgrf: syscon@ff740000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]593 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]594 compatible = "rockchip,rk3288-sgrf", "syscon";
595 reg = <0xff740000 0x1000>;
596 };
597
598 cru: clock-controller@ff760000 {
599 compatible = "rockchip,rk3288-cru";
600 reg = <0xff760000 0x1000>;
601 rockchip,grf = <&grf>;
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]602 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]603 #clock-cells = <1>;
604 #reset-cells = <1>;
605 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
606 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
607 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
608 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
609 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
610 <&cru PCLK_PERI>;
611 assigned-clock-rates = <0>, <0>,
612 <594000000>, <400000000>,
613 <500000000>, <300000000>,
614 <150000000>, <75000000>,
615 <300000000>, <150000000>,
616 <75000000>;
617 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
618 };
619
620 grf: syscon@ff770000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]621 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]622 compatible = "rockchip,rk3288-grf", "syscon";
623 reg = <0xff770000 0x1000>;
624 };
625
626 wdt: watchdog@ff800000 {
627 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
628 reg = <0xff800000 0x100>;
629 clocks = <&cru PCLK_WDT>;
630 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
631 status = "disabled";
632 };
633
Simon Glass15019802016-01-21 19:45:21 -0700[diff] [blame]634 spdif: sound@ff88b0000 {
635 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
636 reg = <0xff8b0000 0x10000>;
637 #sound-dai-cells = <0>;
638 clock-names = "hclk", "mclk";
639 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
640 dmas = <&dmac_bus_s 3>;
641 dma-names = "tx";
642 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&spdif_tx>;
645 rockchip,grf = <&grf>;
646 status = "disabled";
647 };
648
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]649 i2s: i2s@ff890000 {
650 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
651 reg = <0xff890000 0x10000>;
652 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
653 #address-cells = <1>;
654 #size-cells = <0>;
655 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
656 dma-names = "tx", "rx";
657 clock-names = "i2s_hclk", "i2s_clk";
658 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&i2s0_bus>;
661 status = "disabled";
662 };
663
664 vopb: vop@ff930000 {
665 compatible = "rockchip,rk3288-vop";
666 reg = <0xff930000 0x19c>;
667 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
669 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
670 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
671 reset-names = "axi", "ahb", "dclk";
672 iommus = <&vopb_mmu>;
673 power-domains = <&power RK3288_PD_VIO>;
674 status = "disabled";
675 vopb_out: port {
676 #address-cells = <1>;
677 #size-cells = <0>;
678 vopb_out_edp: endpoint@0 {
679 reg = <0>;
680 remote-endpoint = <&edp_in_vopb>;
681 };
682 vopb_out_hdmi: endpoint@1 {
683 reg = <1>;
684 remote-endpoint = <&hdmi_in_vopb>;
685 };
686 };
687 };
688
689 vopb_mmu: iommu@ff930300 {
690 compatible = "rockchip,iommu";
691 reg = <0xff930300 0x100>;
692 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-names = "vopb_mmu";
694 power-domains = <&power RK3288_PD_VIO>;
695 #iommu-cells = <0>;
696 status = "disabled";
697 };
698
699 vopl: vop@ff940000 {
700 compatible = "rockchip,rk3288-vop";
701 reg = <0xff940000 0x19c>;
702 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
704 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
705 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
706 reset-names = "axi", "ahb", "dclk";
707 iommus = <&vopl_mmu>;
708 power-domains = <&power RK3288_PD_VIO>;
709 status = "disabled";
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]710 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]711 vopl_out: port {
712 #address-cells = <1>;
713 #size-cells = <0>;
714 vopl_out_edp: endpoint@0 {
715 reg = <0>;
716 remote-endpoint = <&edp_in_vopl>;
717 };
718 vopl_out_hdmi: endpoint@1 {
719 reg = <1>;
720 remote-endpoint = <&hdmi_in_vopl>;
721 };
722
723 };
724 };
725
726 vopl_mmu: iommu@ff940300 {
727 compatible = "rockchip,iommu";
728 reg = <0xff940300 0x100>;
729 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
730 interrupt-names = "vopl_mmu";
731 power-domains = <&power RK3288_PD_VIO>;
732 #iommu-cells = <0>;
733 status = "disabled";
734 };
735
736 edp: edp@ff970000 {
737 compatible = "rockchip,rk3288-edp";
738 reg = <0xff970000 0x4000>;
739 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
741 rockchip,grf = <&grf>;
742 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
743 resets = <&cru 111>;
744 reset-names = "edp";
745 power-domains = <&power RK3288_PD_VIO>;
746 status = "disabled";
747 ports {
748 edp_in: port {
749 #address-cells = <1>;
750 #size-cells = <0>;
751 edp_in_vopb: endpoint@0 {
752 reg = <0>;
753 remote-endpoint = <&vopb_out_edp>;
754 };
755 edp_in_vopl: endpoint@1 {
756 reg = <1>;
757 remote-endpoint = <&vopl_out_edp>;
758 };
759 };
760 };
761 };
762
763 hdmi: hdmi@ff980000 {
764 compatible = "rockchip,rk3288-dw-hdmi";
765 reg = <0xff980000 0x20000>;
766 reg-io-width = <4>;
767 ddc-i2c-bus = <&i2c5>;
768 rockchip,grf = <&grf>;
769 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
771 clock-names = "iahb", "isfr";
772 status = "disabled";
773 ports {
774 hdmi_in: port {
775 #address-cells = <1>;
776 #size-cells = <0>;
777 hdmi_in_vopb: endpoint@0 {
778 reg = <0>;
779 remote-endpoint = <&vopb_out_hdmi>;
780 };
781 hdmi_in_vopl: endpoint@1 {
782 reg = <1>;
783 remote-endpoint = <&vopl_out_hdmi>;
784 };
785 };
786 };
787 };
788
789 hdmi_audio: hdmi_audio {
790 compatible = "rockchip,rk3288-hdmi-audio";
791 i2s-controller = <&i2s>;
792 status = "disable";
793 };
794
795 vpu: video-codec@ff9a0000 {
796 compatible = "rockchip,rk3288-vpu";
797 reg = <0xff9a0000 0x800>;
798 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
800 interrupt-names = "vepu", "vdpu";
801 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
802 clock-names = "aclk_vcodec", "hclk_vcodec";
803 power-domains = <&power RK3288_PD_VIDEO>;
804 iommus = <&vpu_mmu>;
805 };
806
807 vpu_mmu: iommu@ff9a0800 {
808 compatible = "rockchip,iommu";
809 reg = <0xff9a0800 0x100>;
810 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
811 interrupt-names = "vpu_mmu";
812 power-domains = <&power RK3288_PD_VIDEO>;
813 #iommu-cells = <0>;
814 };
815
816 gpu: gpu@ffa30000 {
817 compatible = "arm,malit764",
818 "arm,malit76x",
819 "arm,malit7xx",
820 "arm,mali-midgard";
821 reg = <0xffa30000 0x10000>;
822 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "JOB", "MMU", "GPU";
826 clocks = <&cru ACLK_GPU>;
827 clock-names = "aclk_gpu";
828 operating-points = <
829 /* KHz uV */
830 100000 950000
831 200000 950000
832 300000 1000000
833 400000 1100000
834 /* 500000 1200000 - See crosbug.com/p/33857 */
835 600000 1250000
836 >;
837 power-domains = <&power RK3288_PD_GPU>;
838 status = "disabled";
839 };
840
841 noc: syscon@ffac0000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]842 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]843 compatible = "rockchip,rk3288-noc", "syscon";
844 reg = <0xffac0000 0x2000>;
845 };
846
847 efuse: efuse@ffb40000 {
848 compatible = "rockchip,rk3288-efuse";
849 reg = <0xffb40000 0x10000>;
850 status = "disabled";
851 };
852
853 gic: interrupt-controller@ffc01000 {
854 compatible = "arm,gic-400";
855 interrupt-controller;
856 #interrupt-cells = <3>;
857 #address-cells = <0>;
858
859 reg = <0xffc01000 0x1000>,
860 <0xffc02000 0x1000>,
861 <0xffc04000 0x2000>,
862 <0xffc06000 0x2000>;
863 interrupts = <GIC_PPI 9 0xf04>;
864 };
865
866 cpuidle: cpuidle {
867 compatible = "rockchip,rk3288-cpuidle";
868 };
869
870 usbphy: phy {
871 compatible = "rockchip,rk3288-usb-phy";
872 rockchip,grf = <&grf>;
873 #address-cells = <1>;
874 #size-cells = <0>;
875 status = "disabled";
876
877 usbphy0: usb-phy0 {
878 #phy-cells = <0>;
879 reg = <0x320>;
880 clocks = <&cru SCLK_OTGPHY0>;
881 clock-names = "phyclk";
882 };
883
884 usbphy1: usb-phy1 {
885 #phy-cells = <0>;
886 reg = <0x334>;
887 clocks = <&cru SCLK_OTGPHY1>;
888 clock-names = "phyclk";
889 };
890
891 usbphy2: usb-phy2 {
892 #phy-cells = <0>;
893 reg = <0x348>;
894 clocks = <&cru SCLK_OTGPHY2>;
895 clock-names = "phyclk";
896 };
897 };
898
899 pinctrl: pinctrl {
900 compatible = "rockchip,rk3288-pinctrl";
901 rockchip,grf = <&grf>;
902 rockchip,pmu = <&pmu>;
903 #address-cells = <1>;
904 #size-cells = <1>;
905 ranges;
906
907 gpio0: gpio0@ff750000 {
908 compatible = "rockchip,gpio-bank";
909 reg = <0xff750000 0x100>;
910 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&cru PCLK_GPIO0>;
912
913 gpio-controller;
914 #gpio-cells = <2>;
915
916 interrupt-controller;
917 #interrupt-cells = <2>;
918 };
919
920 gpio1: gpio1@ff780000 {
921 compatible = "rockchip,gpio-bank";
922 reg = <0xff780000 0x100>;
923 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&cru PCLK_GPIO1>;
925
926 gpio-controller;
927 #gpio-cells = <2>;
928
929 interrupt-controller;
930 #interrupt-cells = <2>;
931 };
932
933 gpio2: gpio2@ff790000 {
934 compatible = "rockchip,gpio-bank";
935 reg = <0xff790000 0x100>;
936 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&cru PCLK_GPIO2>;
938
939 gpio-controller;
940 #gpio-cells = <2>;
941
942 interrupt-controller;
943 #interrupt-cells = <2>;
944 };
945
946 gpio3: gpio3@ff7a0000 {
947 compatible = "rockchip,gpio-bank";
948 reg = <0xff7a0000 0x100>;
949 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&cru PCLK_GPIO3>;
951
952 gpio-controller;
953 #gpio-cells = <2>;
954
955 interrupt-controller;
956 #interrupt-cells = <2>;
957 };
958
959 gpio4: gpio4@ff7b0000 {
960 compatible = "rockchip,gpio-bank";
961 reg = <0xff7b0000 0x100>;
962 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru PCLK_GPIO4>;
964
965 gpio-controller;
966 #gpio-cells = <2>;
967
968 interrupt-controller;
969 #interrupt-cells = <2>;
970 };
971
972 gpio5: gpio5@ff7c0000 {
973 compatible = "rockchip,gpio-bank";
974 reg = <0xff7c0000 0x100>;
975 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&cru PCLK_GPIO5>;
977
978 gpio-controller;
979 #gpio-cells = <2>;
980
981 interrupt-controller;
982 #interrupt-cells = <2>;
983 };
984
985 gpio6: gpio6@ff7d0000 {
986 compatible = "rockchip,gpio-bank";
987 reg = <0xff7d0000 0x100>;
988 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cru PCLK_GPIO6>;
990
991 gpio-controller;
992 #gpio-cells = <2>;
993
994 interrupt-controller;
995 #interrupt-cells = <2>;
996 };
997
998 gpio7: gpio7@ff7e0000 {
999 compatible = "rockchip,gpio-bank";
1000 reg = <0xff7e0000 0x100>;
1001 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cru PCLK_GPIO7>;
1003
1004 gpio-controller;
1005 #gpio-cells = <2>;
1006
1007 interrupt-controller;
1008 #interrupt-cells = <2>;
1009 };
1010
1011 gpio8: gpio8@ff7f0000 {
1012 compatible = "rockchip,gpio-bank";
1013 reg = <0xff7f0000 0x100>;
1014 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cru PCLK_GPIO8>;
1016
1017 gpio-controller;
1018 #gpio-cells = <2>;
1019
1020 interrupt-controller;
1021 #interrupt-cells = <2>;
1022 };
1023
1024 pcfg_pull_up: pcfg-pull-up {
1025 bias-pull-up;
1026 };
1027
1028 pcfg_pull_down: pcfg-pull-down {
1029 bias-pull-down;
1030 };
1031
1032 pcfg_pull_none: pcfg-pull-none {
1033 bias-disable;
1034 };
1035
1036 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1037 bias-disable;
1038 drive-strength = <12>;
1039 };
1040
1041 sleep {
1042 global_pwroff: global-pwroff {
1043 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1044 };
1045
1046 ddrio_pwroff: ddrio-pwroff {
1047 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1048 };
1049
1050 ddr0_retention: ddr0-retention {
1051 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1052 };
1053
1054 ddr1_retention: ddr1-retention {
1055 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1056 };
1057 };
1058
1059 i2c0 {
1060 i2c0_xfer: i2c0-xfer {
1061 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1062 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1063 };
1064 };
1065
1066 i2c1 {
1067 i2c1_xfer: i2c1-xfer {
1068 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1069 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1070 };
1071 };
1072
1073 i2c2 {
1074 i2c2_xfer: i2c2-xfer {
1075 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1076 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1077 };
1078 };
1079
1080 i2c3 {
1081 i2c3_xfer: i2c3-xfer {
1082 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1083 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1084 };
1085 };
1086
1087 i2c4 {
1088 i2c4_xfer: i2c4-xfer {
1089 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1090 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1091 };
1092 };
1093
1094 i2c5 {
1095 i2c5_xfer: i2c5-xfer {
1096 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1097 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1098 };
1099 };
1100
1101 i2s0 {
1102 i2s0_bus: i2s0-bus {
1103 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1104 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1105 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1106 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1107 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1108 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1109 };
1110 };
1111
1112 sdmmc {
1113 sdmmc_clk: sdmmc-clk {
1114 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1115 };
1116
1117 sdmmc_cmd: sdmmc-cmd {
1118 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1119 };
1120
1121 sdmmc_cd: sdmcc-cd {
1122 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1123 };
1124
1125 sdmmc_bus1: sdmmc-bus1 {
1126 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1127 };
1128
1129 sdmmc_bus4: sdmmc-bus4 {
1130 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1131 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1132 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1133 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1134 };
1135 };
1136
1137 sdio0 {
1138 sdio0_bus1: sdio0-bus1 {
1139 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1140 };
1141
1142 sdio0_bus4: sdio0-bus4 {
1143 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1144 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1145 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1146 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1147 };
1148
1149 sdio0_cmd: sdio0-cmd {
1150 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1151 };
1152
1153 sdio0_clk: sdio0-clk {
1154 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1155 };
1156
1157 sdio0_cd: sdio0-cd {
1158 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1159 };
1160
1161 sdio0_wp: sdio0-wp {
1162 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1163 };
1164
1165 sdio0_pwr: sdio0-pwr {
1166 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1167 };
1168
1169 sdio0_bkpwr: sdio0-bkpwr {
1170 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1171 };
1172
1173 sdio0_int: sdio0-int {
1174 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1175 };
1176 };
1177
1178 sdio1 {
1179 sdio1_bus1: sdio1-bus1 {
1180 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1181 };
1182
1183 sdio1_bus4: sdio1-bus4 {
1184 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1185 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1186 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1187 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1188 };
1189
1190 sdio1_cd: sdio1-cd {
1191 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1192 };
1193
1194 sdio1_wp: sdio1-wp {
1195 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1196 };
1197
1198 sdio1_bkpwr: sdio1-bkpwr {
1199 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1200 };
1201
1202 sdio1_int: sdio1-int {
1203 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1204 };
1205
1206 sdio1_cmd: sdio1-cmd {
1207 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1208 };
1209
1210 sdio1_clk: sdio1-clk {
1211 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1212 };
1213
1214 sdio1_pwr: sdio1-pwr {
1215 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1216 };
1217 };
1218
1219 emmc {
1220 emmc_clk: emmc-clk {
1221 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1222 };
1223
1224 emmc_cmd: emmc-cmd {
1225 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1226 };
1227
1228 emmc_pwr: emmc-pwr {
1229 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1230 };
1231
1232 emmc_bus1: emmc-bus1 {
1233 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1234 };
1235
1236 emmc_bus4: emmc-bus4 {
1237 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1238 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1239 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1240 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1241 };
1242
1243 emmc_bus8: emmc-bus8 {
1244 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1245 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1246 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1247 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1248 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1249 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1250 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1251 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1252 };
1253 };
1254
1255 spi0 {
1256 spi0_clk: spi0-clk {
1257 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1258 };
1259 spi0_cs0: spi0-cs0 {
1260 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1261 };
1262 spi0_tx: spi0-tx {
1263 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1264 };
1265 spi0_rx: spi0-rx {
1266 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1267 };
1268 spi0_cs1: spi0-cs1 {
1269 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1270 };
1271 };
1272 spi1 {
1273 spi1_clk: spi1-clk {
1274 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1275 };
1276 spi1_cs0: spi1-cs0 {
1277 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1278 };
1279 spi1_rx: spi1-rx {
1280 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1281 };
1282 spi1_tx: spi1-tx {
1283 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1284 };
1285 };
1286
1287 spi2 {
1288 spi2_cs1: spi2-cs1 {
1289 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1290 };
1291 spi2_clk: spi2-clk {
1292 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1293 };
1294 spi2_cs0: spi2-cs0 {
1295 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1296 };
1297 spi2_rx: spi2-rx {
1298 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1299 };
1300 spi2_tx: spi2-tx {
1301 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1302 };
1303 };
1304
1305 uart0 {
1306 uart0_xfer: uart0-xfer {
1307 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1308 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1309 };
1310
1311 uart0_cts: uart0-cts {
1312 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1313 };
1314
1315 uart0_rts: uart0-rts {
1316 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1317 };
1318 };
1319
1320 uart1 {
1321 uart1_xfer: uart1-xfer {
1322 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1323 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1324 };
1325
1326 uart1_cts: uart1-cts {
1327 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1328 };
1329
1330 uart1_rts: uart1-rts {
1331 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1332 };
1333 };
1334
1335 uart2 {
1336 uart2_xfer: uart2-xfer {
1337 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1338 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1339 };
1340 /* no rts / cts for uart2 */
1341 };
1342
1343 uart3 {
1344 uart3_xfer: uart3-xfer {
1345 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1346 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1347 };
1348
1349 uart3_cts: uart3-cts {
1350 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1351 };
1352
1353 uart3_rts: uart3-rts {
1354 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1355 };
1356 };
1357
1358 uart4 {
1359 uart4_xfer: uart4-xfer {
1360 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1361 <5 13 3 &pcfg_pull_none>;
1362 };
1363
1364 uart4_cts: uart4-cts {
1365 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1366 };
1367
1368 uart4_rts: uart4-rts {
1369 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1370 };
1371 };
1372
1373 tsadc {
1374 otp_out: otp-out {
1375 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1376 };
1377 };
1378
1379 pwm0 {
1380 pwm0_pin: pwm0-pin {
1381 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1382 };
1383 };
1384
1385 pwm1 {
1386 pwm1_pin: pwm1-pin {
1387 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1388 };
1389 };
1390
1391 pwm2 {
1392 pwm2_pin: pwm2-pin {
1393 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1394 };
1395 };
1396
1397 pwm3 {
1398 pwm3_pin: pwm3-pin {
1399 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1400 };
1401 };
1402
1403 gmac {
1404 rgmii_pins: rgmii-pins {
1405 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1406 <3 31 3 &pcfg_pull_none>,
1407 <3 26 3 &pcfg_pull_none>,
1408 <3 27 3 &pcfg_pull_none>,
1409 <3 28 3 &pcfg_pull_none_12ma>,
1410 <3 29 3 &pcfg_pull_none_12ma>,
1411 <3 24 3 &pcfg_pull_none_12ma>,
1412 <3 25 3 &pcfg_pull_none_12ma>,
1413 <4 0 3 &pcfg_pull_none>,
1414 <4 5 3 &pcfg_pull_none>,
1415 <4 6 3 &pcfg_pull_none>,
1416 <4 9 3 &pcfg_pull_none_12ma>,
1417 <4 4 3 &pcfg_pull_none_12ma>,
1418 <4 1 3 &pcfg_pull_none>,
1419 <4 3 3 &pcfg_pull_none>;
1420 };
1421
1422 rmii_pins: rmii-pins {
1423 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1424 <3 31 3 &pcfg_pull_none>,
1425 <3 28 3 &pcfg_pull_none>,
1426 <3 29 3 &pcfg_pull_none>,
1427 <4 0 3 &pcfg_pull_none>,
1428 <4 5 3 &pcfg_pull_none>,
1429 <4 4 3 &pcfg_pull_none>,
1430 <4 1 3 &pcfg_pull_none>,
1431 <4 2 3 &pcfg_pull_none>,
1432 <4 3 3 &pcfg_pull_none>;
1433 };
1434 };
Simon Glass15019802016-01-21 19:45:21 -0700[diff] [blame]1435
1436 spdif {
1437 spdif_tx: spdif-tx {
1438 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1439 };
1440 };
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]1441 };
1442
1443 power: power-controller {
1444 compatible = "rockchip,rk3288-power-controller";
1445 #power-domain-cells = <1>;
1446 rockchip,pmu = <&pmu>;
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1449
1450 pd_gpu {
1451 reg = <RK3288_PD_GPU>;
1452 clocks = <&cru ACLK_GPU>;
1453 };
1454
1455 pd_hevc {
1456 reg = <RK3288_PD_HEVC>;
1457 clocks = <&cru ACLK_HEVC>,
1458 <&cru SCLK_HEVC_CABAC>,
1459 <&cru SCLK_HEVC_CORE>,
1460 <&cru HCLK_HEVC>;
1461 };
1462
1463 pd_vio {
1464 reg = <RK3288_PD_VIO>;
1465 clocks = <&cru ACLK_IEP>,
1466 <&cru ACLK_ISP>,
1467 <&cru ACLK_RGA>,
1468 <&cru ACLK_VIP>,
1469 <&cru ACLK_VOP0>,
1470 <&cru ACLK_VOP1>,
1471 <&cru DCLK_VOP0>,
1472 <&cru DCLK_VOP1>,
1473 <&cru HCLK_IEP>,
1474 <&cru HCLK_ISP>,
1475 <&cru HCLK_RGA>,
1476 <&cru HCLK_VIP>,
1477 <&cru HCLK_VOP0>,
1478 <&cru HCLK_VOP1>,
1479 <&cru PCLK_EDP_CTRL>,
1480 <&cru PCLK_HDMI_CTRL>,
1481 <&cru PCLK_LVDS_PHY>,
1482 <&cru PCLK_MIPI_CSI>,
1483 <&cru PCLK_MIPI_DSI0>,
1484 <&cru PCLK_MIPI_DSI1>,
1485 <&cru SCLK_EDP_24M>,
1486 <&cru SCLK_EDP>,
1487 <&cru SCLK_HDMI_CEC>,
1488 <&cru SCLK_HDMI_HDCP>,
1489 <&cru SCLK_ISP_JPE>,
1490 <&cru SCLK_ISP>,
1491 <&cru SCLK_RGA>;
1492 };
1493
1494 pd_video {
1495 reg = <RK3288_PD_VIDEO>;
1496 clocks = <&cru ACLK_VCODEC>,
1497 <&cru HCLK_VCODEC>;
1498 };
1499 };
1500};