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git01.mediatek.com / filogic / uboot / 3386b376a776623d85e69bda590b12a7b51f7cfe / . / arch / arm / dts / rk3288.dtsi
blob: 0f497099679470ea39078d6ca9e5b1ae550995b0 [file] [log] [blame]
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]1/*
2 * SPDX-License-Identifier: GPL-2.0+
3 */
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/pinctrl/rockchip.h>
9#include <dt-bindings/clock/rk3288-cru.h>
10#include <dt-bindings/power-domain/rk3288.h>
11#include <dt-bindings/thermal/thermal.h>
12#include "skeleton.dtsi"
13
14/ {
15 compatible = "rockchip,rk3288";
16
17 interrupt-parent = <&gic>;
18 aliases {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame^]19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
23 gpio4 = &gpio4;
24 gpio5 = &gpio5;
25 gpio6 = &gpio6;
26 gpio7 = &gpio7;
27 gpio8 = &gpio8;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 i2c2 = &i2c2;
31 i2c3 = &i2c3;
32 i2c4 = &i2c4;
33 i2c5 = &i2c5;
34 mmc0 = &emmc;
35 mmc1 = &sdmmc;
36 mmc2 = &sdio0;
37 mmc3 = &sdio1;
38 mshc0 = &emmc;
39 mshc1 = &sdmmc;
40 mshc2 = &sdio0;
41 mshc3 = &sdio1;
42 serial0 = &uart0;
43 serial1 = &uart1;
44 serial2 = &uart2;
45 serial3 = &uart3;
46 serial4 = &uart4;
47 spi0 = &spi0;
48 spi1 = &spi1;
49 spi2 = &spi2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 enable-method = "rockchip,rk3066-smp";
56 rockchip,pmu = <&pmu>;
57
58 cpu0: cpu@500 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a12";
61 reg = <0x500>;
62 operating-points = <
63 /* KHz uV */
64 1800000 1400000
65 1704000 1350000
66 1608000 1300000
67 1512000 1250000
68 1416000 1200000
69 1200000 1100000
70 1008000 1050000
71 816000 1000000
72 696000 950000
73 600000 900000
74 408000 900000
75 216000 900000
76 126000 900000
77 >;
78 #cooling-cells = <2>; /* min followed by max */
79 clock-latency = <40000>;
80 clocks = <&cru ARMCLK>;
81 resets = <&cru SRST_CORE0>;
82 };
83 cpu@501 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a12";
86 reg = <0x501>;
87 resets = <&cru SRST_CORE1>;
88 };
89 cpu@502 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x502>;
93 resets = <&cru SRST_CORE2>;
94 };
95 cpu@503 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a12";
98 reg = <0x503>;
99 resets = <&cru SRST_CORE3>;
100 };
101 };
102
103 amba {
104 compatible = "arm,amba-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges;
108
109 dmac_peri: dma-controller@ff250000 {
110 compatible = "arm,pl330", "arm,primecell";
111 broken-no-flushp;
112 reg = <0xff250000 0x4000>;
113 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
115 #dma-cells = <1>;
116 clocks = <&cru ACLK_DMAC2>;
117 clock-names = "apb_pclk";
118 };
119
120 dmac_bus_ns: dma-controller@ff600000 {
121 compatible = "arm,pl330", "arm,primecell";
122 broken-no-flushp;
123 reg = <0xff600000 0x4000>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
126 #dma-cells = <1>;
127 clocks = <&cru ACLK_DMAC1>;
128 clock-names = "apb_pclk";
129 status = "disabled";
130 };
131
132 dmac_bus_s: dma-controller@ffb20000 {
133 compatible = "arm,pl330", "arm,primecell";
134 broken-no-flushp;
135 reg = <0xffb20000 0x4000>;
136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
138 #dma-cells = <1>;
139 clocks = <&cru ACLK_DMAC1>;
140 clock-names = "apb_pclk";
141 };
142 };
143
144 xin24m: oscillator {
145 compatible = "fixed-clock";
146 clock-frequency = <24000000>;
147 clock-output-names = "xin24m";
148 #clock-cells = <0>;
149 };
150
151 timer {
152 arm,use-physical-timer;
153 compatible = "arm,armv7-timer";
154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
158 clock-frequency = <24000000>;
159 always-on;
160 };
161
162 display-subsystem {
163 compatible = "rockchip,display-subsystem";
164 ports = <&vopl_out>, <&vopb_out>;
165 };
166
167 sdmmc: dwmmc@ff0c0000 {
168 compatible = "rockchip,rk3288-dw-mshc";
169 clock-freq-min-max = <400000 150000000>;
170 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
171 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
172 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
173 fifo-depth = <0x100>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 reg = <0xff0c0000 0x4000>;
176 status = "disabled";
177 };
178
179 sdio0: dwmmc@ff0d0000 {
180 compatible = "rockchip,rk3288-dw-mshc";
181 clock-freq-min-max = <400000 150000000>;
182 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
183 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
184 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
185 fifo-depth = <0x100>;
186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
187 reg = <0xff0d0000 0x4000>;
188 status = "disabled";
189 };
190
191 sdio1: dwmmc@ff0e0000 {
192 compatible = "rockchip,rk3288-dw-mshc";
193 clock-freq-min-max = <400000 150000000>;
194 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
195 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
196 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
197 fifo-depth = <0x100>;
198 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
199 reg = <0xff0e0000 0x4000>;
200 status = "disabled";
201 };
202
203 emmc: dwmmc@ff0f0000 {
204 compatible = "rockchip,rk3288-dw-mshc";
205 clock-freq-min-max = <400000 150000000>;
206 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
207 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
208 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
209 fifo-depth = <0x100>;
210 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
211 reg = <0xff0f0000 0x4000>;
212 status = "disabled";
213 };
214
215 saradc: saradc@ff100000 {
216 compatible = "rockchip,saradc";
217 reg = <0xff100000 0x100>;
218 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
219 #io-channel-cells = <1>;
220 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
221 clock-names = "saradc", "apb_pclk";
222 status = "disabled";
223 };
224
225 spi0: spi@ff110000 {
226 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
227 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
228 clock-names = "spiclk", "apb_pclk";
229 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
230 dma-names = "tx", "rx";
231 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
234 reg = <0xff110000 0x1000>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 status = "disabled";
238 };
239
240 spi1: spi@ff120000 {
241 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
242 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
243 clock-names = "spiclk", "apb_pclk";
244 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
245 dma-names = "tx", "rx";
246 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
249 reg = <0xff120000 0x1000>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 status = "disabled";
253 };
254
255 spi2: spi@ff130000 {
256 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
257 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
258 clock-names = "spiclk", "apb_pclk";
259 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
260 dma-names = "tx", "rx";
261 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
264 reg = <0xff130000 0x1000>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 i2c1: i2c@ff140000 {
271 compatible = "rockchip,rk3288-i2c";
272 reg = <0xff140000 0x1000>;
273 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
275 #size-cells = <0>;
276 clock-names = "i2c";
277 clocks = <&cru PCLK_I2C1>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c1_xfer>;
280 status = "disabled";
281 };
282
283 i2c3: i2c@ff150000 {
284 compatible = "rockchip,rk3288-i2c";
285 reg = <0xff150000 0x1000>;
286 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 clock-names = "i2c";
290 clocks = <&cru PCLK_I2C3>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c3_xfer>;
293 status = "disabled";
294 };
295
296 i2c4: i2c@ff160000 {
297 compatible = "rockchip,rk3288-i2c";
298 reg = <0xff160000 0x1000>;
299 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 clock-names = "i2c";
303 clocks = <&cru PCLK_I2C4>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c4_xfer>;
306 status = "disabled";
307 };
308
309 i2c5: i2c@ff170000 {
310 compatible = "rockchip,rk3288-i2c";
311 reg = <0xff170000 0x1000>;
312 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 clock-names = "i2c";
316 clocks = <&cru PCLK_I2C5>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&i2c5_xfer>;
319 status = "disabled";
320 };
321 uart0: serial@ff180000 {
322 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
323 reg = <0xff180000 0x100>;
324 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
325 reg-shift = <2>;
326 reg-io-width = <4>;
327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
328 clock-names = "baudclk", "apb_pclk";
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart0_xfer>;
331 status = "disabled";
332 };
333
334 uart1: serial@ff190000 {
335 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
336 reg = <0xff190000 0x100>;
337 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
338 reg-shift = <2>;
339 reg-io-width = <4>;
340 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
341 clock-names = "baudclk", "apb_pclk";
342 pinctrl-names = "default";
343 pinctrl-0 = <&uart1_xfer>;
344 status = "disabled";
345 };
346
347 uart2: serial@ff690000 {
348 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
349 reg = <0xff690000 0x100>;
350 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
351 reg-shift = <2>;
352 reg-io-width = <4>;
353 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
354 clock-names = "baudclk", "apb_pclk";
355 pinctrl-names = "default";
356 pinctrl-0 = <&uart2_xfer>;
357 status = "disabled";
358 };
359 uart3: serial@ff1b0000 {
360 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
361 reg = <0xff1b0000 0x100>;
362 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
363 reg-shift = <2>;
364 reg-io-width = <4>;
365 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
366 clock-names = "baudclk", "apb_pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&uart3_xfer>;
369 status = "disabled";
370 };
371
372 uart4: serial@ff1c0000 {
373 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
374 reg = <0xff1c0000 0x100>;
375 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
376 reg-shift = <2>;
377 reg-io-width = <4>;
378 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
379 clock-names = "baudclk", "apb_pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&uart4_xfer>;
382 status = "disabled";
383 };
384 thermal: thermal-zones {
385 #include "rk3288-thermal.dtsi"
386 };
387
388 tsadc: tsadc@ff280000 {
389 compatible = "rockchip,rk3288-tsadc";
390 reg = <0xff280000 0x100>;
391 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
393 clock-names = "tsadc", "apb_pclk";
394 resets = <&cru SRST_TSADC>;
395 reset-names = "tsadc-apb";
396 pinctrl-names = "otp_out";
397 pinctrl-0 = <&otp_out>;
398 #thermal-sensor-cells = <1>;
399 hw-shut-temp = <125000>;
400 status = "disabled";
401 };
402
403 gmac: ethernet@ff290000 {
404 compatible = "rockchip,rk3288-gmac";
405 reg = <0xff290000 0x10000>;
406 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "macirq";
408 rockchip,grf = <&grf>;
409 clocks = <&cru SCLK_MAC>,
410 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
411 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
412 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
413 clock-names = "stmmaceth",
414 "mac_clk_rx", "mac_clk_tx",
415 "clk_mac_ref", "clk_mac_refout",
416 "aclk_mac", "pclk_mac";
417 };
418
419 usb_host0_ehci: usb@ff500000 {
420 compatible = "generic-ehci";
421 reg = <0xff500000 0x100>;
422 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&cru HCLK_USBHOST0>;
424 clock-names = "usbhost";
425 phys = <&usbphy1>;
426 phy-names = "usb";
427 status = "disabled";
428 };
429
430 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
431
432 usb_host1: usb@ff540000 {
433 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
434 "snps,dwc2";
435 reg = <0xff540000 0x40000>;
436 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&cru HCLK_USBHOST1>;
438 clock-names = "otg";
439 phys = <&usbphy2>;
440 phy-names = "usb2-phy";
441 status = "disabled";
442 };
443
444 usb_otg: usb@ff580000 {
445 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
446 "snps,dwc2";
447 reg = <0xff580000 0x40000>;
448 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&cru HCLK_OTG0>;
450 clock-names = "otg";
451 phys = <&usbphy0>;
452 phy-names = "usb2-phy";
453 status = "disabled";
454 };
455
456 usb_hsic: usb@ff5c0000 {
457 compatible = "generic-ehci";
458 reg = <0xff5c0000 0x100>;
459 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cru HCLK_HSIC>;
461 clock-names = "usbhost";
462 status = "disabled";
463 };
464
465 dmc: dmc@ff610000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame^]466 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]467 compatible = "rockchip,rk3288-dmc", "syscon";
468 rockchip,cru = <&cru>;
469 rockchip,grf = <&grf>;
470 rockchip,pmu = <&pmu>;
471 rockchip,sgrf = <&sgrf>;
472 rockchip,noc = <&noc>;
473 reg = <0xff610000 0x3fc
474 0xff620000 0x294
475 0xff630000 0x3fc
476 0xff640000 0x294>;
477 rockchip,sram = <&ddr_sram>;
478 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
479 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
480 <&cru ARMCLK>;
481 clock-names = "pclk_ddrupctl0", "pclk_publ0",
482 "pclk_ddrupctl1", "pclk_publ1",
483 "arm_clk";
484 };
485
486 i2c0: i2c@ff650000 {
487 compatible = "rockchip,rk3288-i2c";
488 reg = <0xff650000 0x1000>;
489 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 clock-names = "i2c";
493 clocks = <&cru PCLK_I2C0>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c0_xfer>;
496 status = "disabled";
497 };
498
499 i2c2: i2c@ff660000 {
500 compatible = "rockchip,rk3288-i2c";
501 reg = <0xff660000 0x1000>;
502 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 clock-names = "i2c";
506 clocks = <&cru PCLK_I2C2>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c2_xfer>;
509 status = "disabled";
510 };
511
512 pwm0: pwm@ff680000 {
513 compatible = "rockchip,rk3288-pwm";
514 reg = <0xff680000 0x10>;
515 #pwm-cells = <3>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&pwm0_pin>;
518 clocks = <&cru PCLK_PWM>;
519 clock-names = "pwm";
520 rockchip,grf = <&grf>;
521 status = "disabled";
522 };
523
524 pwm1: pwm@ff680010 {
525 compatible = "rockchip,rk3288-pwm";
526 reg = <0xff680010 0x10>;
527 #pwm-cells = <3>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&pwm1_pin>;
530 clocks = <&cru PCLK_PWM>;
531 clock-names = "pwm";
532 rockchip,grf = <&grf>;
533 status = "disabled";
534 };
535
536 pwm2: pwm@ff680020 {
537 compatible = "rockchip,rk3288-pwm";
538 reg = <0xff680020 0x10>;
539 #pwm-cells = <3>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pwm2_pin>;
542 clocks = <&cru PCLK_PWM>;
543 clock-names = "pwm";
544 rockchip,grf = <&grf>;
545 status = "disabled";
546 };
547
548 pwm3: pwm@ff680030 {
549 compatible = "rockchip,rk3288-pwm";
550 reg = <0xff680030 0x10>;
551 #pwm-cells = <2>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pwm3_pin>;
554 clocks = <&cru PCLK_PWM>;
555 clock-names = "pwm";
556 rockchip,grf = <&grf>;
557 status = "disabled";
558 };
559
560 bus_intmem@ff700000 {
561 compatible = "mmio-sram";
562 reg = <0xff700000 0x18000>;
563 #address-cells = <1>;
564 #size-cells = <1>;
565 ranges = <0 0xff700000 0x18000>;
566 smp-sram@0 {
567 compatible = "rockchip,rk3066-smp-sram";
568 reg = <0x00 0x10>;
569 };
570 ddr_sram: ddr-sram@1000 {
571 compatible = "rockchip,rk3288-ddr-sram";
572 reg = <0x1000 0x4000>;
573 };
574 };
575
576 sram@ff720000 {
577 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
578 reg = <0xff720000 0x1000>;
579 };
580
581 pmu: power-management@ff730000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame^]582 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]583 compatible = "rockchip,rk3288-pmu", "syscon";
584 reg = <0xff730000 0x100>;
585 };
586
587 sgrf: syscon@ff740000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame^]588 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]589 compatible = "rockchip,rk3288-sgrf", "syscon";
590 reg = <0xff740000 0x1000>;
591 };
592
593 cru: clock-controller@ff760000 {
594 compatible = "rockchip,rk3288-cru";
595 reg = <0xff760000 0x1000>;
596 rockchip,grf = <&grf>;
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame^]597 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]598 #clock-cells = <1>;
599 #reset-cells = <1>;
600 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
601 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
602 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
603 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
604 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
605 <&cru PCLK_PERI>;
606 assigned-clock-rates = <0>, <0>,
607 <594000000>, <400000000>,
608 <500000000>, <300000000>,
609 <150000000>, <75000000>,
610 <300000000>, <150000000>,
611 <75000000>;
612 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
613 };
614
615 grf: syscon@ff770000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame^]616 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]617 compatible = "rockchip,rk3288-grf", "syscon";
618 reg = <0xff770000 0x1000>;
619 };
620
621 wdt: watchdog@ff800000 {
622 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
623 reg = <0xff800000 0x100>;
624 clocks = <&cru PCLK_WDT>;
625 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
626 status = "disabled";
627 };
628
629 i2s: i2s@ff890000 {
630 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
631 reg = <0xff890000 0x10000>;
632 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
636 dma-names = "tx", "rx";
637 clock-names = "i2s_hclk", "i2s_clk";
638 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&i2s0_bus>;
641 status = "disabled";
642 };
643
644 vopb: vop@ff930000 {
645 compatible = "rockchip,rk3288-vop";
646 reg = <0xff930000 0x19c>;
647 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
649 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
650 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
651 reset-names = "axi", "ahb", "dclk";
652 iommus = <&vopb_mmu>;
653 power-domains = <&power RK3288_PD_VIO>;
654 status = "disabled";
655 vopb_out: port {
656 #address-cells = <1>;
657 #size-cells = <0>;
658 vopb_out_edp: endpoint@0 {
659 reg = <0>;
660 remote-endpoint = <&edp_in_vopb>;
661 };
662 vopb_out_hdmi: endpoint@1 {
663 reg = <1>;
664 remote-endpoint = <&hdmi_in_vopb>;
665 };
666 };
667 };
668
669 vopb_mmu: iommu@ff930300 {
670 compatible = "rockchip,iommu";
671 reg = <0xff930300 0x100>;
672 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
673 interrupt-names = "vopb_mmu";
674 power-domains = <&power RK3288_PD_VIO>;
675 #iommu-cells = <0>;
676 status = "disabled";
677 };
678
679 vopl: vop@ff940000 {
680 compatible = "rockchip,rk3288-vop";
681 reg = <0xff940000 0x19c>;
682 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
684 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
685 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
686 reset-names = "axi", "ahb", "dclk";
687 iommus = <&vopl_mmu>;
688 power-domains = <&power RK3288_PD_VIO>;
689 status = "disabled";
690 vopl_out: port {
691 #address-cells = <1>;
692 #size-cells = <0>;
693 vopl_out_edp: endpoint@0 {
694 reg = <0>;
695 remote-endpoint = <&edp_in_vopl>;
696 };
697 vopl_out_hdmi: endpoint@1 {
698 reg = <1>;
699 remote-endpoint = <&hdmi_in_vopl>;
700 };
701
702 };
703 };
704
705 vopl_mmu: iommu@ff940300 {
706 compatible = "rockchip,iommu";
707 reg = <0xff940300 0x100>;
708 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "vopl_mmu";
710 power-domains = <&power RK3288_PD_VIO>;
711 #iommu-cells = <0>;
712 status = "disabled";
713 };
714
715 edp: edp@ff970000 {
716 compatible = "rockchip,rk3288-edp";
717 reg = <0xff970000 0x4000>;
718 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
720 rockchip,grf = <&grf>;
721 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
722 resets = <&cru 111>;
723 reset-names = "edp";
724 power-domains = <&power RK3288_PD_VIO>;
725 status = "disabled";
726 ports {
727 edp_in: port {
728 #address-cells = <1>;
729 #size-cells = <0>;
730 edp_in_vopb: endpoint@0 {
731 reg = <0>;
732 remote-endpoint = <&vopb_out_edp>;
733 };
734 edp_in_vopl: endpoint@1 {
735 reg = <1>;
736 remote-endpoint = <&vopl_out_edp>;
737 };
738 };
739 };
740 };
741
742 hdmi: hdmi@ff980000 {
743 compatible = "rockchip,rk3288-dw-hdmi";
744 reg = <0xff980000 0x20000>;
745 reg-io-width = <4>;
746 ddc-i2c-bus = <&i2c5>;
747 rockchip,grf = <&grf>;
748 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
750 clock-names = "iahb", "isfr";
751 status = "disabled";
752 ports {
753 hdmi_in: port {
754 #address-cells = <1>;
755 #size-cells = <0>;
756 hdmi_in_vopb: endpoint@0 {
757 reg = <0>;
758 remote-endpoint = <&vopb_out_hdmi>;
759 };
760 hdmi_in_vopl: endpoint@1 {
761 reg = <1>;
762 remote-endpoint = <&vopl_out_hdmi>;
763 };
764 };
765 };
766 };
767
768 hdmi_audio: hdmi_audio {
769 compatible = "rockchip,rk3288-hdmi-audio";
770 i2s-controller = <&i2s>;
771 status = "disable";
772 };
773
774 vpu: video-codec@ff9a0000 {
775 compatible = "rockchip,rk3288-vpu";
776 reg = <0xff9a0000 0x800>;
777 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
779 interrupt-names = "vepu", "vdpu";
780 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
781 clock-names = "aclk_vcodec", "hclk_vcodec";
782 power-domains = <&power RK3288_PD_VIDEO>;
783 iommus = <&vpu_mmu>;
784 };
785
786 vpu_mmu: iommu@ff9a0800 {
787 compatible = "rockchip,iommu";
788 reg = <0xff9a0800 0x100>;
789 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
790 interrupt-names = "vpu_mmu";
791 power-domains = <&power RK3288_PD_VIDEO>;
792 #iommu-cells = <0>;
793 };
794
795 gpu: gpu@ffa30000 {
796 compatible = "arm,malit764",
797 "arm,malit76x",
798 "arm,malit7xx",
799 "arm,mali-midgard";
800 reg = <0xffa30000 0x10000>;
801 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
804 interrupt-names = "JOB", "MMU", "GPU";
805 clocks = <&cru ACLK_GPU>;
806 clock-names = "aclk_gpu";
807 operating-points = <
808 /* KHz uV */
809 100000 950000
810 200000 950000
811 300000 1000000
812 400000 1100000
813 /* 500000 1200000 - See crosbug.com/p/33857 */
814 600000 1250000
815 >;
816 power-domains = <&power RK3288_PD_GPU>;
817 status = "disabled";
818 };
819
820 noc: syscon@ffac0000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame^]821 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]822 compatible = "rockchip,rk3288-noc", "syscon";
823 reg = <0xffac0000 0x2000>;
824 };
825
826 efuse: efuse@ffb40000 {
827 compatible = "rockchip,rk3288-efuse";
828 reg = <0xffb40000 0x10000>;
829 status = "disabled";
830 };
831
832 gic: interrupt-controller@ffc01000 {
833 compatible = "arm,gic-400";
834 interrupt-controller;
835 #interrupt-cells = <3>;
836 #address-cells = <0>;
837
838 reg = <0xffc01000 0x1000>,
839 <0xffc02000 0x1000>,
840 <0xffc04000 0x2000>,
841 <0xffc06000 0x2000>;
842 interrupts = <GIC_PPI 9 0xf04>;
843 };
844
845 cpuidle: cpuidle {
846 compatible = "rockchip,rk3288-cpuidle";
847 };
848
849 usbphy: phy {
850 compatible = "rockchip,rk3288-usb-phy";
851 rockchip,grf = <&grf>;
852 #address-cells = <1>;
853 #size-cells = <0>;
854 status = "disabled";
855
856 usbphy0: usb-phy0 {
857 #phy-cells = <0>;
858 reg = <0x320>;
859 clocks = <&cru SCLK_OTGPHY0>;
860 clock-names = "phyclk";
861 };
862
863 usbphy1: usb-phy1 {
864 #phy-cells = <0>;
865 reg = <0x334>;
866 clocks = <&cru SCLK_OTGPHY1>;
867 clock-names = "phyclk";
868 };
869
870 usbphy2: usb-phy2 {
871 #phy-cells = <0>;
872 reg = <0x348>;
873 clocks = <&cru SCLK_OTGPHY2>;
874 clock-names = "phyclk";
875 };
876 };
877
878 pinctrl: pinctrl {
879 compatible = "rockchip,rk3288-pinctrl";
880 rockchip,grf = <&grf>;
881 rockchip,pmu = <&pmu>;
882 #address-cells = <1>;
883 #size-cells = <1>;
884 ranges;
885
886 gpio0: gpio0@ff750000 {
887 compatible = "rockchip,gpio-bank";
888 reg = <0xff750000 0x100>;
889 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&cru PCLK_GPIO0>;
891
892 gpio-controller;
893 #gpio-cells = <2>;
894
895 interrupt-controller;
896 #interrupt-cells = <2>;
897 };
898
899 gpio1: gpio1@ff780000 {
900 compatible = "rockchip,gpio-bank";
901 reg = <0xff780000 0x100>;
902 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&cru PCLK_GPIO1>;
904
905 gpio-controller;
906 #gpio-cells = <2>;
907
908 interrupt-controller;
909 #interrupt-cells = <2>;
910 };
911
912 gpio2: gpio2@ff790000 {
913 compatible = "rockchip,gpio-bank";
914 reg = <0xff790000 0x100>;
915 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&cru PCLK_GPIO2>;
917
918 gpio-controller;
919 #gpio-cells = <2>;
920
921 interrupt-controller;
922 #interrupt-cells = <2>;
923 };
924
925 gpio3: gpio3@ff7a0000 {
926 compatible = "rockchip,gpio-bank";
927 reg = <0xff7a0000 0x100>;
928 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&cru PCLK_GPIO3>;
930
931 gpio-controller;
932 #gpio-cells = <2>;
933
934 interrupt-controller;
935 #interrupt-cells = <2>;
936 };
937
938 gpio4: gpio4@ff7b0000 {
939 compatible = "rockchip,gpio-bank";
940 reg = <0xff7b0000 0x100>;
941 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&cru PCLK_GPIO4>;
943
944 gpio-controller;
945 #gpio-cells = <2>;
946
947 interrupt-controller;
948 #interrupt-cells = <2>;
949 };
950
951 gpio5: gpio5@ff7c0000 {
952 compatible = "rockchip,gpio-bank";
953 reg = <0xff7c0000 0x100>;
954 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&cru PCLK_GPIO5>;
956
957 gpio-controller;
958 #gpio-cells = <2>;
959
960 interrupt-controller;
961 #interrupt-cells = <2>;
962 };
963
964 gpio6: gpio6@ff7d0000 {
965 compatible = "rockchip,gpio-bank";
966 reg = <0xff7d0000 0x100>;
967 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&cru PCLK_GPIO6>;
969
970 gpio-controller;
971 #gpio-cells = <2>;
972
973 interrupt-controller;
974 #interrupt-cells = <2>;
975 };
976
977 gpio7: gpio7@ff7e0000 {
978 compatible = "rockchip,gpio-bank";
979 reg = <0xff7e0000 0x100>;
980 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cru PCLK_GPIO7>;
982
983 gpio-controller;
984 #gpio-cells = <2>;
985
986 interrupt-controller;
987 #interrupt-cells = <2>;
988 };
989
990 gpio8: gpio8@ff7f0000 {
991 compatible = "rockchip,gpio-bank";
992 reg = <0xff7f0000 0x100>;
993 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru PCLK_GPIO8>;
995
996 gpio-controller;
997 #gpio-cells = <2>;
998
999 interrupt-controller;
1000 #interrupt-cells = <2>;
1001 };
1002
1003 pcfg_pull_up: pcfg-pull-up {
1004 bias-pull-up;
1005 };
1006
1007 pcfg_pull_down: pcfg-pull-down {
1008 bias-pull-down;
1009 };
1010
1011 pcfg_pull_none: pcfg-pull-none {
1012 bias-disable;
1013 };
1014
1015 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1016 bias-disable;
1017 drive-strength = <12>;
1018 };
1019
1020 sleep {
1021 global_pwroff: global-pwroff {
1022 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1023 };
1024
1025 ddrio_pwroff: ddrio-pwroff {
1026 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1027 };
1028
1029 ddr0_retention: ddr0-retention {
1030 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1031 };
1032
1033 ddr1_retention: ddr1-retention {
1034 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1035 };
1036 };
1037
1038 i2c0 {
1039 i2c0_xfer: i2c0-xfer {
1040 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1041 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1042 };
1043 };
1044
1045 i2c1 {
1046 i2c1_xfer: i2c1-xfer {
1047 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1048 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1049 };
1050 };
1051
1052 i2c2 {
1053 i2c2_xfer: i2c2-xfer {
1054 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1055 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1056 };
1057 };
1058
1059 i2c3 {
1060 i2c3_xfer: i2c3-xfer {
1061 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1062 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1063 };
1064 };
1065
1066 i2c4 {
1067 i2c4_xfer: i2c4-xfer {
1068 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1069 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1070 };
1071 };
1072
1073 i2c5 {
1074 i2c5_xfer: i2c5-xfer {
1075 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1076 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1077 };
1078 };
1079
1080 i2s0 {
1081 i2s0_bus: i2s0-bus {
1082 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1083 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1084 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1085 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1086 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1087 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1088 };
1089 };
1090
1091 sdmmc {
1092 sdmmc_clk: sdmmc-clk {
1093 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1094 };
1095
1096 sdmmc_cmd: sdmmc-cmd {
1097 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1098 };
1099
1100 sdmmc_cd: sdmcc-cd {
1101 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1102 };
1103
1104 sdmmc_bus1: sdmmc-bus1 {
1105 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1106 };
1107
1108 sdmmc_bus4: sdmmc-bus4 {
1109 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1110 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1111 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1112 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1113 };
1114 };
1115
1116 sdio0 {
1117 sdio0_bus1: sdio0-bus1 {
1118 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1119 };
1120
1121 sdio0_bus4: sdio0-bus4 {
1122 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1123 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1124 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1125 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1126 };
1127
1128 sdio0_cmd: sdio0-cmd {
1129 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1130 };
1131
1132 sdio0_clk: sdio0-clk {
1133 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1134 };
1135
1136 sdio0_cd: sdio0-cd {
1137 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1138 };
1139
1140 sdio0_wp: sdio0-wp {
1141 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1142 };
1143
1144 sdio0_pwr: sdio0-pwr {
1145 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1146 };
1147
1148 sdio0_bkpwr: sdio0-bkpwr {
1149 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1150 };
1151
1152 sdio0_int: sdio0-int {
1153 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1154 };
1155 };
1156
1157 sdio1 {
1158 sdio1_bus1: sdio1-bus1 {
1159 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1160 };
1161
1162 sdio1_bus4: sdio1-bus4 {
1163 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1164 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1165 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1166 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1167 };
1168
1169 sdio1_cd: sdio1-cd {
1170 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1171 };
1172
1173 sdio1_wp: sdio1-wp {
1174 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1175 };
1176
1177 sdio1_bkpwr: sdio1-bkpwr {
1178 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1179 };
1180
1181 sdio1_int: sdio1-int {
1182 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1183 };
1184
1185 sdio1_cmd: sdio1-cmd {
1186 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1187 };
1188
1189 sdio1_clk: sdio1-clk {
1190 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1191 };
1192
1193 sdio1_pwr: sdio1-pwr {
1194 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1195 };
1196 };
1197
1198 emmc {
1199 emmc_clk: emmc-clk {
1200 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1201 };
1202
1203 emmc_cmd: emmc-cmd {
1204 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1205 };
1206
1207 emmc_pwr: emmc-pwr {
1208 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1209 };
1210
1211 emmc_bus1: emmc-bus1 {
1212 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1213 };
1214
1215 emmc_bus4: emmc-bus4 {
1216 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1217 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1218 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1219 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1220 };
1221
1222 emmc_bus8: emmc-bus8 {
1223 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1224 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1225 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1226 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1227 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1228 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1229 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1230 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1231 };
1232 };
1233
1234 spi0 {
1235 spi0_clk: spi0-clk {
1236 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1237 };
1238 spi0_cs0: spi0-cs0 {
1239 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1240 };
1241 spi0_tx: spi0-tx {
1242 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1243 };
1244 spi0_rx: spi0-rx {
1245 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1246 };
1247 spi0_cs1: spi0-cs1 {
1248 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1249 };
1250 };
1251 spi1 {
1252 spi1_clk: spi1-clk {
1253 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1254 };
1255 spi1_cs0: spi1-cs0 {
1256 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1257 };
1258 spi1_rx: spi1-rx {
1259 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1260 };
1261 spi1_tx: spi1-tx {
1262 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1263 };
1264 };
1265
1266 spi2 {
1267 spi2_cs1: spi2-cs1 {
1268 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1269 };
1270 spi2_clk: spi2-clk {
1271 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1272 };
1273 spi2_cs0: spi2-cs0 {
1274 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1275 };
1276 spi2_rx: spi2-rx {
1277 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1278 };
1279 spi2_tx: spi2-tx {
1280 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1281 };
1282 };
1283
1284 uart0 {
1285 uart0_xfer: uart0-xfer {
1286 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1287 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1288 };
1289
1290 uart0_cts: uart0-cts {
1291 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1292 };
1293
1294 uart0_rts: uart0-rts {
1295 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1296 };
1297 };
1298
1299 uart1 {
1300 uart1_xfer: uart1-xfer {
1301 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1302 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1303 };
1304
1305 uart1_cts: uart1-cts {
1306 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1307 };
1308
1309 uart1_rts: uart1-rts {
1310 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1311 };
1312 };
1313
1314 uart2 {
1315 uart2_xfer: uart2-xfer {
1316 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1317 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1318 };
1319 /* no rts / cts for uart2 */
1320 };
1321
1322 uart3 {
1323 uart3_xfer: uart3-xfer {
1324 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1325 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1326 };
1327
1328 uart3_cts: uart3-cts {
1329 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1330 };
1331
1332 uart3_rts: uart3-rts {
1333 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1334 };
1335 };
1336
1337 uart4 {
1338 uart4_xfer: uart4-xfer {
1339 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1340 <5 13 3 &pcfg_pull_none>;
1341 };
1342
1343 uart4_cts: uart4-cts {
1344 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1345 };
1346
1347 uart4_rts: uart4-rts {
1348 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1349 };
1350 };
1351
1352 tsadc {
1353 otp_out: otp-out {
1354 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1355 };
1356 };
1357
1358 pwm0 {
1359 pwm0_pin: pwm0-pin {
1360 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1361 };
1362 };
1363
1364 pwm1 {
1365 pwm1_pin: pwm1-pin {
1366 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1367 };
1368 };
1369
1370 pwm2 {
1371 pwm2_pin: pwm2-pin {
1372 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1373 };
1374 };
1375
1376 pwm3 {
1377 pwm3_pin: pwm3-pin {
1378 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1379 };
1380 };
1381
1382 gmac {
1383 rgmii_pins: rgmii-pins {
1384 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1385 <3 31 3 &pcfg_pull_none>,
1386 <3 26 3 &pcfg_pull_none>,
1387 <3 27 3 &pcfg_pull_none>,
1388 <3 28 3 &pcfg_pull_none_12ma>,
1389 <3 29 3 &pcfg_pull_none_12ma>,
1390 <3 24 3 &pcfg_pull_none_12ma>,
1391 <3 25 3 &pcfg_pull_none_12ma>,
1392 <4 0 3 &pcfg_pull_none>,
1393 <4 5 3 &pcfg_pull_none>,
1394 <4 6 3 &pcfg_pull_none>,
1395 <4 9 3 &pcfg_pull_none_12ma>,
1396 <4 4 3 &pcfg_pull_none_12ma>,
1397 <4 1 3 &pcfg_pull_none>,
1398 <4 3 3 &pcfg_pull_none>;
1399 };
1400
1401 rmii_pins: rmii-pins {
1402 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1403 <3 31 3 &pcfg_pull_none>,
1404 <3 28 3 &pcfg_pull_none>,
1405 <3 29 3 &pcfg_pull_none>,
1406 <4 0 3 &pcfg_pull_none>,
1407 <4 5 3 &pcfg_pull_none>,
1408 <4 4 3 &pcfg_pull_none>,
1409 <4 1 3 &pcfg_pull_none>,
1410 <4 2 3 &pcfg_pull_none>,
1411 <4 3 3 &pcfg_pull_none>;
1412 };
1413 };
1414 };
1415
1416 power: power-controller {
1417 compatible = "rockchip,rk3288-power-controller";
1418 #power-domain-cells = <1>;
1419 rockchip,pmu = <&pmu>;
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1422
1423 pd_gpu {
1424 reg = <RK3288_PD_GPU>;
1425 clocks = <&cru ACLK_GPU>;
1426 };
1427
1428 pd_hevc {
1429 reg = <RK3288_PD_HEVC>;
1430 clocks = <&cru ACLK_HEVC>,
1431 <&cru SCLK_HEVC_CABAC>,
1432 <&cru SCLK_HEVC_CORE>,
1433 <&cru HCLK_HEVC>;
1434 };
1435
1436 pd_vio {
1437 reg = <RK3288_PD_VIO>;
1438 clocks = <&cru ACLK_IEP>,
1439 <&cru ACLK_ISP>,
1440 <&cru ACLK_RGA>,
1441 <&cru ACLK_VIP>,
1442 <&cru ACLK_VOP0>,
1443 <&cru ACLK_VOP1>,
1444 <&cru DCLK_VOP0>,
1445 <&cru DCLK_VOP1>,
1446 <&cru HCLK_IEP>,
1447 <&cru HCLK_ISP>,
1448 <&cru HCLK_RGA>,
1449 <&cru HCLK_VIP>,
1450 <&cru HCLK_VOP0>,
1451 <&cru HCLK_VOP1>,
1452 <&cru PCLK_EDP_CTRL>,
1453 <&cru PCLK_HDMI_CTRL>,
1454 <&cru PCLK_LVDS_PHY>,
1455 <&cru PCLK_MIPI_CSI>,
1456 <&cru PCLK_MIPI_DSI0>,
1457 <&cru PCLK_MIPI_DSI1>,
1458 <&cru SCLK_EDP_24M>,
1459 <&cru SCLK_EDP>,
1460 <&cru SCLK_HDMI_CEC>,
1461 <&cru SCLK_HDMI_HDCP>,
1462 <&cru SCLK_ISP_JPE>,
1463 <&cru SCLK_ISP>,
1464 <&cru SCLK_RGA>;
1465 };
1466
1467 pd_video {
1468 reg = <RK3288_PD_VIDEO>;
1469 clocks = <&cru ACLK_VCODEC>,
1470 <&cru HCLK_VCODEC>;
1471 };
1472 };
1473};