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Vikas Manocha4515ffe2017-04-10 15:02:56 -07001#ifndef DT_BINDINGS_STM32_SDRAM_H
2#define DT_BINDINGS_STM32_SDRAM_H
3
4#define NO_COL_8 0x0
5#define NO_COL_9 0x1
6#define NO_COL_10 0x2
7#define NO_COL_11 0x3
8
9#define NO_ROW_11 0x0
10#define NO_ROW_12 0x1
11#define NO_ROW_13 0x2
12
13#define MWIDTH_8 0x0
14#define MWIDTH_16 0x1
15#define MWIDTH_32 0x2
16#define BANKS_2 0x0
17#define BANKS_4 0x1
18#define CAS_1 0x1
19#define CAS_2 0x2
20#define CAS_3 0x3
Patrice Chotard0dca06e2017-09-13 18:00:11 +020021#define SDCLK_DIS 0x0
Vikas Manocha1c6459d2017-04-10 15:03:03 -070022#define SDCLK_2 0x2
Patrice Chotard0dca06e2017-09-13 18:00:11 +020023#define SDCLK_3 0x3
Vikas Manocha4515ffe2017-04-10 15:02:56 -070024#define RD_BURST_EN 0x1
25#define RD_BURST_DIS 0x0
26#define RD_PIPE_DL_0 0x0
27#define RD_PIPE_DL_1 0x1
28#define RD_PIPE_DL_2 0x2
29
Vikas Manocha1c6459d2017-04-10 15:03:03 -070030/* Timing = value +1 cycles */
Patrice Chotard0dca06e2017-09-13 18:00:11 +020031#define TMRD_1 (1 - 1)
Vikas Manocha1c6459d2017-04-10 15:03:03 -070032#define TMRD_2 (2 - 1)
Patrice Chotard48b7a042017-12-12 09:49:33 +010033#define TMRD_3 (3 - 1)
Patrice Chotard0dca06e2017-09-13 18:00:11 +020034#define TXSR_1 (1 - 1)
Vikas Manocha1c6459d2017-04-10 15:03:03 -070035#define TXSR_6 (6 - 1)
Patrice Chotard48b7a042017-12-12 09:49:33 +010036#define TXSR_7 (7 - 1)
Patrice Chotard0dca06e2017-09-13 18:00:11 +020037#define TRAS_1 (1 - 1)
Vikas Manocha1c6459d2017-04-10 15:03:03 -070038#define TRAS_4 (4 - 1)
39#define TRC_6 (6 - 1)
Patrice Chotard0dca06e2017-09-13 18:00:11 +020040#define TWR_1 (1 - 1)
Vikas Manocha1c6459d2017-04-10 15:03:03 -070041#define TWR_2 (2 - 1)
42#define TRP_2 (2 - 1)
Patrice Chotard0dca06e2017-09-13 18:00:11 +020043#define TRCD_1 (1 - 1)
Vikas Manocha1c6459d2017-04-10 15:03:03 -070044#define TRCD_2 (2 - 1)
Vikas Manocha4515ffe2017-04-10 15:02:56 -070045
46#endif