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git01.mediatek.com / filogic / uboot / 6a5dccc02202c5bf334825ef3104f9d85c9cb678 / . / include / configs / dra7xx_evm.h
blob: 8217712e3904885534fe2cbc1ed8910439d5ac94 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]2/*
3 * (C) Copyright 2013
4 * Texas Instruments Incorporated.
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Configuration settings for the TI DRA7XX board.
Enric Balletbò i Serra2785bb72013-12-06 21:30:19 +0100[diff] [blame]8 * See ti_omap5_common.h for omap5 common settings.
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]9 */
10
11#ifndef __CONFIG_DRA7XX_EVM_H
12#define __CONFIG_DRA7XX_EVM_H
13
Sekhar Noribb018cf2016-11-25 14:25:54 +0530[diff] [blame]14#include <environment/ti/dfu.h>
15
Lokesh Vutla1fd80222015-06-04 16:42:38 +0530[diff] [blame]16#define CONFIG_IODELAY_RECALIBRATION
Lokesh Vutla1fd80222015-06-04 16:42:38 +0530[diff] [blame]17
Lokesh Vutla18608172016-03-08 09:18:07 +0530[diff] [blame]18#define CONFIG_VERY_BIG_RAM
Lokesh Vutla18608172016-03-08 09:18:07 +0530[diff] [blame]19#define CONFIG_MAX_MEM_MAPPED 0x80000000
20
Tom Rini560ef452014-04-03 07:52:56 -0400[diff] [blame]21#ifndef CONFIG_QSPI_BOOT
Lokesh Vutlaf8c725e2013-08-23 17:27:04 +0530[diff] [blame]22/* MMC ENV related defines */
Tom Rini560ef452014-04-03 07:52:56 -0400[diff] [blame]23#endif
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]24
Minal Shah01ae8ca2013-10-04 14:52:02 -0400[diff] [blame]25#if (CONFIG_CONS_INDEX == 1)
Sam Protsenko02c005f2019-07-12 20:38:12 +0300[diff] [blame]26#define CONSOLEDEV "ttyS0"
Minal Shah01ae8ca2013-10-04 14:52:02 -0400[diff] [blame]27#elif (CONFIG_CONS_INDEX == 3)
Sam Protsenko02c005f2019-07-12 20:38:12 +0300[diff] [blame]28#define CONSOLEDEV "ttyS2"
Minal Shah01ae8ca2013-10-04 14:52:02 -0400[diff] [blame]29#endif
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame]30#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
31#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
32#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]33
Tom Riniaed1ba12015-06-12 20:52:29 -0400[diff] [blame]34#ifndef CONFIG_SPL_BUILD
Kishon Vijay Abraham I24080762015-02-23 18:40:20 +0530[diff] [blame]35#define DFUARGS \
36 "dfu_bufsiz=0x10000\0" \
37 DFU_ALT_INFO_MMC \
38 DFU_ALT_INFO_EMMC \
Vignesh R1bf06342015-10-20 15:22:01 +0530[diff] [blame]39 DFU_ALT_INFO_RAM \
40 DFU_ALT_INFO_QSPI
Tom Riniaed1ba12015-06-12 20:52:29 -0400[diff] [blame]41#endif
Dileep Kattaf2731292015-03-25 04:04:50 +0530[diff] [blame]42
B, Ravie0552472016-07-28 17:39:18 +0530[diff] [blame]43#ifdef CONFIG_SPL_BUILD
Andrew F. Davis6d932e62019-01-17 13:43:02 -0600[diff] [blame]44#ifdef CONFIG_SPL_DFU
B, Ravie0552472016-07-28 17:39:18 +0530[diff] [blame]45#define DFUARGS \
46 "dfu_bufsiz=0x10000\0" \
47 DFU_ALT_INFO_RAM
48#endif
49#endif
50
Enric Balletbò i Serra2785bb72013-12-06 21:30:19 +0100[diff] [blame]51#include <configs/ti_omap5_common.h>
Dan Murphya6f9d152013-06-11 11:22:30 -0500[diff] [blame]52
Tom Rinifce0d592014-01-21 17:15:08 -0500[diff] [blame]53/* Enhance our eMMC support / experience. */
Lubomir Popov6d2f9852014-11-10 18:14:18 +0200[diff] [blame]54#define CONFIG_HSMMC2_8BIT
Tom Rinifce0d592014-01-21 17:15:08 -0500[diff] [blame]55
Tom Rini560ef452014-04-03 07:52:56 -0400[diff] [blame]56/*
57 * Default to using SPI for environment, etc.
B, Raviacd0cab2016-09-26 18:21:13 +0530[diff] [blame]58 * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
Tom Rini560ef452014-04-03 07:52:56 -0400[diff] [blame]59 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
60 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
61 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
62 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
63 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
64 * 0x9E0000 - 0x2000000 : USERLAND
65 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame^]66#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
67#define CFG_SYS_SPI_ARGS_OFFS 0x140000
68#define CFG_SYS_SPI_ARGS_SIZE 0x80000
Tom Rini560ef452014-04-03 07:52:56 -0400[diff] [blame]69
Matt Porterbb1a8472013-10-07 15:53:03 +0530[diff] [blame]70/* SPI SPL */
Matt Porterbb1a8472013-10-07 15:53:03 +0530[diff] [blame]71
pekon gupta64733cc2014-07-22 16:03:23 +0530[diff] [blame]72/* NAND support */
Miquel Raynald0935362019-10-03 19:50:03 +0200[diff] [blame]73#ifdef CONFIG_MTD_RAW_NAND
pekon gupta64733cc2014-07-22 16:03:23 +0530[diff] [blame]74/* NAND: device related configs */
pekon gupta64733cc2014-07-22 16:03:23 +0530[diff] [blame]75/* NAND: driver related configs */
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]76#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
pekon gupta64733cc2014-07-22 16:03:23 +0530[diff] [blame]77 10, 11, 12, 13, 14, 15, 16, 17, \
78 18, 19, 20, 21, 22, 23, 24, 25, \
79 26, 27, 28, 29, 30, 31, 32, 33, \
80 34, 35, 36, 37, 38, 39, 40, 41, \
81 42, 43, 44, 45, 46, 47, 48, 49, \
82 50, 51, 52, 53, 54, 55, 56, 57, }
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]83#define CFG_SYS_NAND_ECCSIZE 512
84#define CFG_SYS_NAND_ECCBYTES 14
Miquel Raynald0935362019-10-03 19:50:03 +0200[diff] [blame]85#endif /* !CONFIG_MTD_RAW_NAND */
pekon gupta64733cc2014-07-22 16:03:23 +0530[diff] [blame]86
pekon gupta01663492014-07-22 16:03:24 +0530[diff] [blame]87/* Parallel NOR Support */
88#if defined(CONFIG_NOR)
89/* NOR: device related configs */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame^]90#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
91#define CFG_SYS_FLASH_BASE (0x08000000)
pekon gupta01663492014-07-22 16:03:24 +0530[diff] [blame]92/* Reduce SPL size by removing unlikey targets */
pekon gupta01663492014-07-22 16:03:24 +0530[diff] [blame]93#endif /* NOR support */
94
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]95#endif /* __CONFIG_DRA7XX_EVM_H */