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git01.mediatek.com / filogic / uboot / 6a5dccc02202c5bf334825ef3104f9d85c9cb678 / . / arch / arm / include / asm / arch-lpc32xx / config.h
blob: 3ad78cb1e645264e7d9d47a6898a16216d680b89 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]2/*
3 * Common definitions for LPC32XX board configurations
4 *
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]6 */
7
8#ifndef _LPC32XX_CONFIG_H
9#define _LPC32XX_CONFIG_H
10
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]11
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]12/* Basic CPU architecture */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]13
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]14/* UART configuration */
Trevor Woerner0b881ac2021-06-10 22:37:02 -0400[diff] [blame]15#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
16 (CONFIG_CONS_INDEX == 7)
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]17#if !defined(CONFIG_LPC32XX_HSUART)
18#define CONFIG_LPC32XX_HSUART
19#endif
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]20#endif
21
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame]22#if !defined(CFG_SYS_NS16550_CLK)
23#define CFG_SYS_NS16550_CLK 13000000
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]24#endif
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]25
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame^]26#define CFG_SYS_BAUDRATE_TABLE \
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]27 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
28
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]29/* NAND */
30#if defined(CONFIG_NAND_LPC32XX_SLC)
31#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
32#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
33
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]34#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]35#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]36 48, 49, 50, 51, 52, 53, 54, 55, \
37 56, 57, 58, 59, 60, 61, 62, 63, }
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]38#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]39#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]40#else
41#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
42#endif
43
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]44#define CFG_SYS_NAND_ECCSIZE 0x100
45#define CFG_SYS_NAND_ECCBYTES 3
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]46#endif /* CONFIG_NAND_LPC32XX_SLC */
47
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]48/* NOR Flash */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]49
Vladimir Zapolskiy69ec0752015-08-12 20:32:08 +0300[diff] [blame]50/* USB OHCI */
51#if defined(CONFIG_USB_OHCI_LPC32XX)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame^]52#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE
Vladimir Zapolskiy69ec0752015-08-12 20:32:08 +0300[diff] [blame]53#endif
54
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]55#endif /* _LPC32XX_CONFIG_H */