| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011 |
| 4 | * Marvell Semiconductor <www.marvell.com> |
| 5 | * Written-by: Lei Wen <leiwen@marvell.com> |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * This file should be included in board config header file. |
| 10 | * |
| 11 | * It supports common definitions for Kirkwood platform |
| 12 | */ |
| 13 | |
| 14 | #ifndef _KW_CONFIG_H |
| 15 | #define _KW_CONFIG_H |
| 16 | |
| 17 | #if defined (CONFIG_KW88F6281) |
| 18 | #include <asm/arch/kw88f6281.h> |
| 19 | #elif defined (CONFIG_KW88F6192) |
| 20 | #include <asm/arch/kw88f6192.h> |
| 21 | #else |
| 22 | #error "SOC Name not defined" |
| 23 | #endif /* CONFIG_KW88F6281 */ |
| 24 | |
| Stefan Roese | c243784 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 25 | #include <asm/arch/soc.h> |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 26 | |
| Paul Kocialkowski | 2fae3e7 | 2015-04-10 23:09:51 +0200 | [diff] [blame] | 27 | #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 28 | #define MV_UART_CONSOLE_BASE KW_UART0_BASE |
| 29 | #define MV_SATA_BASE KW_SATA_BASE |
| 30 | #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET |
| 31 | #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET |
| 32 | |
| 33 | /* |
| 34 | * NAND configuration |
| 35 | */ |
| 36 | #ifdef CONFIG_CMD_NAND |
| 37 | #define CONFIG_NAND_KIRKWOOD |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 38 | #define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 39 | #define NAND_ALLOW_ERASE_ALL 1 |
| 40 | #endif |
| 41 | |
| 42 | /* |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 43 | * IDE Support on SATA ports |
| 44 | */ |
| Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 45 | #ifdef CONFIG_IDE |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 46 | #define __io |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 47 | /* Data, registers and alternate blocks are at the same offset */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 48 | /* Each 8-bit ATA register is aligned to a 4-bytes address */ |
| Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 49 | /* CONFIG_IDE requires some #defines for ATA registers */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 50 | /* ATA registers base is at SATA controller base */ |
| Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 51 | #endif /* CONFIG_IDE */ |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 52 | |
| Stefan Roese | 6417489 | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 53 | /* Use common timer */ |
| Michael Walle | 2e9151e | 2022-08-17 21:37:50 +0200 | [diff] [blame] | 54 | #ifndef CONFIG_TIMER |
| Stefan Roese | 6417489 | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 55 | #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) |
| 56 | #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK |
| Michael Walle | 2e9151e | 2022-08-17 21:37:50 +0200 | [diff] [blame] | 57 | #endif |
| Stefan Roese | 6417489 | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 58 | |
| Lei Wen | 2001476 | 2011-02-09 18:06:58 +0530 | [diff] [blame] | 59 | #endif /* _KW_CONFIG_H */ |