blob: dcf9eb8144b800ec5db5dec300070f30e7e9f9fb [file] [log] [blame]
Heiko Stuebnerfc367852019-07-16 22:18:21 +02001if ROCKCHIP_PX30
2
3config TARGET_EVB_PX30
4 bool "EVB_PX30"
Jagan Tekic6e50172020-10-28 19:03:43 +05305 help
6 This target config option used for below listed px30 boards.
7
8 EVB_PX30:
9 * EVB_PX30 is an evaluation board for Rockchip PX30.
Heiko Stuebnerfc367852019-07-16 22:18:21 +020010
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +020011config TARGET_ODROID_GO2
12 bool "ODROID_GO2"
13
Jagan Teki57a0a562020-10-28 19:03:45 +053014config TARGET_PX30_CORE
15 bool "Engicam PX30.Core"
16 help
17 PX30.Core EDIMM2.2:
18 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
19 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.
20 * PX30.Core needs to mount on top of EDIMM2.2 for creating complete
21 PX30.Core EDIMM2.2 Starter Kit.
22
Jagan Tekic7a3d132020-10-28 19:03:47 +053023 PX30.Core CTOUCH2:
24 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
25 * CTOUCH2.0 is a general purpose Carrier board with capacitive
26 touch interface support.
27 * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
28 PX30.Core C.TOUCH Carrier board.
29
Jagan Teki19e0c952021-11-15 23:08:21 +053030 PX30.Core CTOUCH2-OF10:
31 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
32 * CTOUCH2.0 is a general purpose Carrier board with capacitive
33 touch interface support.
34 * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
35 * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
36 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
37
Quentin Schulz00a6f602023-01-09 11:36:45 +010038config TARGET_RINGNECK_PX30
Michal Simek75a4e1e2024-04-16 08:55:18 +020039 bool "Theobroma Systems PX30-uQ7 (Ringneck)"
Quentin Schulz00a6f602023-01-09 11:36:45 +010040 help
Michal Simek75a4e1e2024-04-16 08:55:18 +020041 The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm,
Quentin Schulz00a6f602023-01-09 11:36:45 +010042 MXM-230 connector) system-on-module from Theobroma Systems[1],
43 featuring the Rockchip PX30.
44
45 It provides the following feature set:
46 * up to 4GB DDR4
47 * up to 128GB on-module eMMC (with 8-bit 1.8V interface)
48 * SD card (on a baseboard) via edge connector
49 * Fast Ethernet with on-module TI DP83825I PHY
50 * MIPI-DSI/LVDS
51 * MIPI-CSI
52 * USB
53 - 1x USB 2.0 dual-role
54 - 3x USB 2.0 host
55 * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing:
56 - low-power RTC functionality (ISL1208 emulation)
57 - fan controller (AMC6821 emulation)
58 - USB<->CAN bridge controller (STM32 only)
59 * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi
60 * on-module NXP SE05x Secure Element
61
Heiko Stuebnerfc367852019-07-16 22:18:21 +020062config ROCKCHIP_BOOT_MODE_REG
63 default 0xff010200
64
Johan Jonkerf6fc8952022-04-09 18:55:02 +020065config ROCKCHIP_STIMER_BASE
66 default 0xff220020
67
Heiko Stuebnerfc367852019-07-16 22:18:21 +020068config SYS_SOC
69 default "px30"
70
Quentin Schulz6a2442a2024-05-23 18:59:35 +020071config ROCKCHIP_COMMON_STACK_ADDR
72 default y
73
Heiko Stuebnerfc367852019-07-16 22:18:21 +020074config SYS_MALLOC_F_LEN
Quentin Schulz6a2442a2024-05-23 18:59:35 +020075 default 0x400 if !SPL_SHARES_INIT_SP_ADDR
Heiko Stuebnerfc367852019-07-16 22:18:21 +020076
Simon Glassf4d60392021-08-08 12:20:12 -060077config SPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020078 default y
79
80config TPL_LDSCRIPT
81 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
82
83config TPL_TEXT_BASE
84 default 0xff0e1000
85
Heiko Stuebnerfc367852019-07-16 22:18:21 +020086config TPL_STACK
87 default 0xff0e4fff
88
Quentin Schulz2e720162024-05-23 18:59:34 +020089config TPL_SYS_MALLOC_F_LEN
90 default 0x600
91
Paul Kocialkowski7250b232019-11-28 15:27:51 +010092config DEBUG_UART_CHANNEL
93 int "Mux channel to use for debug UART2/UART3"
Heiko Stuebnerfc367852019-07-16 22:18:21 +020094 depends on DEBUG_UART_BOARD_INIT
95 default 0
96 help
Paul Kocialkowski7250b232019-11-28 15:27:51 +010097 UART2 and UART3 can use two different set of pins to route the output.
Heiko Stuebnerfc367852019-07-16 22:18:21 +020098 For using the UART for early debugging the route to use needs
99 to be declared (0 or 1).
100
Jagan Teki57a0a562020-10-28 19:03:45 +0530101source "board/engicam/px30_core/Kconfig"
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200102source "board/hardkernel/odroid_go2/Kconfig"
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200103source "board/rockchip/evb_px30/Kconfig"
Quentin Schulz00a6f602023-01-09 11:36:45 +0100104source "board/theobroma-systems/ringneck_px30/Kconfig"
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200105
106endif