Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 2 | /* |
| 3 | * spi driver for rockchip |
| 4 | * |
Philipp Tomsich | 8e45399 | 2019-02-03 16:17:31 +0100 | [diff] [blame] | 5 | * (C) 2019 Theobroma Systems Design und Consulting GmbH |
| 6 | * |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 7 | * (C) Copyright 2015 Google, Inc |
| 8 | * |
| 9 | * (C) Copyright 2008-2013 Rockchip Electronics |
| 10 | * Peter, Software Engineering, <superpeter.cai@gmail.com>. |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <clk.h> |
| 15 | #include <dm.h> |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 16 | #include <dt-structs.h> |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 17 | #include <errno.h> |
| 18 | #include <spi.h> |
Simon Glass | 495a5dc | 2019-11-14 12:57:30 -0700 | [diff] [blame] | 19 | #include <time.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 20 | #include <linux/errno.h> |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 21 | #include <asm/io.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 22 | #include <asm/arch-rockchip/clock.h> |
| 23 | #include <asm/arch-rockchip/periph.h> |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 24 | #include <dm/pinctrl.h> |
| 25 | #include "rk_spi.h" |
| 26 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 27 | /* Change to 1 to output registers at the start of each transaction */ |
| 28 | #define DEBUG_RK_SPI 0 |
| 29 | |
Jagan Teki | 46bbff1 | 2019-12-21 13:24:30 +0530 | [diff] [blame] | 30 | /* |
| 31 | * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However, |
| 32 | * the controller seems to hang when given 0x10000, so stick with this for now. |
| 33 | */ |
| 34 | #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff |
| 35 | |
Philipp Tomsich | 8d1b09c | 2019-02-03 16:17:32 +0100 | [diff] [blame] | 36 | struct rockchip_spi_params { |
| 37 | /* RXFIFO overruns and TXFIFO underruns stop the master clock */ |
| 38 | bool master_manages_fifo; |
| 39 | }; |
| 40 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 41 | struct rockchip_spi_platdata { |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 42 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 43 | struct dtd_rockchip_rk3288_spi of_plat; |
| 44 | #endif |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 45 | s32 frequency; /* Default clock frequency, -1 for none */ |
| 46 | fdt_addr_t base; |
| 47 | uint deactivate_delay_us; /* Delay to wait after deactivate */ |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 48 | uint activate_delay_us; /* Delay to wait after activate */ |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | struct rockchip_spi_priv { |
| 52 | struct rockchip_spi *regs; |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 53 | struct clk clk; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 54 | unsigned int max_freq; |
| 55 | unsigned int mode; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 56 | ulong last_transaction_us; /* Time of last transaction end */ |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 57 | unsigned int speed_hz; |
Simon Glass | 30508e9 | 2016-01-21 19:44:03 -0700 | [diff] [blame] | 58 | unsigned int last_speed_hz; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 59 | uint input_rate; |
| 60 | }; |
| 61 | |
| 62 | #define SPI_FIFO_DEPTH 32 |
| 63 | |
| 64 | static void rkspi_dump_regs(struct rockchip_spi *regs) |
| 65 | { |
| 66 | debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); |
| 67 | debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); |
| 68 | debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); |
| 69 | debug("ser: \t\t0x%08x\n", readl(®s->ser)); |
| 70 | debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); |
| 71 | debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); |
| 72 | debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); |
| 73 | debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); |
| 74 | debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); |
| 75 | debug("sr: \t\t0x%08x\n", readl(®s->sr)); |
| 76 | debug("imr: \t\t0x%08x\n", readl(®s->imr)); |
| 77 | debug("isr: \t\t0x%08x\n", readl(®s->isr)); |
| 78 | debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); |
| 79 | debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); |
| 80 | debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); |
| 81 | } |
| 82 | |
| 83 | static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable) |
| 84 | { |
| 85 | writel(enable ? 1 : 0, ®s->enr); |
| 86 | } |
| 87 | |
| 88 | static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) |
| 89 | { |
Philipp Tomsich | 0f5b4c9 | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 90 | /* |
| 91 | * We should try not to exceed the speed requested by the caller: |
| 92 | * when selecting a divider, we need to make sure we round up. |
| 93 | */ |
| 94 | uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 95 | |
Philipp Tomsich | 0f5b4c9 | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 96 | /* The baudrate register (BAUDR) is defined as a 32bit register where |
| 97 | * the upper 16bit are reserved and having 'Fsclk_out' in the lower |
| 98 | * 16bits with 'Fsclk_out' defined as follows: |
| 99 | * |
| 100 | * Fsclk_out = Fspi_clk/ SCKDV |
| 101 | * Where SCKDV is any even value between 2 and 65534. |
| 102 | */ |
| 103 | if (clk_div > 0xfffe) { |
| 104 | clk_div = 0xfffe; |
Heinrich Schuchardt | 348c878 | 2017-11-12 20:59:44 +0100 | [diff] [blame] | 105 | debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n", |
Philipp Tomsich | 0f5b4c9 | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 106 | __func__, speed, priv->input_rate / clk_div); |
| 107 | } |
| 108 | |
| 109 | /* Round up to the next even 16bit number */ |
| 110 | clk_div = (clk_div + 1) & 0xfffe; |
| 111 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 112 | debug("spi speed %u, div %u\n", speed, clk_div); |
| 113 | |
Philipp Tomsich | 0f5b4c9 | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 114 | clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); |
Simon Glass | 30508e9 | 2016-01-21 19:44:03 -0700 | [diff] [blame] | 115 | priv->last_speed_hz = speed; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | static int rkspi_wait_till_not_busy(struct rockchip_spi *regs) |
| 119 | { |
| 120 | unsigned long start; |
| 121 | |
| 122 | start = get_timer(0); |
| 123 | while (readl(®s->sr) & SR_BUSY) { |
| 124 | if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) { |
| 125 | debug("RK SPI: Status keeps busy for 1000us after a read/write!\n"); |
| 126 | return -ETIMEDOUT; |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 133 | static void spi_cs_activate(struct udevice *dev, uint cs) |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 134 | { |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 135 | struct udevice *bus = dev->parent; |
| 136 | struct rockchip_spi_platdata *plat = bus->platdata; |
| 137 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 138 | struct rockchip_spi *regs = priv->regs; |
| 139 | |
Simon Glass | cf65b00 | 2016-11-13 14:22:03 -0700 | [diff] [blame] | 140 | /* If it's too soon to do another transaction, wait */ |
| 141 | if (plat->deactivate_delay_us && priv->last_transaction_us) { |
| 142 | ulong delay_us; /* The delay completed so far */ |
| 143 | delay_us = timer_get_us() - priv->last_transaction_us; |
Philipp Tomsich | 8cb1d58 | 2019-02-03 16:17:26 +0100 | [diff] [blame] | 144 | if (delay_us < plat->deactivate_delay_us) { |
| 145 | ulong additional_delay_us = |
| 146 | plat->deactivate_delay_us - delay_us; |
| 147 | debug("%s: delaying by %ld us\n", |
| 148 | __func__, additional_delay_us); |
| 149 | udelay(additional_delay_us); |
| 150 | } |
Simon Glass | cf65b00 | 2016-11-13 14:22:03 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 153 | debug("activate cs%u\n", cs); |
| 154 | writel(1 << cs, ®s->ser); |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 155 | if (plat->activate_delay_us) |
| 156 | udelay(plat->activate_delay_us); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 157 | } |
| 158 | |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 159 | static void spi_cs_deactivate(struct udevice *dev, uint cs) |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 160 | { |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 161 | struct udevice *bus = dev->parent; |
| 162 | struct rockchip_spi_platdata *plat = bus->platdata; |
| 163 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 164 | struct rockchip_spi *regs = priv->regs; |
| 165 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 166 | debug("deactivate cs%u\n", cs); |
| 167 | writel(0, ®s->ser); |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 168 | |
| 169 | /* Remember time of this transaction so we can honour the bus delay */ |
| 170 | if (plat->deactivate_delay_us) |
| 171 | priv->last_transaction_us = timer_get_us(); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 172 | } |
| 173 | |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 174 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 175 | static int conv_of_platdata(struct udevice *dev) |
| 176 | { |
| 177 | struct rockchip_spi_platdata *plat = dev->platdata; |
| 178 | struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; |
| 179 | struct rockchip_spi_priv *priv = dev_get_priv(dev); |
| 180 | int ret; |
| 181 | |
| 182 | plat->base = dtplat->reg[0]; |
| 183 | plat->frequency = 20000000; |
| 184 | ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); |
| 185 | if (ret < 0) |
| 186 | return ret; |
| 187 | dev->req_seq = 0; |
| 188 | |
| 189 | return 0; |
| 190 | } |
| 191 | #endif |
| 192 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 193 | static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) |
| 194 | { |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 195 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 196 | struct rockchip_spi_platdata *plat = dev_get_platdata(bus); |
Simon Glass | a95049e | 2016-01-21 19:43:43 -0700 | [diff] [blame] | 197 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 198 | int ret; |
| 199 | |
Philipp Tomsich | 828dbb5 | 2017-09-11 22:04:20 +0200 | [diff] [blame] | 200 | plat->base = dev_read_addr(bus); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 201 | |
Simon Glass | a95049e | 2016-01-21 19:43:43 -0700 | [diff] [blame] | 202 | ret = clk_get_by_index(bus, 0, &priv->clk); |
| 203 | if (ret < 0) { |
| 204 | debug("%s: Could not get clock for %s: %d\n", __func__, |
| 205 | bus->name, ret); |
| 206 | return ret; |
| 207 | } |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 208 | |
Philipp Tomsich | 778ec66 | 2017-06-07 18:45:58 +0200 | [diff] [blame] | 209 | plat->frequency = |
| 210 | dev_read_u32_default(bus, "spi-max-frequency", 50000000); |
| 211 | plat->deactivate_delay_us = |
| 212 | dev_read_u32_default(bus, "spi-deactivate-delay", 0); |
| 213 | plat->activate_delay_us = |
| 214 | dev_read_u32_default(bus, "spi-activate-delay", 0); |
| 215 | |
Simon Glass | c45aec9 | 2016-01-21 19:44:12 -0700 | [diff] [blame] | 216 | debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", |
| 217 | __func__, (uint)plat->base, plat->frequency, |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 218 | plat->deactivate_delay_us); |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 219 | #endif |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 220 | |
| 221 | return 0; |
| 222 | } |
| 223 | |
Philipp Tomsich | 4544788 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 224 | static int rockchip_spi_calc_modclk(ulong max_freq) |
| 225 | { |
Philipp Tomsich | c720b89 | 2017-07-25 16:25:30 +0200 | [diff] [blame] | 226 | /* |
| 227 | * While this is not strictly correct for the RK3368, as the |
| 228 | * GPLL will be 576MHz, things will still work, as the |
| 229 | * clk_set_rate(...) implementation in our clock-driver will |
| 230 | * chose the next closest rate not exceeding what we request |
| 231 | * based on the output of this function. |
| 232 | */ |
| 233 | |
Philipp Tomsich | 4544788 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 234 | unsigned div; |
| 235 | const unsigned long gpll_hz = 594000000UL; |
| 236 | |
| 237 | /* |
| 238 | * We need to find an input clock that provides at least twice |
| 239 | * the maximum frequency and can be generated from the assumed |
| 240 | * speed of GPLL (594MHz) using an integer divider. |
| 241 | * |
| 242 | * To give us more achievable bitrates at higher speeds (these |
| 243 | * are generated by dividing by an even 16-bit integer from |
| 244 | * this frequency), we try to have an input frequency of at |
| 245 | * least 4x our max_freq. |
| 246 | */ |
| 247 | |
| 248 | div = DIV_ROUND_UP(gpll_hz, max_freq * 4); |
| 249 | return gpll_hz / div; |
| 250 | } |
| 251 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 252 | static int rockchip_spi_probe(struct udevice *bus) |
| 253 | { |
| 254 | struct rockchip_spi_platdata *plat = dev_get_platdata(bus); |
| 255 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 256 | int ret; |
| 257 | |
| 258 | debug("%s: probe\n", __func__); |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 259 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 260 | ret = conv_of_platdata(bus); |
| 261 | if (ret) |
| 262 | return ret; |
| 263 | #endif |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 264 | priv->regs = (struct rockchip_spi *)plat->base; |
| 265 | |
| 266 | priv->last_transaction_us = timer_get_us(); |
| 267 | priv->max_freq = plat->frequency; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 268 | |
Philipp Tomsich | 4544788 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 269 | /* Clamp the value from the DTS against any hardware limits */ |
| 270 | if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE) |
| 271 | priv->max_freq = ROCKCHIP_SPI_MAX_RATE; |
| 272 | |
| 273 | /* Find a module-input clock that fits with the max_freq setting */ |
| 274 | ret = clk_set_rate(&priv->clk, |
| 275 | rockchip_spi_calc_modclk(priv->max_freq)); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 276 | if (ret < 0) { |
| 277 | debug("%s: Failed to set clock: %d\n", __func__, ret); |
| 278 | return ret; |
| 279 | } |
| 280 | priv->input_rate = ret; |
| 281 | debug("%s: rate = %u\n", __func__, priv->input_rate); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static int rockchip_spi_claim_bus(struct udevice *dev) |
| 287 | { |
| 288 | struct udevice *bus = dev->parent; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 289 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 290 | struct rockchip_spi *regs = priv->regs; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 291 | uint ctrlr0; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 292 | |
| 293 | /* Disable the SPI hardware */ |
Philipp Tomsich | 5755fff | 2019-02-03 16:17:29 +0100 | [diff] [blame] | 294 | rkspi_enable_chip(regs, false); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 295 | |
Simon Glass | 30508e9 | 2016-01-21 19:44:03 -0700 | [diff] [blame] | 296 | if (priv->speed_hz != priv->last_speed_hz) |
| 297 | rkspi_set_clk(priv, priv->speed_hz); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 298 | |
| 299 | /* Operation Mode */ |
| 300 | ctrlr0 = OMOD_MASTER << OMOD_SHIFT; |
| 301 | |
| 302 | /* Data Frame Size */ |
Philipp Tomsich | 1b35a51 | 2019-02-03 16:17:27 +0100 | [diff] [blame] | 303 | ctrlr0 |= DFS_8BIT << DFS_SHIFT; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 304 | |
| 305 | /* set SPI mode 0..3 */ |
| 306 | if (priv->mode & SPI_CPOL) |
| 307 | ctrlr0 |= SCOL_HIGH << SCOL_SHIFT; |
| 308 | if (priv->mode & SPI_CPHA) |
| 309 | ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT; |
| 310 | |
| 311 | /* Chip Select Mode */ |
| 312 | ctrlr0 |= CSM_KEEP << CSM_SHIFT; |
| 313 | |
| 314 | /* SSN to Sclk_out delay */ |
| 315 | ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT; |
| 316 | |
| 317 | /* Serial Endian Mode */ |
| 318 | ctrlr0 |= SEM_LITTLE << SEM_SHIFT; |
| 319 | |
| 320 | /* First Bit Mode */ |
| 321 | ctrlr0 |= FBM_MSB << FBM_SHIFT; |
| 322 | |
| 323 | /* Byte and Halfword Transform */ |
Philipp Tomsich | 1b35a51 | 2019-02-03 16:17:27 +0100 | [diff] [blame] | 324 | ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 325 | |
| 326 | /* Rxd Sample Delay */ |
| 327 | ctrlr0 |= 0 << RXDSD_SHIFT; |
| 328 | |
| 329 | /* Frame Format */ |
| 330 | ctrlr0 |= FRF_SPI << FRF_SHIFT; |
| 331 | |
| 332 | /* Tx and Rx mode */ |
Philipp Tomsich | 1b35a51 | 2019-02-03 16:17:27 +0100 | [diff] [blame] | 333 | ctrlr0 |= TMOD_TR << TMOD_SHIFT; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 334 | |
| 335 | writel(ctrlr0, ®s->ctrlr0); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 336 | |
| 337 | return 0; |
| 338 | } |
| 339 | |
| 340 | static int rockchip_spi_release_bus(struct udevice *dev) |
| 341 | { |
Simon Glass | 2c9693c | 2016-01-21 19:44:11 -0700 | [diff] [blame] | 342 | struct udevice *bus = dev->parent; |
| 343 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 344 | |
| 345 | rkspi_enable_chip(priv->regs, false); |
| 346 | |
Philipp Tomsich | 8e45399 | 2019-02-03 16:17:31 +0100 | [diff] [blame] | 347 | return 0; |
| 348 | } |
| 349 | |
| 350 | static inline int rockchip_spi_16bit_reader(struct udevice *dev, |
| 351 | u8 **din, int *len) |
| 352 | { |
| 353 | struct udevice *bus = dev->parent; |
| 354 | const struct rockchip_spi_params * const data = |
| 355 | (void *)dev_get_driver_data(bus); |
| 356 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 357 | struct rockchip_spi *regs = priv->regs; |
| 358 | const u32 saved_ctrlr0 = readl(®s->ctrlr0); |
| 359 | #if defined(DEBUG) |
| 360 | u32 statistics_rxlevels[33] = { }; |
| 361 | #endif |
| 362 | u32 frames = *len / 2; |
Philipp Tomsich | 09258c9 | 2019-02-03 16:17:33 +0100 | [diff] [blame] | 363 | u8 *in = (u8 *)(*din); |
Philipp Tomsich | 8e45399 | 2019-02-03 16:17:31 +0100 | [diff] [blame] | 364 | u32 max_chunk_size = SPI_FIFO_DEPTH; |
| 365 | |
| 366 | if (!frames) |
| 367 | return 0; |
| 368 | |
| 369 | /* |
Philipp Tomsich | 8d1b09c | 2019-02-03 16:17:32 +0100 | [diff] [blame] | 370 | * If we know that the hardware will manage RXFIFO overruns |
| 371 | * (i.e. stop the SPI clock until there's space in the FIFO), |
| 372 | * we the allow largest possible chunk size that can be |
| 373 | * represented in CTRLR1. |
| 374 | */ |
| 375 | if (data && data->master_manages_fifo) |
Jagan Teki | 46bbff1 | 2019-12-21 13:24:30 +0530 | [diff] [blame] | 376 | max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN; |
Philipp Tomsich | 8d1b09c | 2019-02-03 16:17:32 +0100 | [diff] [blame] | 377 | |
Philipp Tomsich | 8e45399 | 2019-02-03 16:17:31 +0100 | [diff] [blame] | 378 | // rockchip_spi_configure(dev, mode, size) |
| 379 | rkspi_enable_chip(regs, false); |
| 380 | clrsetbits_le32(®s->ctrlr0, |
| 381 | TMOD_MASK << TMOD_SHIFT, |
| 382 | TMOD_RO << TMOD_SHIFT); |
| 383 | /* 16bit data frame size */ |
| 384 | clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT); |
| 385 | |
| 386 | /* Update caller's context */ |
| 387 | const u32 bytes_to_process = 2 * frames; |
| 388 | *din += bytes_to_process; |
| 389 | *len -= bytes_to_process; |
| 390 | |
| 391 | /* Process our frames */ |
| 392 | while (frames) { |
| 393 | u32 chunk_size = min(frames, max_chunk_size); |
| 394 | |
| 395 | frames -= chunk_size; |
| 396 | |
| 397 | writew(chunk_size - 1, ®s->ctrlr1); |
| 398 | rkspi_enable_chip(regs, true); |
| 399 | |
| 400 | do { |
| 401 | u32 rx_level = readw(®s->rxflr); |
| 402 | #if defined(DEBUG) |
| 403 | statistics_rxlevels[rx_level]++; |
| 404 | #endif |
| 405 | chunk_size -= rx_level; |
Philipp Tomsich | 09258c9 | 2019-02-03 16:17:33 +0100 | [diff] [blame] | 406 | while (rx_level--) { |
| 407 | u16 val = readw(regs->rxdr); |
| 408 | *in++ = val & 0xff; |
| 409 | *in++ = val >> 8; |
| 410 | } |
Philipp Tomsich | 8e45399 | 2019-02-03 16:17:31 +0100 | [diff] [blame] | 411 | } while (chunk_size); |
| 412 | |
| 413 | rkspi_enable_chip(regs, false); |
| 414 | } |
| 415 | |
| 416 | #if defined(DEBUG) |
| 417 | debug("%s: observed rx_level during processing:\n", __func__); |
| 418 | for (int i = 0; i <= 32; ++i) |
| 419 | if (statistics_rxlevels[i]) |
| 420 | debug("\t%2d: %d\n", i, statistics_rxlevels[i]); |
| 421 | #endif |
| 422 | /* Restore the original transfer setup and return error-free. */ |
| 423 | writel(saved_ctrlr0, ®s->ctrlr0); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 424 | return 0; |
| 425 | } |
| 426 | |
| 427 | static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 428 | const void *dout, void *din, unsigned long flags) |
| 429 | { |
| 430 | struct udevice *bus = dev->parent; |
| 431 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 432 | struct rockchip_spi *regs = priv->regs; |
| 433 | struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); |
| 434 | int len = bitlen >> 3; |
| 435 | const u8 *out = dout; |
| 436 | u8 *in = din; |
| 437 | int toread, towrite; |
Philipp Tomsich | 8e45399 | 2019-02-03 16:17:31 +0100 | [diff] [blame] | 438 | int ret = 0; |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 439 | |
| 440 | debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, |
| 441 | len, flags); |
| 442 | if (DEBUG_RK_SPI) |
| 443 | rkspi_dump_regs(regs); |
| 444 | |
| 445 | /* Assert CS before transfer */ |
| 446 | if (flags & SPI_XFER_BEGIN) |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 447 | spi_cs_activate(dev, slave_plat->cs); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 448 | |
Philipp Tomsich | 8e45399 | 2019-02-03 16:17:31 +0100 | [diff] [blame] | 449 | /* |
| 450 | * To ensure fast loading of firmware images (e.g. full U-Boot |
| 451 | * stage, ATF, Linux kernel) from SPI flash, we optimise the |
| 452 | * case of read-only transfers by using the full 16bits of each |
| 453 | * FIFO element. |
| 454 | */ |
| 455 | if (!out) |
| 456 | ret = rockchip_spi_16bit_reader(dev, &in, &len); |
| 457 | |
| 458 | /* This is the original 8bit reader/writer code */ |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 459 | while (len > 0) { |
Jagan Teki | 46bbff1 | 2019-12-21 13:24:30 +0530 | [diff] [blame] | 460 | int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 461 | |
Simon Glass | 2c9693c | 2016-01-21 19:44:11 -0700 | [diff] [blame] | 462 | rkspi_enable_chip(regs, false); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 463 | writel(todo - 1, ®s->ctrlr1); |
| 464 | rkspi_enable_chip(regs, true); |
| 465 | |
| 466 | toread = todo; |
| 467 | towrite = todo; |
| 468 | while (toread || towrite) { |
| 469 | u32 status = readl(®s->sr); |
| 470 | |
| 471 | if (towrite && !(status & SR_TF_FULL)) { |
| 472 | writel(out ? *out++ : 0, regs->txdr); |
| 473 | towrite--; |
| 474 | } |
| 475 | if (toread && !(status & SR_RF_EMPT)) { |
| 476 | u32 byte = readl(regs->rxdr); |
| 477 | |
| 478 | if (in) |
| 479 | *in++ = byte; |
| 480 | toread--; |
| 481 | } |
| 482 | } |
Philipp Tomsich | e3cc1a2 | 2019-02-03 16:17:30 +0100 | [diff] [blame] | 483 | |
| 484 | /* |
| 485 | * In case that there's a transmit-component, we need to wait |
| 486 | * until the control goes idle before we can disable the SPI |
| 487 | * control logic (as this will implictly flush the FIFOs). |
| 488 | */ |
| 489 | if (out) { |
| 490 | ret = rkspi_wait_till_not_busy(regs); |
| 491 | if (ret) |
| 492 | break; |
| 493 | } |
| 494 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 495 | len -= todo; |
| 496 | } |
| 497 | |
| 498 | /* Deassert CS after transfer */ |
| 499 | if (flags & SPI_XFER_END) |
Simon Glass | 58a52e8 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 500 | spi_cs_deactivate(dev, slave_plat->cs); |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 501 | |
| 502 | rkspi_enable_chip(regs, false); |
| 503 | |
| 504 | return ret; |
| 505 | } |
| 506 | |
| 507 | static int rockchip_spi_set_speed(struct udevice *bus, uint speed) |
| 508 | { |
| 509 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 510 | |
Philipp Tomsich | 4544788 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 511 | /* Clamp to the maximum frequency specified in the DTS */ |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 512 | if (speed > priv->max_freq) |
| 513 | speed = priv->max_freq; |
Philipp Tomsich | 4544788 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 514 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 515 | priv->speed_hz = speed; |
| 516 | |
| 517 | return 0; |
| 518 | } |
| 519 | |
| 520 | static int rockchip_spi_set_mode(struct udevice *bus, uint mode) |
| 521 | { |
| 522 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 523 | |
| 524 | priv->mode = mode; |
| 525 | |
| 526 | return 0; |
| 527 | } |
| 528 | |
| 529 | static const struct dm_spi_ops rockchip_spi_ops = { |
| 530 | .claim_bus = rockchip_spi_claim_bus, |
| 531 | .release_bus = rockchip_spi_release_bus, |
| 532 | .xfer = rockchip_spi_xfer, |
| 533 | .set_speed = rockchip_spi_set_speed, |
| 534 | .set_mode = rockchip_spi_set_mode, |
| 535 | /* |
| 536 | * cs_info is not needed, since we require all chip selects to be |
| 537 | * in the device tree explicitly |
| 538 | */ |
| 539 | }; |
| 540 | |
Philipp Tomsich | 8d1b09c | 2019-02-03 16:17:32 +0100 | [diff] [blame] | 541 | const struct rockchip_spi_params rk3399_spi_params = { |
| 542 | .master_manages_fifo = true, |
| 543 | }; |
| 544 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 545 | static const struct udevice_id rockchip_spi_ids[] = { |
| 546 | { .compatible = "rockchip,rk3288-spi" }, |
Philipp Tomsich | 8d1b09c | 2019-02-03 16:17:32 +0100 | [diff] [blame] | 547 | { .compatible = "rockchip,rk3368-spi", |
| 548 | .data = (ulong)&rk3399_spi_params }, |
| 549 | { .compatible = "rockchip,rk3399-spi", |
| 550 | .data = (ulong)&rk3399_spi_params }, |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 551 | { } |
| 552 | }; |
| 553 | |
| 554 | U_BOOT_DRIVER(rockchip_spi) = { |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 555 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 556 | .name = "rockchip_rk3288_spi", |
| 557 | #else |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 558 | .name = "rockchip_spi", |
Simon Glass | 32308d2 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 559 | #endif |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 560 | .id = UCLASS_SPI, |
| 561 | .of_match = rockchip_spi_ids, |
| 562 | .ops = &rockchip_spi_ops, |
| 563 | .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata, |
| 564 | .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata), |
| 565 | .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv), |
| 566 | .probe = rockchip_spi_probe, |
| 567 | }; |