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git01.mediatek.com / filogic / uboot / 67d544a86efe6aebc870ab83bbe056846ba0be87 / . / arch / arm / dts / rk3288.dtsi
blob: da518783e204ae9dd0044cd2f82d9006ddbdf5d1 [file] [log] [blame]
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]1/*
2 * SPDX-License-Identifier: GPL-2.0+
3 */
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/pinctrl/rockchip.h>
9#include <dt-bindings/clock/rk3288-cru.h>
10#include <dt-bindings/power-domain/rk3288.h>
11#include <dt-bindings/thermal/thermal.h>
Jacob Chen17fd3442016-03-14 11:20:17 +0800[diff] [blame]12#include <dt-bindings/video/rk3288.h>
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]13#include "skeleton.dtsi"
14
15/ {
16 compatible = "rockchip,rk3288";
17
18 interrupt-parent = <&gic>;
19 aliases {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 gpio2 = &gpio2;
23 gpio3 = &gpio3;
24 gpio4 = &gpio4;
25 gpio5 = &gpio5;
26 gpio6 = &gpio6;
27 gpio7 = &gpio7;
28 gpio8 = &gpio8;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]29 i2c0 = &i2c0;
30 i2c1 = &i2c1;
31 i2c2 = &i2c2;
32 i2c3 = &i2c3;
33 i2c4 = &i2c4;
34 i2c5 = &i2c5;
35 mmc0 = &emmc;
36 mmc1 = &sdmmc;
37 mmc2 = &sdio0;
38 mmc3 = &sdio1;
39 mshc0 = &emmc;
40 mshc1 = &sdmmc;
41 mshc2 = &sdio0;
42 mshc3 = &sdio1;
43 serial0 = &uart0;
44 serial1 = &uart1;
45 serial2 = &uart2;
46 serial3 = &uart3;
47 serial4 = &uart4;
48 spi0 = &spi0;
49 spi1 = &spi1;
50 spi2 = &spi2;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56 enable-method = "rockchip,rk3066-smp";
57 rockchip,pmu = <&pmu>;
58
59 cpu0: cpu@500 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a12";
62 reg = <0x500>;
63 operating-points = <
64 /* KHz uV */
65 1800000 1400000
66 1704000 1350000
67 1608000 1300000
68 1512000 1250000
69 1416000 1200000
70 1200000 1100000
71 1008000 1050000
72 816000 1000000
73 696000 950000
74 600000 900000
75 408000 900000
76 216000 900000
77 126000 900000
78 >;
79 #cooling-cells = <2>; /* min followed by max */
80 clock-latency = <40000>;
81 clocks = <&cru ARMCLK>;
82 resets = <&cru SRST_CORE0>;
83 };
84 cpu@501 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a12";
87 reg = <0x501>;
88 resets = <&cru SRST_CORE1>;
89 };
90 cpu@502 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a12";
93 reg = <0x502>;
94 resets = <&cru SRST_CORE2>;
95 };
96 cpu@503 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a12";
99 reg = <0x503>;
100 resets = <&cru SRST_CORE3>;
101 };
102 };
103
104 amba {
105 compatible = "arm,amba-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges;
109
110 dmac_peri: dma-controller@ff250000 {
111 compatible = "arm,pl330", "arm,primecell";
112 broken-no-flushp;
113 reg = <0xff250000 0x4000>;
114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
116 #dma-cells = <1>;
117 clocks = <&cru ACLK_DMAC2>;
118 clock-names = "apb_pclk";
119 };
120
121 dmac_bus_ns: dma-controller@ff600000 {
122 compatible = "arm,pl330", "arm,primecell";
123 broken-no-flushp;
124 reg = <0xff600000 0x4000>;
125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
127 #dma-cells = <1>;
128 clocks = <&cru ACLK_DMAC1>;
129 clock-names = "apb_pclk";
130 status = "disabled";
131 };
132
133 dmac_bus_s: dma-controller@ffb20000 {
134 compatible = "arm,pl330", "arm,primecell";
135 broken-no-flushp;
136 reg = <0xffb20000 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139 #dma-cells = <1>;
140 clocks = <&cru ACLK_DMAC1>;
141 clock-names = "apb_pclk";
142 };
143 };
144
145 xin24m: oscillator {
146 compatible = "fixed-clock";
147 clock-frequency = <24000000>;
148 clock-output-names = "xin24m";
149 #clock-cells = <0>;
150 };
151
152 timer {
153 arm,use-physical-timer;
154 compatible = "arm,armv7-timer";
155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
159 clock-frequency = <24000000>;
160 always-on;
161 };
162
163 display-subsystem {
164 compatible = "rockchip,display-subsystem";
165 ports = <&vopl_out>, <&vopb_out>;
166 };
167
168 sdmmc: dwmmc@ff0c0000 {
169 compatible = "rockchip,rk3288-dw-mshc";
Kever Yangd0947322017-06-14 16:31:44 +0800[diff] [blame]170 max-frequency = <150000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]171 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
172 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
173 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
174 fifo-depth = <0x100>;
175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 reg = <0xff0c0000 0x4000>;
177 status = "disabled";
178 };
179
180 sdio0: dwmmc@ff0d0000 {
181 compatible = "rockchip,rk3288-dw-mshc";
Kever Yangd0947322017-06-14 16:31:44 +0800[diff] [blame]182 max-frequency = <150000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]183 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
184 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
185 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
186 fifo-depth = <0x100>;
187 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
188 reg = <0xff0d0000 0x4000>;
189 status = "disabled";
190 };
191
192 sdio1: dwmmc@ff0e0000 {
193 compatible = "rockchip,rk3288-dw-mshc";
Kever Yangd0947322017-06-14 16:31:44 +0800[diff] [blame]194 max-frequency = <150000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]195 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
196 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
197 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
198 fifo-depth = <0x100>;
199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
200 reg = <0xff0e0000 0x4000>;
201 status = "disabled";
202 };
203
204 emmc: dwmmc@ff0f0000 {
205 compatible = "rockchip,rk3288-dw-mshc";
Kever Yangd0947322017-06-14 16:31:44 +0800[diff] [blame]206 max-frequency = <150000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]207 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
208 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
209 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
210 fifo-depth = <0x100>;
211 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
212 reg = <0xff0f0000 0x4000>;
213 status = "disabled";
214 };
215
216 saradc: saradc@ff100000 {
217 compatible = "rockchip,saradc";
218 reg = <0xff100000 0x100>;
219 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
220 #io-channel-cells = <1>;
221 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
222 clock-names = "saradc", "apb_pclk";
223 status = "disabled";
224 };
225
226 spi0: spi@ff110000 {
227 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
228 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
229 clock-names = "spiclk", "apb_pclk";
230 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
231 dma-names = "tx", "rx";
232 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
235 reg = <0xff110000 0x1000>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 status = "disabled";
239 };
240
241 spi1: spi@ff120000 {
242 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
243 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
244 clock-names = "spiclk", "apb_pclk";
245 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
246 dma-names = "tx", "rx";
247 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
250 reg = <0xff120000 0x1000>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 status = "disabled";
254 };
255
256 spi2: spi@ff130000 {
257 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
258 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
259 clock-names = "spiclk", "apb_pclk";
260 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
261 dma-names = "tx", "rx";
262 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
265 reg = <0xff130000 0x1000>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 status = "disabled";
269 };
270
271 i2c1: i2c@ff140000 {
272 compatible = "rockchip,rk3288-i2c";
273 reg = <0xff140000 0x1000>;
274 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
275 #address-cells = <1>;
276 #size-cells = <0>;
277 clock-names = "i2c";
278 clocks = <&cru PCLK_I2C1>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c1_xfer>;
281 status = "disabled";
282 };
283
284 i2c3: i2c@ff150000 {
285 compatible = "rockchip,rk3288-i2c";
286 reg = <0xff150000 0x1000>;
287 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 clock-names = "i2c";
291 clocks = <&cru PCLK_I2C3>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&i2c3_xfer>;
294 status = "disabled";
295 };
296
297 i2c4: i2c@ff160000 {
298 compatible = "rockchip,rk3288-i2c";
299 reg = <0xff160000 0x1000>;
300 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 clock-names = "i2c";
304 clocks = <&cru PCLK_I2C4>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2c4_xfer>;
307 status = "disabled";
308 };
309
310 i2c5: i2c@ff170000 {
311 compatible = "rockchip,rk3288-i2c";
312 reg = <0xff170000 0x1000>;
313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 clock-names = "i2c";
317 clocks = <&cru PCLK_I2C5>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&i2c5_xfer>;
320 status = "disabled";
321 };
322 uart0: serial@ff180000 {
323 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
324 reg = <0xff180000 0x100>;
325 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
326 reg-shift = <2>;
327 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]328 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]329 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
330 clock-names = "baudclk", "apb_pclk";
331 pinctrl-names = "default";
332 pinctrl-0 = <&uart0_xfer>;
333 status = "disabled";
334 };
335
336 uart1: serial@ff190000 {
337 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
338 reg = <0xff190000 0x100>;
339 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
340 reg-shift = <2>;
341 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]342 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]343 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_pclk";
345 pinctrl-names = "default";
346 pinctrl-0 = <&uart1_xfer>;
347 status = "disabled";
348 };
349
350 uart2: serial@ff690000 {
351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
352 reg = <0xff690000 0x100>;
353 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
354 reg-shift = <2>;
355 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]356 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]357 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
358 clock-names = "baudclk", "apb_pclk";
359 pinctrl-names = "default";
360 pinctrl-0 = <&uart2_xfer>;
361 status = "disabled";
362 };
363 uart3: serial@ff1b0000 {
364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
365 reg = <0xff1b0000 0x100>;
366 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
367 reg-shift = <2>;
368 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]369 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]370 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
371 clock-names = "baudclk", "apb_pclk";
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart3_xfer>;
374 status = "disabled";
375 };
376
377 uart4: serial@ff1c0000 {
378 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
379 reg = <0xff1c0000 0x100>;
380 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
381 reg-shift = <2>;
382 reg-io-width = <4>;
Thomas Chou57ce19f2015-11-19 21:48:08 +0800[diff] [blame]383 clock-frequency = <24000000>;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]384 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
385 clock-names = "baudclk", "apb_pclk";
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart4_xfer>;
388 status = "disabled";
389 };
390 thermal: thermal-zones {
391 #include "rk3288-thermal.dtsi"
392 };
393
394 tsadc: tsadc@ff280000 {
395 compatible = "rockchip,rk3288-tsadc";
396 reg = <0xff280000 0x100>;
397 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
399 clock-names = "tsadc", "apb_pclk";
400 resets = <&cru SRST_TSADC>;
401 reset-names = "tsadc-apb";
402 pinctrl-names = "otp_out";
403 pinctrl-0 = <&otp_out>;
404 #thermal-sensor-cells = <1>;
405 hw-shut-temp = <125000>;
406 status = "disabled";
407 };
408
409 gmac: ethernet@ff290000 {
410 compatible = "rockchip,rk3288-gmac";
411 reg = <0xff290000 0x10000>;
412 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "macirq";
414 rockchip,grf = <&grf>;
415 clocks = <&cru SCLK_MAC>,
416 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
417 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
418 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
419 clock-names = "stmmaceth",
420 "mac_clk_rx", "mac_clk_tx",
421 "clk_mac_ref", "clk_mac_refout",
422 "aclk_mac", "pclk_mac";
423 };
424
425 usb_host0_ehci: usb@ff500000 {
426 compatible = "generic-ehci";
427 reg = <0xff500000 0x100>;
428 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru HCLK_USBHOST0>;
430 clock-names = "usbhost";
431 phys = <&usbphy1>;
432 phy-names = "usb";
433 status = "disabled";
434 };
435
436 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
437
438 usb_host1: usb@ff540000 {
439 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
440 "snps,dwc2";
441 reg = <0xff540000 0x40000>;
442 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cru HCLK_USBHOST1>;
444 clock-names = "otg";
445 phys = <&usbphy2>;
446 phy-names = "usb2-phy";
447 status = "disabled";
448 };
449
450 usb_otg: usb@ff580000 {
451 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
452 "snps,dwc2";
453 reg = <0xff580000 0x40000>;
454 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru HCLK_OTG0>;
456 clock-names = "otg";
Xu Ziyuana11a53f2016-07-15 00:26:59 +0800[diff] [blame]457 dr_mode = "otg";
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]458 phys = <&usbphy0>;
459 phy-names = "usb2-phy";
460 status = "disabled";
461 };
462
463 usb_hsic: usb@ff5c0000 {
464 compatible = "generic-ehci";
465 reg = <0xff5c0000 0x100>;
466 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&cru HCLK_HSIC>;
468 clock-names = "usbhost";
469 status = "disabled";
470 };
471
472 dmc: dmc@ff610000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]473 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]474 compatible = "rockchip,rk3288-dmc", "syscon";
475 rockchip,cru = <&cru>;
476 rockchip,grf = <&grf>;
477 rockchip,pmu = <&pmu>;
478 rockchip,sgrf = <&sgrf>;
479 rockchip,noc = <&noc>;
480 reg = <0xff610000 0x3fc
481 0xff620000 0x294
482 0xff630000 0x3fc
483 0xff640000 0x294>;
484 rockchip,sram = <&ddr_sram>;
485 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
486 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
487 <&cru ARMCLK>;
488 clock-names = "pclk_ddrupctl0", "pclk_publ0",
489 "pclk_ddrupctl1", "pclk_publ1",
490 "arm_clk";
491 };
492
493 i2c0: i2c@ff650000 {
494 compatible = "rockchip,rk3288-i2c";
495 reg = <0xff650000 0x1000>;
496 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 clock-names = "i2c";
500 clocks = <&cru PCLK_I2C0>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_xfer>;
503 status = "disabled";
504 };
505
506 i2c2: i2c@ff660000 {
507 compatible = "rockchip,rk3288-i2c";
508 reg = <0xff660000 0x1000>;
509 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 clock-names = "i2c";
513 clocks = <&cru PCLK_I2C2>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c2_xfer>;
516 status = "disabled";
517 };
518
519 pwm0: pwm@ff680000 {
520 compatible = "rockchip,rk3288-pwm";
521 reg = <0xff680000 0x10>;
522 #pwm-cells = <3>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pwm0_pin>;
525 clocks = <&cru PCLK_PWM>;
526 clock-names = "pwm";
527 rockchip,grf = <&grf>;
528 status = "disabled";
529 };
530
531 pwm1: pwm@ff680010 {
532 compatible = "rockchip,rk3288-pwm";
533 reg = <0xff680010 0x10>;
534 #pwm-cells = <3>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&pwm1_pin>;
537 clocks = <&cru PCLK_PWM>;
538 clock-names = "pwm";
539 rockchip,grf = <&grf>;
540 status = "disabled";
541 };
542
543 pwm2: pwm@ff680020 {
544 compatible = "rockchip,rk3288-pwm";
545 reg = <0xff680020 0x10>;
546 #pwm-cells = <3>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&pwm2_pin>;
549 clocks = <&cru PCLK_PWM>;
550 clock-names = "pwm";
551 rockchip,grf = <&grf>;
552 status = "disabled";
553 };
554
555 pwm3: pwm@ff680030 {
556 compatible = "rockchip,rk3288-pwm";
557 reg = <0xff680030 0x10>;
558 #pwm-cells = <2>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pwm3_pin>;
561 clocks = <&cru PCLK_PWM>;
562 clock-names = "pwm";
563 rockchip,grf = <&grf>;
564 status = "disabled";
565 };
566
567 bus_intmem@ff700000 {
568 compatible = "mmio-sram";
569 reg = <0xff700000 0x18000>;
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges = <0 0xff700000 0x18000>;
573 smp-sram@0 {
574 compatible = "rockchip,rk3066-smp-sram";
575 reg = <0x00 0x10>;
576 };
577 ddr_sram: ddr-sram@1000 {
578 compatible = "rockchip,rk3288-ddr-sram";
579 reg = <0x1000 0x4000>;
580 };
581 };
582
583 sram@ff720000 {
584 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
585 reg = <0xff720000 0x1000>;
586 };
587
588 pmu: power-management@ff730000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]589 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]590 compatible = "rockchip,rk3288-pmu", "syscon";
591 reg = <0xff730000 0x100>;
592 };
593
594 sgrf: syscon@ff740000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]595 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]596 compatible = "rockchip,rk3288-sgrf", "syscon";
597 reg = <0xff740000 0x1000>;
598 };
599
600 cru: clock-controller@ff760000 {
601 compatible = "rockchip,rk3288-cru";
602 reg = <0xff760000 0x1000>;
603 rockchip,grf = <&grf>;
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]604 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]605 #clock-cells = <1>;
606 #reset-cells = <1>;
607 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
608 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
609 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
610 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
611 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
612 <&cru PCLK_PERI>;
613 assigned-clock-rates = <0>, <0>,
614 <594000000>, <400000000>,
615 <500000000>, <300000000>,
616 <150000000>, <75000000>,
617 <300000000>, <150000000>,
618 <75000000>;
619 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
620 };
621
622 grf: syscon@ff770000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]623 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]624 compatible = "rockchip,rk3288-grf", "syscon";
625 reg = <0xff770000 0x1000>;
626 };
627
628 wdt: watchdog@ff800000 {
629 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
630 reg = <0xff800000 0x100>;
631 clocks = <&cru PCLK_WDT>;
632 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
633 status = "disabled";
634 };
635
Simon Glass15019802016-01-21 19:45:21 -0700[diff] [blame]636 spdif: sound@ff88b0000 {
637 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
638 reg = <0xff8b0000 0x10000>;
639 #sound-dai-cells = <0>;
640 clock-names = "hclk", "mclk";
641 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
642 dmas = <&dmac_bus_s 3>;
643 dma-names = "tx";
644 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&spdif_tx>;
647 rockchip,grf = <&grf>;
648 status = "disabled";
649 };
650
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]651 i2s: i2s@ff890000 {
652 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
653 reg = <0xff890000 0x10000>;
654 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
658 dma-names = "tx", "rx";
659 clock-names = "i2s_hclk", "i2s_clk";
660 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&i2s0_bus>;
663 status = "disabled";
664 };
665
666 vopb: vop@ff930000 {
Eric Gao590c4ac2017-05-02 18:32:45 +0800[diff] [blame]667 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]668 compatible = "rockchip,rk3288-vop";
669 reg = <0xff930000 0x19c>;
670 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
672 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
673 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
674 reset-names = "axi", "ahb", "dclk";
675 iommus = <&vopb_mmu>;
676 power-domains = <&power RK3288_PD_VIO>;
677 status = "disabled";
678 vopb_out: port {
679 #address-cells = <1>;
680 #size-cells = <0>;
681 vopb_out_edp: endpoint@0 {
682 reg = <0>;
683 remote-endpoint = <&edp_in_vopb>;
684 };
685 vopb_out_hdmi: endpoint@1 {
686 reg = <1>;
687 remote-endpoint = <&hdmi_in_vopb>;
688 };
Jacob Chen17fd3442016-03-14 11:20:17 +0800[diff] [blame]689 vopb_out_lvds: endpoint@2 {
690 reg = <2>;
691 remote-endpoint = <&lvds_in_vopb>;
692 };
Eric Gao590c4ac2017-05-02 18:32:45 +0800[diff] [blame]693 vopb_out_mipi: endpoint@3 {
694 reg = <3>;
695 remote-endpoint = <&mipi_in_vopb>;
696 };
697
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]698 };
699 };
700
701 vopb_mmu: iommu@ff930300 {
702 compatible = "rockchip,iommu";
703 reg = <0xff930300 0x100>;
704 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
705 interrupt-names = "vopb_mmu";
706 power-domains = <&power RK3288_PD_VIO>;
707 #iommu-cells = <0>;
708 status = "disabled";
709 };
710
711 vopl: vop@ff940000 {
712 compatible = "rockchip,rk3288-vop";
713 reg = <0xff940000 0x19c>;
714 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
716 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
717 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
718 reset-names = "axi", "ahb", "dclk";
719 iommus = <&vopl_mmu>;
720 power-domains = <&power RK3288_PD_VIO>;
721 status = "disabled";
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]722 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]723 vopl_out: port {
724 #address-cells = <1>;
725 #size-cells = <0>;
726 vopl_out_edp: endpoint@0 {
727 reg = <0>;
728 remote-endpoint = <&edp_in_vopl>;
729 };
730 vopl_out_hdmi: endpoint@1 {
731 reg = <1>;
732 remote-endpoint = <&hdmi_in_vopl>;
733 };
Jacob Chen17fd3442016-03-14 11:20:17 +0800[diff] [blame]734 vopl_out_lvds: endpoint@2 {
735 reg = <2>;
736 remote-endpoint = <&lvds_in_vopl>;
737 };
Eric Gao590c4ac2017-05-02 18:32:45 +0800[diff] [blame]738 vopl_out_mipi: endpoint@3 {
739 reg = <3>;
740 remote-endpoint = <&mipi_in_vopl>;
741 };
742
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]743 };
744 };
745
746 vopl_mmu: iommu@ff940300 {
747 compatible = "rockchip,iommu";
748 reg = <0xff940300 0x100>;
749 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
750 interrupt-names = "vopl_mmu";
751 power-domains = <&power RK3288_PD_VIO>;
752 #iommu-cells = <0>;
753 status = "disabled";
754 };
755
756 edp: edp@ff970000 {
757 compatible = "rockchip,rk3288-edp";
758 reg = <0xff970000 0x4000>;
759 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
761 rockchip,grf = <&grf>;
762 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
763 resets = <&cru 111>;
764 reset-names = "edp";
765 power-domains = <&power RK3288_PD_VIO>;
766 status = "disabled";
767 ports {
768 edp_in: port {
769 #address-cells = <1>;
770 #size-cells = <0>;
771 edp_in_vopb: endpoint@0 {
772 reg = <0>;
773 remote-endpoint = <&vopb_out_edp>;
774 };
775 edp_in_vopl: endpoint@1 {
776 reg = <1>;
777 remote-endpoint = <&vopl_out_edp>;
778 };
779 };
780 };
781 };
782
783 hdmi: hdmi@ff980000 {
784 compatible = "rockchip,rk3288-dw-hdmi";
785 reg = <0xff980000 0x20000>;
786 reg-io-width = <4>;
787 ddc-i2c-bus = <&i2c5>;
788 rockchip,grf = <&grf>;
789 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
791 clock-names = "iahb", "isfr";
792 status = "disabled";
793 ports {
794 hdmi_in: port {
795 #address-cells = <1>;
796 #size-cells = <0>;
797 hdmi_in_vopb: endpoint@0 {
798 reg = <0>;
799 remote-endpoint = <&vopb_out_hdmi>;
800 };
801 hdmi_in_vopl: endpoint@1 {
802 reg = <1>;
803 remote-endpoint = <&vopl_out_hdmi>;
804 };
805 };
806 };
807 };
808
Jacob Chen17fd3442016-03-14 11:20:17 +0800[diff] [blame]809 lvds: lvds@ff96c000 {
810 compatible = "rockchip,rk3288-lvds";
811 reg = <0xff96c000 0x4000>;
812 clocks = <&cru PCLK_LVDS_PHY>;
813 clock-names = "pclk_lvds";
814 pinctrl-names = "default";
815 pinctrl-0 = <&lcdc0_ctl>;
816 rockchip,grf = <&grf>;
817 status = "disabled";
818 ports {
819 #address-cells = <1>;
820 #size-cells = <0>;
821 lvds_in: port@0 {
822 reg = <0>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 lvds_in_vopb: endpoint@0 {
826 reg = <0>;
827 remote-endpoint = <&vopb_out_lvds>;
828 };
829 lvds_in_vopl: endpoint@1 {
830 reg = <1>;
831 remote-endpoint = <&vopl_out_lvds>;
832 };
833 };
834 };
835 };
836
Eric Gao590c4ac2017-05-02 18:32:45 +0800[diff] [blame]837 mipi_dsi0: mipi@ff960000 {
838 compatible = "rockchip,rk3288_mipi_dsi";
839 reg = <0xff960000 0x4000>;
840 clocks = <&cru PCLK_MIPI_DSI0>;
841 clock-names = "pclk_mipi";
842 /*pinctrl-names = "default";
843 pinctrl-0 = <&lcdc0_ctl>;*/
844 rockchip,grf = <&grf>;
845 #address-cells = <1>;
846 #size-cells = <0>;
847 status = "disabled";
848 ports {
849 #address-cells = <1>;
850 #size-cells = <0>;
851 reg = <1>;
852 mipi_in: port {
853 #address-cells = <1>;
854 #size-cells = <0>;
855 mipi_in_vopb: endpoint@0 {
856 reg = <0>;
857 remote-endpoint = <&vopb_out_mipi>;
858 };
859 mipi_in_vopl: endpoint@1 {
860 reg = <1>;
861 remote-endpoint = <&vopl_out_mipi>;
862 };
863 };
864 };
865 };
866
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]867 hdmi_audio: hdmi_audio {
868 compatible = "rockchip,rk3288-hdmi-audio";
869 i2s-controller = <&i2s>;
870 status = "disable";
871 };
872
873 vpu: video-codec@ff9a0000 {
874 compatible = "rockchip,rk3288-vpu";
875 reg = <0xff9a0000 0x800>;
876 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
878 interrupt-names = "vepu", "vdpu";
879 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
880 clock-names = "aclk_vcodec", "hclk_vcodec";
881 power-domains = <&power RK3288_PD_VIDEO>;
882 iommus = <&vpu_mmu>;
883 };
884
885 vpu_mmu: iommu@ff9a0800 {
886 compatible = "rockchip,iommu";
887 reg = <0xff9a0800 0x100>;
888 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "vpu_mmu";
890 power-domains = <&power RK3288_PD_VIDEO>;
891 #iommu-cells = <0>;
892 };
893
894 gpu: gpu@ffa30000 {
895 compatible = "arm,malit764",
896 "arm,malit76x",
897 "arm,malit7xx",
898 "arm,mali-midgard";
899 reg = <0xffa30000 0x10000>;
900 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "JOB", "MMU", "GPU";
904 clocks = <&cru ACLK_GPU>;
905 clock-names = "aclk_gpu";
906 operating-points = <
907 /* KHz uV */
908 100000 950000
909 200000 950000
910 300000 1000000
911 400000 1100000
912 /* 500000 1200000 - See crosbug.com/p/33857 */
913 600000 1250000
914 >;
915 power-domains = <&power RK3288_PD_GPU>;
916 status = "disabled";
917 };
918
919 noc: syscon@ffac0000 {
Simon Glass3386b372015-08-30 16:55:21 -0600[diff] [blame]920 u-boot,dm-pre-reloc;
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]921 compatible = "rockchip,rk3288-noc", "syscon";
922 reg = <0xffac0000 0x2000>;
923 };
924
925 efuse: efuse@ffb40000 {
926 compatible = "rockchip,rk3288-efuse";
927 reg = <0xffb40000 0x10000>;
928 status = "disabled";
929 };
930
931 gic: interrupt-controller@ffc01000 {
932 compatible = "arm,gic-400";
933 interrupt-controller;
934 #interrupt-cells = <3>;
935 #address-cells = <0>;
936
937 reg = <0xffc01000 0x1000>,
938 <0xffc02000 0x1000>,
939 <0xffc04000 0x2000>,
940 <0xffc06000 0x2000>;
941 interrupts = <GIC_PPI 9 0xf04>;
942 };
943
944 cpuidle: cpuidle {
945 compatible = "rockchip,rk3288-cpuidle";
946 };
947
948 usbphy: phy {
949 compatible = "rockchip,rk3288-usb-phy";
950 rockchip,grf = <&grf>;
951 #address-cells = <1>;
952 #size-cells = <0>;
953 status = "disabled";
954
955 usbphy0: usb-phy0 {
956 #phy-cells = <0>;
957 reg = <0x320>;
958 clocks = <&cru SCLK_OTGPHY0>;
959 clock-names = "phyclk";
960 };
961
962 usbphy1: usb-phy1 {
963 #phy-cells = <0>;
964 reg = <0x334>;
965 clocks = <&cru SCLK_OTGPHY1>;
966 clock-names = "phyclk";
967 };
968
969 usbphy2: usb-phy2 {
970 #phy-cells = <0>;
971 reg = <0x348>;
972 clocks = <&cru SCLK_OTGPHY2>;
973 clock-names = "phyclk";
974 };
975 };
976
977 pinctrl: pinctrl {
978 compatible = "rockchip,rk3288-pinctrl";
979 rockchip,grf = <&grf>;
980 rockchip,pmu = <&pmu>;
981 #address-cells = <1>;
982 #size-cells = <1>;
983 ranges;
984
985 gpio0: gpio0@ff750000 {
986 compatible = "rockchip,gpio-bank";
987 reg = <0xff750000 0x100>;
988 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cru PCLK_GPIO0>;
990
991 gpio-controller;
992 #gpio-cells = <2>;
993
994 interrupt-controller;
995 #interrupt-cells = <2>;
996 };
997
998 gpio1: gpio1@ff780000 {
999 compatible = "rockchip,gpio-bank";
1000 reg = <0xff780000 0x100>;
1001 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cru PCLK_GPIO1>;
1003
1004 gpio-controller;
1005 #gpio-cells = <2>;
1006
1007 interrupt-controller;
1008 #interrupt-cells = <2>;
1009 };
1010
1011 gpio2: gpio2@ff790000 {
1012 compatible = "rockchip,gpio-bank";
1013 reg = <0xff790000 0x100>;
1014 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cru PCLK_GPIO2>;
1016
1017 gpio-controller;
1018 #gpio-cells = <2>;
1019
1020 interrupt-controller;
1021 #interrupt-cells = <2>;
1022 };
1023
1024 gpio3: gpio3@ff7a0000 {
1025 compatible = "rockchip,gpio-bank";
1026 reg = <0xff7a0000 0x100>;
1027 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&cru PCLK_GPIO3>;
1029
1030 gpio-controller;
1031 #gpio-cells = <2>;
1032
1033 interrupt-controller;
1034 #interrupt-cells = <2>;
1035 };
1036
1037 gpio4: gpio4@ff7b0000 {
1038 compatible = "rockchip,gpio-bank";
1039 reg = <0xff7b0000 0x100>;
1040 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&cru PCLK_GPIO4>;
1042
1043 gpio-controller;
1044 #gpio-cells = <2>;
1045
1046 interrupt-controller;
1047 #interrupt-cells = <2>;
1048 };
1049
1050 gpio5: gpio5@ff7c0000 {
1051 compatible = "rockchip,gpio-bank";
1052 reg = <0xff7c0000 0x100>;
1053 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&cru PCLK_GPIO5>;
1055
1056 gpio-controller;
1057 #gpio-cells = <2>;
1058
1059 interrupt-controller;
1060 #interrupt-cells = <2>;
1061 };
1062
1063 gpio6: gpio6@ff7d0000 {
1064 compatible = "rockchip,gpio-bank";
1065 reg = <0xff7d0000 0x100>;
1066 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&cru PCLK_GPIO6>;
1068
1069 gpio-controller;
1070 #gpio-cells = <2>;
1071
1072 interrupt-controller;
1073 #interrupt-cells = <2>;
1074 };
1075
1076 gpio7: gpio7@ff7e0000 {
1077 compatible = "rockchip,gpio-bank";
1078 reg = <0xff7e0000 0x100>;
1079 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&cru PCLK_GPIO7>;
1081
1082 gpio-controller;
1083 #gpio-cells = <2>;
1084
1085 interrupt-controller;
1086 #interrupt-cells = <2>;
1087 };
1088
1089 gpio8: gpio8@ff7f0000 {
1090 compatible = "rockchip,gpio-bank";
1091 reg = <0xff7f0000 0x100>;
1092 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cru PCLK_GPIO8>;
1094
1095 gpio-controller;
1096 #gpio-cells = <2>;
1097
1098 interrupt-controller;
1099 #interrupt-cells = <2>;
1100 };
1101
1102 pcfg_pull_up: pcfg-pull-up {
1103 bias-pull-up;
1104 };
1105
1106 pcfg_pull_down: pcfg-pull-down {
1107 bias-pull-down;
1108 };
1109
1110 pcfg_pull_none: pcfg-pull-none {
1111 bias-disable;
1112 };
1113
1114 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1115 bias-disable;
1116 drive-strength = <12>;
1117 };
1118
1119 sleep {
1120 global_pwroff: global-pwroff {
1121 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1122 };
1123
1124 ddrio_pwroff: ddrio-pwroff {
1125 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1126 };
1127
1128 ddr0_retention: ddr0-retention {
1129 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1130 };
1131
1132 ddr1_retention: ddr1-retention {
1133 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1134 };
1135 };
1136
1137 i2c0 {
1138 i2c0_xfer: i2c0-xfer {
1139 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1140 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1141 };
1142 };
1143
1144 i2c1 {
1145 i2c1_xfer: i2c1-xfer {
1146 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1147 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1148 };
1149 };
1150
1151 i2c2 {
1152 i2c2_xfer: i2c2-xfer {
1153 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1154 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1155 };
1156 };
1157
1158 i2c3 {
1159 i2c3_xfer: i2c3-xfer {
1160 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1161 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1162 };
1163 };
1164
1165 i2c4 {
1166 i2c4_xfer: i2c4-xfer {
1167 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1168 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1169 };
1170 };
1171
1172 i2c5 {
1173 i2c5_xfer: i2c5-xfer {
1174 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1175 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1176 };
1177 };
1178
1179 i2s0 {
1180 i2s0_bus: i2s0-bus {
1181 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1182 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1183 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1184 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1185 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1186 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1187 };
1188 };
1189
Jacob Chen17fd3442016-03-14 11:20:17 +0800[diff] [blame]1190 lcdc0 {
1191 lcdc0_ctl: lcdc0-ctl {
1192 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1193 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1194 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1195 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1196 };
1197 };
1198
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]1199 sdmmc {
1200 sdmmc_clk: sdmmc-clk {
1201 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1202 };
1203
1204 sdmmc_cmd: sdmmc-cmd {
1205 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1206 };
1207
1208 sdmmc_cd: sdmcc-cd {
1209 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1210 };
1211
1212 sdmmc_bus1: sdmmc-bus1 {
1213 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1214 };
1215
1216 sdmmc_bus4: sdmmc-bus4 {
1217 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1218 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1219 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1220 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1221 };
1222 };
1223
1224 sdio0 {
1225 sdio0_bus1: sdio0-bus1 {
1226 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1227 };
1228
1229 sdio0_bus4: sdio0-bus4 {
1230 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1231 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1232 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1233 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1234 };
1235
1236 sdio0_cmd: sdio0-cmd {
1237 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1238 };
1239
1240 sdio0_clk: sdio0-clk {
1241 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1242 };
1243
1244 sdio0_cd: sdio0-cd {
1245 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1246 };
1247
1248 sdio0_wp: sdio0-wp {
1249 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1250 };
1251
1252 sdio0_pwr: sdio0-pwr {
1253 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1254 };
1255
1256 sdio0_bkpwr: sdio0-bkpwr {
1257 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1258 };
1259
1260 sdio0_int: sdio0-int {
1261 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1262 };
1263 };
1264
1265 sdio1 {
1266 sdio1_bus1: sdio1-bus1 {
1267 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1268 };
1269
1270 sdio1_bus4: sdio1-bus4 {
1271 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1272 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1273 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1274 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1275 };
1276
1277 sdio1_cd: sdio1-cd {
1278 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1279 };
1280
1281 sdio1_wp: sdio1-wp {
1282 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1283 };
1284
1285 sdio1_bkpwr: sdio1-bkpwr {
1286 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1287 };
1288
1289 sdio1_int: sdio1-int {
1290 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1291 };
1292
1293 sdio1_cmd: sdio1-cmd {
1294 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1295 };
1296
1297 sdio1_clk: sdio1-clk {
1298 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1299 };
1300
1301 sdio1_pwr: sdio1-pwr {
1302 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1303 };
1304 };
1305
1306 emmc {
1307 emmc_clk: emmc-clk {
1308 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1309 };
1310
1311 emmc_cmd: emmc-cmd {
1312 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1313 };
1314
1315 emmc_pwr: emmc-pwr {
1316 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1317 };
1318
1319 emmc_bus1: emmc-bus1 {
1320 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1321 };
1322
1323 emmc_bus4: emmc-bus4 {
1324 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1325 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1326 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1327 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1328 };
1329
1330 emmc_bus8: emmc-bus8 {
1331 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1332 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1333 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1334 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1335 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1336 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1337 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1338 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1339 };
1340 };
1341
1342 spi0 {
1343 spi0_clk: spi0-clk {
1344 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1345 };
1346 spi0_cs0: spi0-cs0 {
1347 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1348 };
1349 spi0_tx: spi0-tx {
1350 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1351 };
1352 spi0_rx: spi0-rx {
1353 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1354 };
1355 spi0_cs1: spi0-cs1 {
1356 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1357 };
1358 };
1359 spi1 {
1360 spi1_clk: spi1-clk {
1361 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1362 };
1363 spi1_cs0: spi1-cs0 {
1364 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1365 };
1366 spi1_rx: spi1-rx {
1367 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1368 };
1369 spi1_tx: spi1-tx {
1370 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1371 };
1372 };
1373
1374 spi2 {
1375 spi2_cs1: spi2-cs1 {
1376 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1377 };
1378 spi2_clk: spi2-clk {
1379 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1380 };
1381 spi2_cs0: spi2-cs0 {
1382 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1383 };
1384 spi2_rx: spi2-rx {
1385 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1386 };
1387 spi2_tx: spi2-tx {
1388 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1389 };
1390 };
1391
1392 uart0 {
1393 uart0_xfer: uart0-xfer {
1394 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1395 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1396 };
1397
1398 uart0_cts: uart0-cts {
1399 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1400 };
1401
1402 uart0_rts: uart0-rts {
1403 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1404 };
1405 };
1406
1407 uart1 {
1408 uart1_xfer: uart1-xfer {
1409 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1410 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1411 };
1412
1413 uart1_cts: uart1-cts {
1414 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1415 };
1416
1417 uart1_rts: uart1-rts {
1418 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1419 };
1420 };
1421
1422 uart2 {
1423 uart2_xfer: uart2-xfer {
1424 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1425 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1426 };
1427 /* no rts / cts for uart2 */
1428 };
1429
1430 uart3 {
1431 uart3_xfer: uart3-xfer {
1432 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1433 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1434 };
1435
1436 uart3_cts: uart3-cts {
1437 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1438 };
1439
1440 uart3_rts: uart3-rts {
1441 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1442 };
1443 };
1444
1445 uart4 {
1446 uart4_xfer: uart4-xfer {
1447 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1448 <5 13 3 &pcfg_pull_none>;
1449 };
1450
1451 uart4_cts: uart4-cts {
1452 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1453 };
1454
1455 uart4_rts: uart4-rts {
1456 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1457 };
1458 };
1459
1460 tsadc {
1461 otp_out: otp-out {
1462 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1463 };
1464 };
1465
1466 pwm0 {
1467 pwm0_pin: pwm0-pin {
1468 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1469 };
1470 };
1471
1472 pwm1 {
1473 pwm1_pin: pwm1-pin {
1474 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1475 };
1476 };
1477
1478 pwm2 {
1479 pwm2_pin: pwm2-pin {
1480 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1481 };
1482 };
1483
1484 pwm3 {
1485 pwm3_pin: pwm3-pin {
1486 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1487 };
1488 };
1489
1490 gmac {
1491 rgmii_pins: rgmii-pins {
1492 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1493 <3 31 3 &pcfg_pull_none>,
1494 <3 26 3 &pcfg_pull_none>,
1495 <3 27 3 &pcfg_pull_none>,
1496 <3 28 3 &pcfg_pull_none_12ma>,
1497 <3 29 3 &pcfg_pull_none_12ma>,
1498 <3 24 3 &pcfg_pull_none_12ma>,
1499 <3 25 3 &pcfg_pull_none_12ma>,
1500 <4 0 3 &pcfg_pull_none>,
1501 <4 5 3 &pcfg_pull_none>,
1502 <4 6 3 &pcfg_pull_none>,
1503 <4 9 3 &pcfg_pull_none_12ma>,
1504 <4 4 3 &pcfg_pull_none_12ma>,
1505 <4 1 3 &pcfg_pull_none>,
1506 <4 3 3 &pcfg_pull_none>;
1507 };
1508
1509 rmii_pins: rmii-pins {
1510 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1511 <3 31 3 &pcfg_pull_none>,
1512 <3 28 3 &pcfg_pull_none>,
1513 <3 29 3 &pcfg_pull_none>,
1514 <4 0 3 &pcfg_pull_none>,
1515 <4 5 3 &pcfg_pull_none>,
1516 <4 4 3 &pcfg_pull_none>,
1517 <4 1 3 &pcfg_pull_none>,
1518 <4 2 3 &pcfg_pull_none>,
1519 <4 3 3 &pcfg_pull_none>;
1520 };
1521 };
Simon Glass15019802016-01-21 19:45:21 -0700[diff] [blame]1522
1523 spdif {
1524 spdif_tx: spdif-tx {
1525 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1526 };
1527 };
Simon Glass087e9872015-08-30 16:55:20 -0600[diff] [blame]1528 };
1529
1530 power: power-controller {
1531 compatible = "rockchip,rk3288-power-controller";
1532 #power-domain-cells = <1>;
1533 rockchip,pmu = <&pmu>;
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1536
1537 pd_gpu {
1538 reg = <RK3288_PD_GPU>;
1539 clocks = <&cru ACLK_GPU>;
1540 };
1541
1542 pd_hevc {
1543 reg = <RK3288_PD_HEVC>;
1544 clocks = <&cru ACLK_HEVC>,
1545 <&cru SCLK_HEVC_CABAC>,
1546 <&cru SCLK_HEVC_CORE>,
1547 <&cru HCLK_HEVC>;
1548 };
1549
1550 pd_vio {
1551 reg = <RK3288_PD_VIO>;
1552 clocks = <&cru ACLK_IEP>,
1553 <&cru ACLK_ISP>,
1554 <&cru ACLK_RGA>,
1555 <&cru ACLK_VIP>,
1556 <&cru ACLK_VOP0>,
1557 <&cru ACLK_VOP1>,
1558 <&cru DCLK_VOP0>,
1559 <&cru DCLK_VOP1>,
1560 <&cru HCLK_IEP>,
1561 <&cru HCLK_ISP>,
1562 <&cru HCLK_RGA>,
1563 <&cru HCLK_VIP>,
1564 <&cru HCLK_VOP0>,
1565 <&cru HCLK_VOP1>,
1566 <&cru PCLK_EDP_CTRL>,
1567 <&cru PCLK_HDMI_CTRL>,
1568 <&cru PCLK_LVDS_PHY>,
1569 <&cru PCLK_MIPI_CSI>,
1570 <&cru PCLK_MIPI_DSI0>,
1571 <&cru PCLK_MIPI_DSI1>,
1572 <&cru SCLK_EDP_24M>,
1573 <&cru SCLK_EDP>,
1574 <&cru SCLK_HDMI_CEC>,
1575 <&cru SCLK_HDMI_HDCP>,
1576 <&cru SCLK_ISP_JPE>,
1577 <&cru SCLK_ISP>,
1578 <&cru SCLK_RGA>;
1579 };
1580
1581 pd_video {
1582 reg = <RK3288_PD_VIDEO>;
1583 clocks = <&cru ACLK_VCODEC>,
1584 <&cru HCLK_VCODEC>;
1585 };
1586 };
1587};