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Michal Simeke42840b2019-03-27 20:14:19 +01001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
Michal Simeka8c94362023-07-10 14:35:49 +02007 * Michal Simek <michal.simek@amd.com>
Michal Simeke42840b2019-03-27 20:14:19 +01008 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
Michal Simekfe8cb0c2021-05-10 14:55:34 +020014#include <dt-bindings/phy/phy.h>
Michal Simeke42840b2019-03-27 20:14:19 +010015
16/ {
17 model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
Michal Simek36aeb172019-06-28 13:16:10 +020018 compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
Michal Simeke42840b2019-03-27 20:14:19 +010019 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
Michal Simeke42840b2019-03-27 20:14:19 +010023 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci0;
26 mmc1 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +020027 nvmem0 = &eeprom;
Michal Simeke42840b2019-03-27 20:14:19 +010028 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &uart1;
31 serial2 = &dcc;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simeke42840b2019-03-27 20:14:19 +010039 };
40
41 memory@0 {
42 device_type = "memory";
Michal Simek2ceb5b52019-10-14 10:35:03 +020043 reg = <0x0 0x0 0x0 0x80000000>;
Michal Simeke42840b2019-03-27 20:14:19 +010044 };
Michal Simekfe8cb0c2021-05-10 14:55:34 +020045
Michal Simeke3157622024-01-08 10:24:45 +010046 si5332_1: si5332-1 { /* clk0_sgmii - u142 */
Michal Simekfe8cb0c2021-05-10 14:55:34 +020047 compatible = "fixed-clock";
48 #clock-cells = <0>;
Michal Simekd959bfc2021-10-15 14:48:20 +020049 clock-frequency = <125000000>;
Michal Simekfe8cb0c2021-05-10 14:55:34 +020050 };
51
Michal Simeke3157622024-01-08 10:24:45 +010052 si5332_2: si5332-2 { /* clk1_usb - u142 */
Michal Simekfe8cb0c2021-05-10 14:55:34 +020053 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <27000000>;
56 };
Michal Simeke42840b2019-03-27 20:14:19 +010057};
58
59&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
60 status = "okay";
61 non-removable;
62 disable-wp;
63 bus-width = <8>;
Michal Simek3b662642020-07-22 17:42:43 +020064 xlnx,mio-bank = <0>;
Michal Simeke42840b2019-03-27 20:14:19 +010065};
66
67&uart0 { /* uart0 MIO38-39 */
68 status = "okay";
Michal Simeke42840b2019-03-27 20:14:19 +010069};
70
71&uart1 { /* uart1 MIO40-41 */
72 status = "okay";
Michal Simeke42840b2019-03-27 20:14:19 +010073};
74
75&sdhci1 { /* sd1 MIO45-51 cd in place */
76 status = "okay";
77 no-1-8-v;
78 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +020079 xlnx,mio-bank = <1>;
Michal Simeke42840b2019-03-27 20:14:19 +010080};
81
Michal Simekfe8cb0c2021-05-10 14:55:34 +020082&psgtr {
83 status = "okay";
84 /* sgmii, usb3 */
85 clocks = <&si5332_1>, <&si5332_2>;
86 clock-names = "ref0", "ref1";
87};
88
Michal Simeke42840b2019-03-27 20:14:19 +010089&gem0 {
90 status = "okay";
91 phy-handle = <&phy0>;
92 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
Michal Simek0641df72023-09-22 12:35:36 +020093 mdio: mdio {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
97 phy0: ethernet-phy@0 {
98 reg = <0>;
99 };
Michal Simeke42840b2019-03-27 20:14:19 +0100100 };
101};
102
103&gpio {
104 status = "okay";
105 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
106 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
107 "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
108 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
109 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
110 "", "", "", "", "", /* 25 - 29 */
111 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
112 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
113 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
114 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
115 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
116 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
117 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
118 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
119 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
120 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
121 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
122 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
Michal Simeka8c5ce42024-09-13 11:28:46 +0200123 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 - 89 */
Michal Simeke42840b2019-03-27 20:14:19 +0100124 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
125 "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
126 "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
127 "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
128 "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
129 "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
130 "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
131 "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
132 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
133 "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
134 "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
135 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
136 "", "", "", "", "", /* 150 - 154 */
137 "", "", "", "", "", /* 155 - 159 */
138 "", "", "", "", "", /* 160 - 164 */
139 "", "", "", "", "", /* 165 - 169 */
Michal Simekfdf3fc62023-07-10 14:37:31 +0200140 "", "", "", ""; /* 170 - 173 */
Michal Simeke42840b2019-03-27 20:14:19 +0100141};
142
143&i2c0 { /* MIO 34-35 - can't stay here */
144 status = "okay";
145 clock-frequency = <400000>;
146 i2c-mux@74 { /* u33 */
147 compatible = "nxp,pca9548";
148 #address-cells = <1>;
149 #size-cells = <0>;
150 reg = <0x74>;
151 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
152 i2c@0 { /* PMBUS1 */
153 #address-cells = <1>;
154 #size-cells = <0>;
155 reg = <0>;
156 /* On connector J98 */
157 reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */
158 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
159 reg = <0x7>;
160 regulator-name = "reg_vcc_fmc";
161 regulator-min-microvolt = <1800000>;
162 regulator-max-microvolt = <2600000>;
163 /* enable-gpio = <&gpio0 23 0x4>; optional */
164 };
165 reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */
166 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
167 reg = <0x8>;
168 };
169 reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */
170 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
171 reg = <0x9>;
172 };
173 reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */
174 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
175 reg = <0xa>;
176 };
Nishant Mittal6815dd52019-07-24 14:58:52 +0530177 reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
Nishant Mittalce2c40d2019-07-24 14:58:52 +0530178 compatible = "ti,tps53681", "ti,tps53679";
Nishant Mittal6815dd52019-07-24 14:58:52 +0530179 reg = <0x60>;
Michal Simeke42840b2019-03-27 20:14:19 +0100180 /* vccint, vcc_io_soc */
181 };
182 };
183 i2c@1 { /* PMBUS1_INA226 */
184 #address-cells = <1>;
185 #size-cells = <0>;
186 reg = <1>;
Michal Simek892249d2019-10-14 10:27:42 +0200187 /* FIXME check alerts coming to SC */
Michal Simeke42840b2019-03-27 20:14:19 +0100188 vcc_fmc: ina226@42 { /* u81 */
189 compatible = "ti,ina226";
190 reg = <0x42>;
191 shunt-resistor = <5000>;
192 };
193 vcc_ram: ina226@43 { /* u82 */
194 compatible = "ti,ina226";
195 reg = <0x43>;
196 shunt-resistor = <5000>;
197 };
198 vcc_pslp: ina226@44 { /* u84 */
199 compatible = "ti,ina226";
200 reg = <0x44>;
201 shunt-resistor = <5000>;
202 };
203 vcc_psfp: ina226@45 { /* u87 */
204 compatible = "ti,ina226";
205 reg = <0x45>;
206 shunt-resistor = <5000>;
207 };
208 };
209 i2c@2 { /* PMBUS2 */
210 #address-cells = <1>;
211 #size-cells = <0>;
212 reg = <2>;
213 /* On connector J104 */
214 reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */
215 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
216 reg = <0xd>;
217 };
218 reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */
219 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
220 reg = <0xe>;
221 };
222 reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */
223 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
224 reg = <0xf>;
225 };
226 reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */
227 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
228 reg = <0x10>;
229 };
230 reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */
231 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
232 reg = <0x11>;
233 };
234 reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */
235 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
236 reg = <0x12>;
237 };
238 reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */
239 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
240 reg = <0x13>;
241 };
242 reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */
243 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
244 reg = <0x14>;
245 };
246 reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */
247 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
248 reg = <0x15>;
249 };
250 reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */
251 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
252 reg = <0x16>;
253 };
254 reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */
255 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
256 reg = <0x17>;
257 };
258 reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */
259 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
260 reg = <0x19>;
261 };
262 reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */
263 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
264 reg = <0x1a>;
265 };
266 reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */
267 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
268 reg = <0x1b>;
269 };
270 reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */
271 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
272 reg = <0x1c>;
273 };
274 reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */
275 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
276 reg = <0x1d>;
277 };
278 reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */
279 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
280 reg = <0x1e>;
281 };
282 reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */
283 compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
284 reg = <0x1f>;
285 };
286 };
287 i2c@3 { /* PMBUS2_INA226 */
288 #address-cells = <1>;
289 #size-cells = <0>;
290 reg = <3>;
291 /* FIXME check alerts coming to SC */
292 vccaux: ina226@40 { /* u89 */
293 compatible = "ti,ina226";
294 reg = <0x40>;
295 shunt-resistor = <5000>;
296 };
297 vccaux_fmc: ina226@41 { /* u91 */
298 compatible = "ti,ina226";
299 reg = <0x41>;
300 shunt-resistor = <5000>;
301 };
302 vcco_500: ina226@42 { /* u92 */
303 compatible = "ti,ina226";
304 reg = <0x42>;
305 shunt-resistor = <5000>;
306 };
307 vcco_501: ina226@43 { /* u94 */
308 compatible = "ti,ina226";
309 reg = <0x43>;
310 shunt-resistor = <5000>;
311 };
312 vcco_502: ina226@44 { /* u96 */
313 compatible = "ti,ina226";
314 reg = <0x44>;
315 shunt-resistor = <5000>;
316 };
317 vcco_503: ina226@45 { /* u98 */
318 compatible = "ti,ina226";
319 reg = <0x45>;
320 shunt-resistor = <5000>;
321 };
322 vcc_1v8: ina226@46 { /* u100 */
323 compatible = "ti,ina226";
324 reg = <0x46>;
325 shunt-resistor = <5000>;
326 };
327 vcc_3v3: ina226@47 { /* u103 */
328 compatible = "ti,ina226";
329 reg = <0x47>;
330 shunt-resistor = <5000>;
331 };
332 vcc_1v2_ddr4: ina226@48 { /* u105 */
333 compatible = "ti,ina226";
334 reg = <0x48>;
335 shunt-resistor = <1000>;
336 };
337 vcc1v1_lp4: ina226@49 { /* u107 */
338 compatible = "ti,ina226";
339 reg = <0x49>;
340 shunt-resistor = <5000>;
341 };
342 vadj_fmc: ina226@4a { /* u110 */
343 compatible = "ti,ina226";
344 reg = <0x4a>;
345 shunt-resistor = <5000>;
346 };
347 mgtyavcc: ina226@4b { /* u112 */
348 compatible = "ti,ina226";
349 reg = <0x4b>;
350 shunt-resistor = <1000>;
351 };
352 mgtyavtt: ina226@4c { /* u113 */
353 compatible = "ti,ina226";
354 reg = <0x4c>;
355 shunt-resistor = <1000>;
356 };
357 mgtyvccaux: ina226@4d { /* u116 */
358 compatible = "ti,ina226";
359 reg = <0x4d>;
360 shunt-resistor = <5000>;
361 };
362 vcc_bat: ina226@4e { /* u12 */
363 compatible = "ti,ina226";
364 reg = <0x4e>;
365 shunt-resistor = <10000000>; /* 10 ohm */
366 };
367 };
368 i2c@4 { /* LP_I2C_SM */
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <4>;
372 /* connected to J212G */
373 /* zynqmp sm alert or samtec J212H */
374 };
375 /* 5-7 unused */
376 };
377};
378
379&i2c1 { /* i2c1 MIO 36-37 */
380 status = "okay";
381 clock-frequency = <400000>;
382
383 /* Must be enabled via J242 */
384 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
385 compatible = "atmel,24c02";
386 reg = <0x51>;
387 };
388
389 i2c-mux@74 { /* u35 */
390 compatible = "nxp,pca9548";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 reg = <0x74>;
394 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
395 dc_i2c: i2c@0 { /* DC_I2C */
396 #address-cells = <1>;
397 #size-cells = <0>;
398 reg = <0>;
399 /* Use for storing information about SC board */
400 eeprom: eeprom@54 { /* u34 - m24128 16kB */
401 compatible = "st,24c128", "atmel,24c128";
402 reg = <0x54>;
403 };
404 si570_ref_clk: clock-generator@5d { /* u32 */
405 #clock-cells = <0>;
406 compatible = "silabs,si570";
407 reg = <0x5d>; /* 570JAC000900DG */
408 temperature-stability = <50>;
Michal Simek9579da32019-06-25 08:55:52 +0200409 factory-fout = <33333333>;
Michal Simeke42840b2019-03-27 20:14:19 +0100410 clock-frequency = <33333333>;
Michal Simek9579da32019-06-25 08:55:52 +0200411 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100412 silabs,skip-recall;
Michal Simeke42840b2019-03-27 20:14:19 +0100413 };
414 /* Connection via Samtec J212D */
415 /* Use for storing information about X-PRC card */
416 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
417 compatible = "atmel,24c02";
418 reg = <0x52>;
419 };
420
421 /* Use for setting up certain features on X-PRC card */
422 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
423 compatible = "nxp,pca9534";
424 reg = <0x22>;
425 gpio-controller; /* IRQ not connected */
426 #gpio-cells = <2>;
427 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
428 "", "", "", "";
Michal Simek5368d402024-09-13 11:28:43 +0200429 gtr-sel0-hog {
Michal Simeke42840b2019-03-27 20:14:19 +0100430 gpio-hog;
431 gpios = <0 0>;
432 input; /* FIXME add meaning */
433 line-name = "sw4_1";
434 };
Michal Simek5368d402024-09-13 11:28:43 +0200435 gtr-sel1-hog {
Michal Simeke42840b2019-03-27 20:14:19 +0100436 gpio-hog;
437 gpios = <1 0>;
438 input; /* FIXME add meaning */
439 line-name = "sw4_2";
440 };
Michal Simek5368d402024-09-13 11:28:43 +0200441 gtr-sel2-hog {
Michal Simeke42840b2019-03-27 20:14:19 +0100442 gpio-hog;
443 gpios = <2 0>;
444 input; /* FIXME add meaning */
445 line-name = "sw4_3";
446 };
Michal Simek5368d402024-09-13 11:28:43 +0200447 gtr-sel3-hog {
Michal Simeke42840b2019-03-27 20:14:19 +0100448 gpio-hog;
449 gpios = <3 0>;
450 input; /* FIXME add meaning */
451 line-name = "sw4_4";
452 };
453 };
454 };
455 i2c@1 { /* FMCP1_IIC */
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <1>;
459 /* FIXME connection to Samtec J51C */
460 /* expected eeprom 0x50 SE cards */
461 };
462 i2c@2 { /* FMCP2_IIC */
463 #address-cells = <1>;
464 #size-cells = <0>;
465 reg = <2>;
466 /* FIXME connection to Samtec J53C */
467 /* expected eeprom 0x50 SE cards */
468 };
469 i2c@3 { /* DDR4_DIMM1 */
470 #address-cells = <1>;
471 #size-cells = <0>;
472 reg = <3>;
473 si570_ddr_dimm1: clock-generator@60 { /* u2 */
474 #clock-cells = <0>;
475 compatible = "silabs,si570";
476 reg = <0x60>; /* 570BAB000299DG */
477 temperature-stability = <50>;
Michal Simek9579da32019-06-25 08:55:52 +0200478 factory-fout = <200000000>;
479 clock-frequency = <200000000>;
480 clock-output-names = "si570_ddrdimm1_clk";
Michal Simeke42840b2019-03-27 20:14:19 +0100481 };
482 /* 0x50 SPD? */
483 };
484 i2c@4 { /* DDR4_DIMM2 */
485 #address-cells = <1>;
486 #size-cells = <0>;
487 reg = <4>;
488 si570_ddr_dimm2: clock-generator@60 { /* u3 */
489 #clock-cells = <0>;
490 compatible = "silabs,si570";
491 reg = <0x60>; /* 570BAB000299DG */
492 temperature-stability = <50>;
Michal Simek9579da32019-06-25 08:55:52 +0200493 factory-fout = <200000000>;
494 clock-frequency = <200000000>;
495 clock-output-names = "si570_ddrdimm2_clk";
Michal Simeke42840b2019-03-27 20:14:19 +0100496 };
497 /* 0x50 SPD? */
498 };
499 i2c@5 { /* LPDDR4_SI570_CLK */
500 #address-cells = <1>;
501 #size-cells = <0>;
502 reg = <5>;
503 si570_lpddr4: clock-generator@60 { /* u4 */
504 #clock-cells = <0>;
505 compatible = "silabs,si570";
506 reg = <0x60>; /* 570BAB000299DG */
507 temperature-stability = <50>;
Michal Simek9579da32019-06-25 08:55:52 +0200508 factory-fout = <200000000>;
509 clock-frequency = <200000000>;
510 clock-output-names = "si570_lpddr4_clk";
Michal Simeke42840b2019-03-27 20:14:19 +0100511 };
512 };
513 i2c@6 { /* HSDP_SI570 */
514 #address-cells = <1>;
515 #size-cells = <0>;
516 reg = <6>;
Michal Simek4ac631d2022-03-07 08:53:38 +0100517 si570_hsdp: clock-generator@60 { /* u5 */
Michal Simeke42840b2019-03-27 20:14:19 +0100518 #clock-cells = <0>;
519 compatible = "silabs,si570";
Michal Simek4ac631d2022-03-07 08:53:38 +0100520 reg = <0x60>; /* 570JAC000900DG */
Michal Simeke42840b2019-03-27 20:14:19 +0100521 temperature-stability = <50>;
Michal Simek9579da32019-06-25 08:55:52 +0200522 factory-fout = <156250000>;
523 clock-frequency = <156250000>;
524 clock-output-names = "si570_hsdp_clk";
Michal Simeke42840b2019-03-27 20:14:19 +0100525 };
526 };
527 i2c@7 { /* PCIE_CLK */
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <7>;
531 /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
532 /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */
533 /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
Michal Simek11fae8c2023-11-08 08:36:40 +0100534 /* u39 8T49N240 - pcie clocking 3 */
Michal Simeke42840b2019-03-27 20:14:19 +0100535 };
536 };
537};
538
539&usb0 {
540 status = "okay";
Manish Naranif3c63382021-07-14 06:17:19 -0600541 phy-names = "usb3-phy";
542 phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
Michal Simeke42840b2019-03-27 20:14:19 +0100543};
544
545&dwc3_0 {
546 status = "okay";
547 dr_mode = "peripheral";
548 snps,dis_u2_susphy_quirk;
549 snps,dis_u3_susphy_quirk;
550 maximum-speed = "super-speed";
Michal Simeke42840b2019-03-27 20:14:19 +0100551};
552
553&usb1 {
554 status = "okay";
Michal Simeke42840b2019-03-27 20:14:19 +0100555};
556
557&dwc3_1 {
558 /delete-property/ phy-names ;
559 /delete-property/ phys ;
560 dr_mode = "host";
561 maximum-speed = "high-speed";
562 snps,dis_u2_susphy_quirk ;
563 snps,dis_u3_susphy_quirk ;
564 status = "okay";
565};
566
567&xilinx_ams {
568 status = "okay";
569};
570
571&ams_ps {
572 status = "okay";
573};
574
575&ams_pl {
576 status = "okay";
577};