Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 2 | /* |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 3 | * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2003 Motorola,Inc. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards |
| 8 | * |
| 9 | * The processor starts at 0xfffffffc and the code is first executed in the |
| 10 | * last 4K page(0xfffff000-0xffffffff) in flash/rom. |
| 11 | * |
| 12 | */ |
| 13 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 14 | #include <asm-offsets.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 15 | #include <config.h> |
| 16 | #include <mpc85xx.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 17 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 18 | #include <ppc_asm.tmpl> |
| 19 | #include <ppc_defs.h> |
| 20 | |
| 21 | #include <asm/cache.h> |
| 22 | #include <asm/mmu.h> |
| 23 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 24 | #undef MSR_KERNEL |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 25 | #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 26 | |
Prabhakar Kushwaha | 3fc2e89 | 2014-04-08 19:12:05 +0530 | [diff] [blame] | 27 | #define LAW_EN 0x80000000 |
| 28 | |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 29 | #if defined(CONFIG_NAND_SPL) || \ |
| 30 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) |
| 31 | #define MINIMAL_SPL |
| 32 | #endif |
| 33 | |
Liu Gang | ee9d753 | 2013-06-28 17:58:37 +0800 | [diff] [blame] | 34 | #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \ |
Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 35 | !defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 36 | #define NOR_BOOT |
| 37 | #endif |
| 38 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 39 | /* |
| 40 | * Set up GOT: Global Offset Table |
| 41 | * |
Joakim Tjernlund | 3fbaa4d | 2010-01-19 14:41:56 +0100 | [diff] [blame] | 42 | * Use r12 to access the GOT |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 43 | */ |
| 44 | START_GOT |
| 45 | GOT_ENTRY(_GOT2_TABLE_) |
| 46 | GOT_ENTRY(_FIXUP_TABLE_) |
| 47 | |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 48 | #ifndef MINIMAL_SPL |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 49 | GOT_ENTRY(_start_of_vectors) |
| 50 | GOT_ENTRY(_end_of_vectors) |
| 51 | GOT_ENTRY(transfer_to_handler) |
Mingkai Hu | 0255cd7 | 2009-09-11 14:19:10 +0800 | [diff] [blame] | 52 | #endif |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 53 | |
| 54 | GOT_ENTRY(__init_end) |
Simon Glass | ed70c8f | 2013-03-14 06:54:53 +0000 | [diff] [blame] | 55 | GOT_ENTRY(__bss_end) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 56 | GOT_ENTRY(__bss_start) |
| 57 | END_GOT |
| 58 | |
| 59 | /* |
| 60 | * e500 Startup -- after reset only the last 4KB of the effective |
| 61 | * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg |
| 62 | * section is located at THIS LAST page and basically does three |
| 63 | * things: clear some registers, set up exception tables and |
| 64 | * add more TLB entries for 'larger spaces'(e.g. the boot rom) to |
| 65 | * continue the boot procedure. |
| 66 | |
| 67 | * Once the boot rom is mapped by TLB entries we can proceed |
| 68 | * with normal startup. |
| 69 | * |
| 70 | */ |
| 71 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 72 | .section .bootpg,"ax" |
| 73 | .globl _start_e500 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 74 | |
| 75 | _start_e500: |
Prabhakar Kushwaha | 8f3e892 | 2012-04-29 23:56:30 +0000 | [diff] [blame] | 76 | /* Enable debug exception */ |
| 77 | li r1,MSR_DE |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 78 | mtmsr r1 |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 79 | |
Alexander Graf | c346848 | 2014-04-11 17:09:45 +0200 | [diff] [blame] | 80 | /* |
| 81 | * If we got an ePAPR device tree pointer passed in as r3, we need that |
| 82 | * later in cpu_init_early_f(). Save it to a safe register before we |
| 83 | * clobber it so that we can fetch it from there later. |
| 84 | */ |
| 85 | mr r24, r3 |
| 86 | |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 87 | #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 |
| 88 | mfspr r3,SPRN_SVR |
| 89 | rlwinm r3,r3,0,0xff |
| 90 | li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV |
| 91 | cmpw r3,r4 |
| 92 | beq 1f |
| 93 | |
| 94 | #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 |
| 95 | li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 |
| 96 | cmpw r3,r4 |
| 97 | beq 1f |
| 98 | #endif |
| 99 | |
| 100 | /* Not a supported revision affected by erratum */ |
| 101 | li r27,0 |
| 102 | b 2f |
| 103 | |
| 104 | 1: li r27,1 /* Remember for later that we have the erratum */ |
| 105 | /* Erratum says set bits 55:60 to 001001 */ |
| 106 | msync |
| 107 | isync |
Andy Fleming | eab55c0 | 2013-03-25 07:33:10 +0000 | [diff] [blame] | 108 | mfspr r3,SPRN_HDBCR0 |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 109 | li r4,0x48 |
| 110 | rlwimi r3,r4,0,0x1f8 |
Andy Fleming | eab55c0 | 2013-03-25 07:33:10 +0000 | [diff] [blame] | 111 | mtspr SPRN_HDBCR0,r3 |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 112 | isync |
| 113 | 2: |
| 114 | #endif |
York Sun | 0cc5907 | 2013-08-20 15:09:43 -0700 | [diff] [blame] | 115 | #ifdef CONFIG_SYS_FSL_ERRATUM_A005125 |
| 116 | msync |
| 117 | isync |
| 118 | mfspr r3, SPRN_HDBCR0 |
| 119 | oris r3, r3, 0x0080 |
| 120 | mtspr SPRN_HDBCR0, r3 |
| 121 | #endif |
| 122 | |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 123 | |
Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 124 | #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \ |
Aneesh Bansal | 8bcbc27 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 125 | !defined(CONFIG_E6500) |
Ruchika Gupta | 8ca8d82 | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 126 | /* ISBC uses L2 as stack. |
| 127 | * Disable L2 cache here so that u-boot can enable it later |
| 128 | * as part of it's normal flow |
| 129 | */ |
| 130 | |
| 131 | /* Check if L2 is enabled */ |
| 132 | mfspr r3, SPRN_L2CSR0 |
| 133 | lis r2, L2CSR0_L2E@h |
| 134 | ori r2, r2, L2CSR0_L2E@l |
| 135 | and. r4, r3, r2 |
| 136 | beq l2_disabled |
| 137 | |
| 138 | mfspr r3, SPRN_L2CSR0 |
| 139 | /* Flush L2 cache */ |
| 140 | lis r2,(L2CSR0_L2FL)@h |
| 141 | ori r2, r2, (L2CSR0_L2FL)@l |
| 142 | or r3, r2, r3 |
| 143 | sync |
| 144 | isync |
| 145 | mtspr SPRN_L2CSR0,r3 |
| 146 | isync |
| 147 | 1: |
| 148 | mfspr r3, SPRN_L2CSR0 |
| 149 | and. r1, r3, r2 |
| 150 | bne 1b |
| 151 | |
| 152 | mfspr r3, SPRN_L2CSR0 |
| 153 | lis r2, L2CSR0_L2E@h |
| 154 | ori r2, r2, L2CSR0_L2E@l |
| 155 | andc r4, r3, r2 |
| 156 | sync |
| 157 | isync |
| 158 | mtspr SPRN_L2CSR0,r4 |
| 159 | isync |
| 160 | |
| 161 | l2_disabled: |
| 162 | #endif |
| 163 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 164 | /* clear registers/arrays not reset by hardware */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 165 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 166 | /* L1 */ |
| 167 | li r0,2 |
| 168 | mtspr L1CSR0,r0 /* invalidate d-cache */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 169 | mtspr L1CSR1,r0 /* invalidate i-cache */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 170 | |
| 171 | mfspr r1,DBSR |
| 172 | mtspr DBSR,r1 /* Clear all valid bits */ |
| 173 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 174 | |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 175 | .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch |
| 176 | lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h |
| 177 | ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l |
| 178 | mtspr MAS0, \scratch |
| 179 | lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h |
| 180 | ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l |
| 181 | mtspr MAS1, \scratch |
| 182 | lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h |
| 183 | ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l |
| 184 | mtspr MAS2, \scratch |
| 185 | lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h |
| 186 | ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l |
| 187 | mtspr MAS3, \scratch |
| 188 | lis \scratch, \phy_high@h |
| 189 | ori \scratch, \scratch, \phy_high@l |
| 190 | mtspr MAS7, \scratch |
| 191 | isync |
| 192 | msync |
| 193 | tlbwe |
| 194 | isync |
| 195 | .endm |
| 196 | |
| 197 | .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch |
| 198 | lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h |
| 199 | ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l |
| 200 | mtspr MAS0, \scratch |
| 201 | lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h |
| 202 | ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l |
| 203 | mtspr MAS1, \scratch |
| 204 | lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h |
| 205 | ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l |
| 206 | mtspr MAS2, \scratch |
| 207 | lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h |
| 208 | ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l |
| 209 | mtspr MAS3, \scratch |
| 210 | lis \scratch, \phy_high@h |
| 211 | ori \scratch, \scratch, \phy_high@l |
| 212 | mtspr MAS7, \scratch |
| 213 | isync |
| 214 | msync |
| 215 | tlbwe |
| 216 | isync |
| 217 | .endm |
| 218 | |
| 219 | .macro delete_tlb1_entry esel scratch |
| 220 | lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h |
| 221 | ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l |
| 222 | mtspr MAS0, \scratch |
| 223 | li \scratch, 0 |
| 224 | mtspr MAS1, \scratch |
| 225 | isync |
| 226 | msync |
| 227 | tlbwe |
| 228 | isync |
| 229 | .endm |
| 230 | |
| 231 | .macro delete_tlb0_entry esel epn wimg scratch |
| 232 | lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h |
| 233 | ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l |
| 234 | mtspr MAS0, \scratch |
| 235 | li \scratch, 0 |
| 236 | mtspr MAS1, \scratch |
| 237 | lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h |
| 238 | ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l |
| 239 | mtspr MAS2, \scratch |
| 240 | isync |
| 241 | msync |
| 242 | tlbwe |
| 243 | isync |
| 244 | .endm |
| 245 | |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 246 | /* Interrupt vectors do not fit in minimal SPL. */ |
| 247 | #if !defined(MINIMAL_SPL) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 248 | /* Setup interrupt vectors */ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 249 | lis r1,CONFIG_VAL(SYS_MONITOR_BASE)@h |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 250 | mtspr IVPR,r1 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 251 | |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 252 | li r4,CriticalInput@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 253 | mtspr IVOR0,r4 /* 0: Critical input */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 254 | li r4,MachineCheck@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 255 | mtspr IVOR1,r4 /* 1: Machine check */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 256 | li r4,DataStorage@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 257 | mtspr IVOR2,r4 /* 2: Data storage */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 258 | li r4,InstStorage@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 259 | mtspr IVOR3,r4 /* 3: Instruction storage */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 260 | li r4,ExtInterrupt@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 261 | mtspr IVOR4,r4 /* 4: External interrupt */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 262 | li r4,Alignment@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 263 | mtspr IVOR5,r4 /* 5: Alignment */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 264 | li r4,ProgramCheck@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 265 | mtspr IVOR6,r4 /* 6: Program check */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 266 | li r4,FPUnavailable@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 267 | mtspr IVOR7,r4 /* 7: floating point unavailable */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 268 | li r4,SystemCall@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 269 | mtspr IVOR8,r4 /* 8: System call */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 270 | /* 9: Auxiliary processor unavailable(unsupported) */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 271 | li r4,Decrementer@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 272 | mtspr IVOR10,r4 /* 10: Decrementer */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 273 | li r4,IntervalTimer@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 274 | mtspr IVOR11,r4 /* 11: Interval timer */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 275 | li r4,WatchdogTimer@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 276 | mtspr IVOR12,r4 /* 12: Watchdog timer */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 277 | li r4,DataTLBError@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 278 | mtspr IVOR13,r4 /* 13: Data TLB error */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 279 | li r4,InstructionTLBError@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 280 | mtspr IVOR14,r4 /* 14: Instruction TLB error */ |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 281 | li r4,DebugBreakpoint@l |
Prabhakar Kushwaha | 2153b57 | 2012-02-14 22:49:29 +0000 | [diff] [blame] | 282 | mtspr IVOR15,r4 /* 15: Debug */ |
Prabhakar Kushwaha | 4a66422 | 2012-02-14 22:50:02 +0000 | [diff] [blame] | 283 | #endif |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 284 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 285 | /* Clear and set up some registers. */ |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 286 | li r0,0x0000 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 287 | lis r1,0xffff |
| 288 | mtspr DEC,r0 /* prevent dec exceptions */ |
| 289 | mttbl r0 /* prevent fit & wdt exceptions */ |
| 290 | mttbu r0 |
| 291 | mtspr TSR,r1 /* clear all timer exception status */ |
| 292 | mtspr TCR,r0 /* disable all */ |
| 293 | mtspr ESR,r0 /* clear exception syndrome register */ |
| 294 | mtspr MCSR,r0 /* machine check syndrome register */ |
| 295 | mtxer r0 /* clear integer exception register */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 296 | |
Scott Wood | 31e6010 | 2009-08-20 17:45:05 -0500 | [diff] [blame] | 297 | #ifdef CONFIG_SYS_BOOK3E_HV |
| 298 | mtspr MAS8,r0 /* make sure MAS8 is clear */ |
| 299 | #endif |
| 300 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 301 | /* Enable Time Base and Select Time Base Clock */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 302 | lis r0,HID0_EMCP@h /* Enable machine check */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 303 | #if defined(CONFIG_ENABLE_36BIT_PHYS) |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 304 | ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 305 | #endif |
Kumar Gala | e56f2c5 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 306 | #ifndef CONFIG_E500MC |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 307 | ori r0,r0,HID0_TBEN@l /* Enable Timebase */ |
Kumar Gala | e56f2c5 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 308 | #endif |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 309 | mtspr HID0,r0 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 310 | |
York Sun | 51e91e8 | 2016-11-18 12:29:51 -0800 | [diff] [blame] | 311 | #if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500) |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 312 | li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ |
Sandeep Gopalpet | 8709aed | 2010-03-12 10:45:02 +0530 | [diff] [blame] | 313 | mfspr r3,PVR |
| 314 | andi. r3,r3, 0xff |
| 315 | cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ |
| 316 | blt 1f |
| 317 | /* Set MBDD bit also */ |
| 318 | ori r0, r0, HID1_MBDD@l |
| 319 | 1: |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 320 | mtspr HID1,r0 |
Kumar Gala | 9f4a689 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 321 | #endif |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 322 | |
Kumar Gala | 945e59a | 2011-11-22 06:51:15 -0600 | [diff] [blame] | 323 | #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
Andy Fleming | eab55c0 | 2013-03-25 07:33:10 +0000 | [diff] [blame] | 324 | mfspr r3,SPRN_HDBCR1 |
Kumar Gala | 945e59a | 2011-11-22 06:51:15 -0600 | [diff] [blame] | 325 | oris r3,r3,0x0100 |
Andy Fleming | eab55c0 | 2013-03-25 07:33:10 +0000 | [diff] [blame] | 326 | mtspr SPRN_HDBCR1,r3 |
Kumar Gala | 945e59a | 2011-11-22 06:51:15 -0600 | [diff] [blame] | 327 | #endif |
| 328 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 329 | /* Enable Branch Prediction */ |
| 330 | #if defined(CONFIG_BTB) |
Kumar Gala | 5530cb8 | 2010-03-29 13:50:31 -0500 | [diff] [blame] | 331 | lis r0,BUCSR_ENABLE@h |
| 332 | ori r0,r0,BUCSR_ENABLE@l |
| 333 | mtspr SPRN_BUCSR,r0 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 334 | #endif |
| 335 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 336 | #if defined(CONFIG_SYS_INIT_DBCR) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 337 | lis r1,0xffff |
| 338 | ori r1,r1,0xffff |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 339 | mtspr DBSR,r1 /* Clear all status bits */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 340 | lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ |
| 341 | ori r0,r0,CONFIG_SYS_INIT_DBCR@l |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 342 | mtspr DBCR0,r0 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 343 | #endif |
| 344 | |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 345 | /* |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 346 | * Search for the TLB that covers the code we're executing, and shrink it |
| 347 | * so that it covers only this 4K page. That will ensure that any other |
| 348 | * TLB we create won't interfere with it. We assume that the TLB exists, |
Scott Wood | 2bfa0f4 | 2012-08-20 13:10:08 +0000 | [diff] [blame] | 349 | * which is why we don't check the Valid bit of MAS1. We also assume |
| 350 | * it is in TLB1. |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 351 | * |
| 352 | * This is necessary, for example, when booting from the on-chip ROM, |
| 353 | * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 354 | */ |
| 355 | bl nexti /* Find our address */ |
| 356 | nexti: mflr r1 /* R1 = our PC */ |
| 357 | li r2, 0 |
| 358 | mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ |
| 359 | isync |
| 360 | msync |
| 361 | tlbsx 0, r1 /* This must succeed */ |
| 362 | |
Scott Wood | 2bfa0f4 | 2012-08-20 13:10:08 +0000 | [diff] [blame] | 363 | mfspr r14, MAS0 /* Save ESEL for later */ |
| 364 | rlwinm r14, r14, 16, 0xfff |
| 365 | |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 366 | /* Set the size of the TLB to 4KB */ |
| 367 | mfspr r3, MAS1 |
Scott Wood | 33a619c | 2013-01-18 15:45:58 +0000 | [diff] [blame] | 368 | li r2, 0xF80 |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 369 | andc r3, r3, r2 /* Clear the TSIZE bits */ |
| 370 | ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l |
Scott Wood | 2bfa0f4 | 2012-08-20 13:10:08 +0000 | [diff] [blame] | 371 | oris r3, r3, MAS1_IPROT@h |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 372 | mtspr MAS1, r3 |
| 373 | |
| 374 | /* |
| 375 | * Set the base address of the TLB to our PC. We assume that |
| 376 | * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. |
| 377 | */ |
| 378 | lis r3, MAS2_EPN@h |
| 379 | ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ |
| 380 | |
| 381 | and r1, r1, r3 /* Our PC, rounded down to the nearest page */ |
| 382 | |
| 383 | mfspr r2, MAS2 |
| 384 | andc r2, r2, r3 |
| 385 | or r2, r2, r1 |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 386 | #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 |
| 387 | cmpwi r27,0 |
| 388 | beq 1f |
| 389 | andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */ |
| 390 | rlwinm r2, r2, 0, ~MAS2_I |
| 391 | ori r2, r2, MAS2_G |
| 392 | 1: |
| 393 | #endif |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 394 | mtspr MAS2, r2 /* Set the EPN to our PC base address */ |
| 395 | |
| 396 | mfspr r2, MAS3 |
| 397 | andc r2, r2, r3 |
| 398 | or r2, r2, r1 |
| 399 | mtspr MAS3, r2 /* Set the RPN to our PC base address */ |
| 400 | |
| 401 | isync |
| 402 | msync |
| 403 | tlbwe |
Scott Wood | 2bfa0f4 | 2012-08-20 13:10:08 +0000 | [diff] [blame] | 404 | |
| 405 | /* |
| 406 | * Clear out any other TLB entries that may exist, to avoid conflicts. |
| 407 | * Our TLB entry is in r14. |
| 408 | */ |
| 409 | li r0, TLBIVAX_ALL | TLBIVAX_TLB0 |
| 410 | tlbivax 0, r0 |
| 411 | tlbsync |
| 412 | |
| 413 | mfspr r4, SPRN_TLB1CFG |
| 414 | rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK |
| 415 | |
| 416 | li r3, 0 |
| 417 | mtspr MAS1, r3 |
| 418 | 1: cmpw r3, r14 |
Scott Wood | 2bfa0f4 | 2012-08-20 13:10:08 +0000 | [diff] [blame] | 419 | rlwinm r5, r3, 16, MAS0_ESEL_MSK |
| 420 | addi r3, r3, 1 |
| 421 | beq 2f /* skip the entry we're executing from */ |
| 422 | |
| 423 | oris r5, r5, MAS0_TLBSEL(1)@h |
| 424 | mtspr MAS0, r5 |
| 425 | |
| 426 | isync |
| 427 | tlbwe |
| 428 | isync |
| 429 | msync |
| 430 | |
| 431 | 2: cmpw r3, r4 |
| 432 | blt 1b |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 433 | |
Aneesh Bansal | bf955b2 | 2014-03-12 00:07:27 +0530 | [diff] [blame] | 434 | #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ |
Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 435 | !defined(CONFIG_NXP_ESBC) |
Scott Wood | d6a8288 | 2012-10-25 19:27:41 -0500 | [diff] [blame] | 436 | /* |
| 437 | * TLB entry for debuggging in AS1 |
| 438 | * Create temporary TLB entry in AS0 to handle debug exception |
| 439 | * As on debug exception MSR is cleared i.e. Address space is changed |
| 440 | * to 0. A TLB entry (in AS0) is required to handle debug exception generated |
| 441 | * in AS1. |
| 442 | */ |
| 443 | |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 444 | #ifdef NOR_BOOT |
Scott Wood | d6a8288 | 2012-10-25 19:27:41 -0500 | [diff] [blame] | 445 | /* |
| 446 | * TLB entry is created for IVPR + IVOR15 to map on valid OP code address |
| 447 | * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. |
| 448 | * and this window is outside of 4K boot window. |
| 449 | */ |
| 450 | create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ |
| 451 | 0, BOOKE_PAGESZ_4M, \ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 452 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xffc00000, MAS2_I|MAS2_G, \ |
Scott Wood | d6a8288 | 2012-10-25 19:27:41 -0500 | [diff] [blame] | 453 | 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ |
| 454 | 0, r6 |
| 455 | |
Scott Wood | d6a8288 | 2012-10-25 19:27:41 -0500 | [diff] [blame] | 456 | #else |
| 457 | /* |
| 458 | * TLB entry is created for IVPR + IVOR15 to map on valid OP code address |
| 459 | * because "nexti" will resize TLB to 4K |
| 460 | */ |
| 461 | create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ |
| 462 | 0, BOOKE_PAGESZ_256K, \ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 463 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xfffc0000, MAS2_I, \ |
| 464 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ |
Scott Wood | d6a8288 | 2012-10-25 19:27:41 -0500 | [diff] [blame] | 465 | 0, r6 |
| 466 | #endif |
| 467 | #endif |
| 468 | |
Timur Tabi | c9a1b77 | 2011-10-31 13:30:45 -0500 | [diff] [blame] | 469 | /* |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 470 | * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default |
| 471 | * location is not where we want it. This typically happens on a 36-bit |
| 472 | * system, where we want to move CCSR to near the top of 36-bit address space. |
| 473 | * |
| 474 | * To move CCSR, we create two temporary TLBs, one for the old location, and |
| 475 | * another for the new location. On CoreNet systems, we also need to create |
| 476 | * a special, temporary LAW. |
| 477 | * |
| 478 | * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for |
| 479 | * long-term TLBs, so we use TLB0 here. |
| 480 | */ |
| 481 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) |
| 482 | |
| 483 | #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) |
| 484 | #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." |
| 485 | #endif |
| 486 | |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 487 | create_ccsr_new_tlb: |
| 488 | /* |
| 489 | * Create a TLB for the new location of CCSR. Register R8 is reserved |
| 490 | * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). |
| 491 | */ |
Scott Wood | 2bfa0f4 | 2012-08-20 13:10:08 +0000 | [diff] [blame] | 492 | lis r8, CONFIG_SYS_CCSRBAR@h |
| 493 | ori r8, r8, CONFIG_SYS_CCSRBAR@l |
| 494 | lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h |
| 495 | ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 496 | create_tlb0_entry 0, \ |
| 497 | 0, BOOKE_PAGESZ_4K, \ |
| 498 | CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ |
| 499 | CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ |
| 500 | CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 501 | /* |
Timur Tabi | 40402f0 | 2011-10-31 13:30:42 -0500 | [diff] [blame] | 502 | * Create a TLB for the current location of CCSR. Register R9 is reserved |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 503 | * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). |
| 504 | */ |
| 505 | create_ccsr_old_tlb: |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 506 | create_tlb0_entry 1, \ |
| 507 | 0, BOOKE_PAGESZ_4K, \ |
| 508 | CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ |
| 509 | CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ |
| 510 | 0, r3 /* The default CCSR address is always a 32-bit number */ |
| 511 | |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 512 | |
Timur Tabi | c19b068 | 2011-10-31 13:30:44 -0500 | [diff] [blame] | 513 | /* |
| 514 | * We have a TLB for what we think is the current (old) CCSR. Let's |
| 515 | * verify that, otherwise we won't be able to move it. |
| 516 | * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only |
| 517 | * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. |
| 518 | */ |
| 519 | verify_old_ccsr: |
| 520 | lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h |
| 521 | ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l |
| 522 | #ifdef CONFIG_FSL_CORENET |
| 523 | lwz r1, 4(r9) /* CCSRBARL */ |
| 524 | #else |
| 525 | lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ |
| 526 | slwi r1, r1, 12 |
| 527 | #endif |
| 528 | |
| 529 | cmpl 0, r0, r1 |
| 530 | |
| 531 | /* |
| 532 | * If the value we read from CCSRBARL is not what we expect, then |
| 533 | * enter an infinite loop. This will at least allow a debugger to |
| 534 | * halt execution and examine TLBs, etc. There's no point in going |
| 535 | * on. |
| 536 | */ |
| 537 | infinite_debug_loop: |
| 538 | bne infinite_debug_loop |
| 539 | |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 540 | #ifdef CONFIG_FSL_CORENET |
| 541 | |
| 542 | #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 543 | #define LAW_SIZE_4K 0xb |
| 544 | #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) |
| 545 | #define CCSRAR_C 0x80000000 /* Commit */ |
| 546 | |
| 547 | create_temp_law: |
| 548 | /* |
| 549 | * On CoreNet systems, we create the temporary LAW using a special LAW |
| 550 | * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. |
| 551 | */ |
| 552 | lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h |
| 553 | ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l |
| 554 | lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h |
| 555 | ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l |
| 556 | lis r2, CCSRBAR_LAWAR@h |
| 557 | ori r2, r2, CCSRBAR_LAWAR@l |
| 558 | |
| 559 | stw r0, 0xc00(r9) /* LAWBARH0 */ |
| 560 | stw r1, 0xc04(r9) /* LAWBARL0 */ |
| 561 | sync |
| 562 | stw r2, 0xc08(r9) /* LAWAR0 */ |
| 563 | |
| 564 | /* |
| 565 | * Read back from LAWAR to ensure the update is complete. e500mc |
| 566 | * cores also require an isync. |
| 567 | */ |
| 568 | lwz r0, 0xc08(r9) /* LAWAR0 */ |
| 569 | isync |
| 570 | |
| 571 | /* |
| 572 | * Read the current CCSRBARH and CCSRBARL using load word instructions. |
| 573 | * Follow this with an isync instruction. This forces any outstanding |
| 574 | * accesses to configuration space to completion. |
| 575 | */ |
| 576 | read_old_ccsrbar: |
| 577 | lwz r0, 0(r9) /* CCSRBARH */ |
Timur Tabi | 40402f0 | 2011-10-31 13:30:42 -0500 | [diff] [blame] | 578 | lwz r0, 4(r9) /* CCSRBARL */ |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 579 | isync |
| 580 | |
| 581 | /* |
| 582 | * Write the new values for CCSRBARH and CCSRBARL to their old |
| 583 | * locations. The CCSRBARH has a shadow register. When the CCSRBARH |
| 584 | * has a new value written it loads a CCSRBARH shadow register. When |
| 585 | * the CCSRBARL is written, the CCSRBARH shadow register contents |
| 586 | * along with the CCSRBARL value are loaded into the CCSRBARH and |
| 587 | * CCSRBARL registers, respectively. Follow this with a sync |
| 588 | * instruction. |
| 589 | */ |
| 590 | write_new_ccsrbar: |
| 591 | lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h |
| 592 | ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l |
| 593 | lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h |
| 594 | ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l |
| 595 | lis r2, CCSRAR_C@h |
| 596 | ori r2, r2, CCSRAR_C@l |
| 597 | |
| 598 | stw r0, 0(r9) /* Write to CCSRBARH */ |
| 599 | sync /* Make sure we write to CCSRBARH first */ |
| 600 | stw r1, 4(r9) /* Write to CCSRBARL */ |
| 601 | sync |
| 602 | |
| 603 | /* |
| 604 | * Write a 1 to the commit bit (C) of CCSRAR at the old location. |
| 605 | * Follow this with a sync instruction. |
| 606 | */ |
| 607 | stw r2, 8(r9) |
| 608 | sync |
| 609 | |
| 610 | /* Delete the temporary LAW */ |
| 611 | delete_temp_law: |
| 612 | li r1, 0 |
| 613 | stw r1, 0xc08(r8) |
| 614 | sync |
| 615 | stw r1, 0xc00(r8) |
| 616 | stw r1, 0xc04(r8) |
| 617 | sync |
| 618 | |
| 619 | #else /* #ifdef CONFIG_FSL_CORENET */ |
| 620 | |
| 621 | write_new_ccsrbar: |
| 622 | /* |
| 623 | * Read the current value of CCSRBAR using a load word instruction |
| 624 | * followed by an isync. This forces all accesses to configuration |
| 625 | * space to complete. |
| 626 | */ |
| 627 | sync |
| 628 | lwz r0, 0(r9) |
| 629 | isync |
| 630 | |
| 631 | /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ |
| 632 | #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ |
| 633 | (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) |
| 634 | |
| 635 | /* Write the new value to CCSRBAR. */ |
| 636 | lis r0, CCSRBAR_PHYS_RS12@h |
| 637 | ori r0, r0, CCSRBAR_PHYS_RS12@l |
| 638 | stw r0, 0(r9) |
| 639 | sync |
| 640 | |
| 641 | /* |
| 642 | * The manual says to perform a load of an address that does not |
| 643 | * access configuration space or the on-chip SRAM using an existing TLB, |
| 644 | * but that doesn't appear to be necessary. We will do the isync, |
| 645 | * though. |
| 646 | */ |
| 647 | isync |
| 648 | |
| 649 | /* |
| 650 | * Read the contents of CCSRBAR from its new location, followed by |
| 651 | * another isync. |
| 652 | */ |
| 653 | lwz r0, 0(r8) |
| 654 | isync |
| 655 | |
| 656 | #endif /* #ifdef CONFIG_FSL_CORENET */ |
| 657 | |
| 658 | /* Delete the temporary TLBs */ |
| 659 | delete_temp_tlbs: |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 660 | delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 |
| 661 | delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 662 | |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 663 | #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ |
| 664 | |
Prabhakar Kushwaha | cc3c5b6 | 2013-08-29 13:10:38 +0530 | [diff] [blame] | 665 | #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) |
York Sun | c3d87b1 | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 666 | create_ccsr_l2_tlb: |
| 667 | /* |
| 668 | * Create a TLB for the MMR location of CCSR |
| 669 | * to access L2CSR0 register |
| 670 | */ |
| 671 | create_tlb0_entry 0, \ |
| 672 | 0, BOOKE_PAGESZ_4K, \ |
| 673 | CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ |
| 674 | CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ |
| 675 | CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 |
| 676 | |
| 677 | enable_l2_cluster_l2: |
| 678 | /* enable L2 cache */ |
| 679 | lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h |
| 680 | ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l |
| 681 | li r4, 33 /* stash id */ |
| 682 | stw r4, 4(r3) |
| 683 | lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h |
| 684 | ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l |
| 685 | sync |
| 686 | stw r4, 0(r3) /* invalidate L2 */ |
Aneesh Bansal | 5661fcc | 2016-04-18 22:58:33 +0530 | [diff] [blame] | 687 | /* Poll till the bits are cleared */ |
York Sun | c3d87b1 | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 688 | 1: sync |
| 689 | lwz r0, 0(r3) |
| 690 | twi 0, r0, 0 |
| 691 | isync |
| 692 | and. r1, r0, r4 |
| 693 | bne 1b |
Aneesh Bansal | 5661fcc | 2016-04-18 22:58:33 +0530 | [diff] [blame] | 694 | |
| 695 | /* L2PE must be set before L2 cache is enabled */ |
| 696 | lis r4, (L2CSR0_L2PE)@h |
| 697 | ori r4, r4, (L2CSR0_L2PE)@l |
| 698 | sync |
| 699 | stw r4, 0(r3) /* enable L2 parity/ECC error checking */ |
| 700 | /* Poll till the bit is set */ |
| 701 | 1: sync |
| 702 | lwz r0, 0(r3) |
| 703 | twi 0, r0, 0 |
| 704 | isync |
| 705 | and. r1, r0, r4 |
| 706 | beq 1b |
| 707 | |
James Yang | 718fd95 | 2013-03-25 07:39:58 +0000 | [diff] [blame] | 708 | lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h |
James Yang | 284ce50 | 2013-03-25 07:40:03 +0000 | [diff] [blame] | 709 | ori r4, r4, (L2CSR0_L2REP_MODE)@l |
York Sun | c3d87b1 | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 710 | sync |
Andy Fleming | 5631c64 | 2013-03-25 07:33:14 +0000 | [diff] [blame] | 711 | stw r4, 0(r3) /* enable L2 */ |
Aneesh Bansal | 5661fcc | 2016-04-18 22:58:33 +0530 | [diff] [blame] | 712 | /* Poll till the bit is set */ |
| 713 | 1: sync |
| 714 | lwz r0, 0(r3) |
| 715 | twi 0, r0, 0 |
| 716 | isync |
| 717 | and. r1, r0, r4 |
| 718 | beq 1b |
| 719 | |
York Sun | c3d87b1 | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 720 | delete_ccsr_l2_tlb: |
| 721 | delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 |
| 722 | #endif |
| 723 | |
Andy Fleming | 5631c64 | 2013-03-25 07:33:14 +0000 | [diff] [blame] | 724 | /* |
| 725 | * Enable the L1. On e6500, this has to be done |
| 726 | * after the L2 is up. |
| 727 | */ |
| 728 | |
| 729 | #ifdef CONFIG_SYS_CACHE_STASHING |
| 730 | /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ |
| 731 | li r2,(32 + 0) |
| 732 | mtspr L1CSR2,r2 |
| 733 | #endif |
| 734 | |
| 735 | /* Enable/invalidate the I-Cache */ |
| 736 | lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h |
| 737 | ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l |
| 738 | mtspr SPRN_L1CSR1,r2 |
| 739 | 1: |
| 740 | mfspr r3,SPRN_L1CSR1 |
| 741 | and. r1,r3,r2 |
| 742 | bne 1b |
| 743 | |
| 744 | lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h |
| 745 | ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l |
| 746 | mtspr SPRN_L1CSR1,r3 |
| 747 | isync |
| 748 | 2: |
| 749 | mfspr r3,SPRN_L1CSR1 |
| 750 | andi. r1,r3,L1CSR1_ICE@l |
| 751 | beq 2b |
| 752 | |
| 753 | /* Enable/invalidate the D-Cache */ |
| 754 | lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h |
| 755 | ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l |
| 756 | mtspr SPRN_L1CSR0,r2 |
| 757 | 1: |
| 758 | mfspr r3,SPRN_L1CSR0 |
| 759 | and. r1,r3,r2 |
| 760 | bne 1b |
| 761 | |
| 762 | lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h |
| 763 | ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l |
| 764 | mtspr SPRN_L1CSR0,r3 |
| 765 | isync |
| 766 | 2: |
| 767 | mfspr r3,SPRN_L1CSR0 |
| 768 | andi. r1,r3,L1CSR0_DCE@l |
| 769 | beq 2b |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 770 | #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 |
| 771 | #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) |
| 772 | #define LAW_SIZE_1M 0x13 |
| 773 | #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) |
| 774 | |
| 775 | cmpwi r27,0 |
| 776 | beq 9f |
| 777 | |
| 778 | /* |
| 779 | * Create a TLB entry for CCSR |
| 780 | * |
| 781 | * We're executing out of TLB1 entry in r14, and that's the only |
| 782 | * TLB entry that exists. To allocate some TLB entries for our |
| 783 | * own use, flip a bit high enough that we won't flip it again |
| 784 | * via incrementing. |
| 785 | */ |
| 786 | |
| 787 | xori r8, r14, 32 |
| 788 | lis r0, MAS0_TLBSEL(1)@h |
| 789 | rlwimi r0, r8, 16, MAS0_ESEL_MSK |
| 790 | lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h |
| 791 | ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l |
| 792 | lis r7, CONFIG_SYS_CCSRBAR@h |
| 793 | ori r7, r7, CONFIG_SYS_CCSRBAR@l |
| 794 | ori r2, r7, MAS2_I|MAS2_G |
| 795 | lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h |
| 796 | ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l |
| 797 | lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h |
| 798 | ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l |
| 799 | mtspr MAS0, r0 |
| 800 | mtspr MAS1, r1 |
| 801 | mtspr MAS2, r2 |
| 802 | mtspr MAS3, r3 |
| 803 | mtspr MAS7, r4 |
| 804 | isync |
| 805 | tlbwe |
| 806 | isync |
| 807 | msync |
| 808 | |
| 809 | /* Map DCSR temporarily to physical address zero */ |
| 810 | li r0, 0 |
| 811 | lis r3, DCSRBAR_LAWAR@h |
| 812 | ori r3, r3, DCSRBAR_LAWAR@l |
| 813 | |
| 814 | stw r0, 0xc00(r7) /* LAWBARH0 */ |
| 815 | stw r0, 0xc04(r7) /* LAWBARL0 */ |
| 816 | sync |
| 817 | stw r3, 0xc08(r7) /* LAWAR0 */ |
| 818 | |
| 819 | /* Read back from LAWAR to ensure the update is complete. */ |
| 820 | lwz r3, 0xc08(r7) /* LAWAR0 */ |
| 821 | isync |
| 822 | |
| 823 | /* Create a TLB entry for DCSR at zero */ |
| 824 | |
| 825 | addi r9, r8, 1 |
| 826 | lis r0, MAS0_TLBSEL(1)@h |
| 827 | rlwimi r0, r9, 16, MAS0_ESEL_MSK |
| 828 | lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h |
| 829 | ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l |
| 830 | li r6, 0 /* DCSR effective address */ |
| 831 | ori r2, r6, MAS2_I|MAS2_G |
| 832 | li r3, MAS3_SW|MAS3_SR |
| 833 | li r4, 0 |
| 834 | mtspr MAS0, r0 |
| 835 | mtspr MAS1, r1 |
| 836 | mtspr MAS2, r2 |
| 837 | mtspr MAS3, r3 |
| 838 | mtspr MAS7, r4 |
| 839 | isync |
| 840 | tlbwe |
| 841 | isync |
| 842 | msync |
| 843 | |
| 844 | /* enable the timebase */ |
| 845 | #define CTBENR 0xe2084 |
| 846 | li r3, 1 |
| 847 | addis r4, r7, CTBENR@ha |
| 848 | stw r3, CTBENR@l(r4) |
| 849 | lwz r3, CTBENR@l(r4) |
| 850 | twi 0,r3,0 |
| 851 | isync |
| 852 | |
| 853 | .macro erratum_set_ccsr offset value |
| 854 | addis r3, r7, \offset@ha |
| 855 | lis r4, \value@h |
| 856 | addi r3, r3, \offset@l |
| 857 | ori r4, r4, \value@l |
| 858 | bl erratum_set_value |
| 859 | .endm |
| 860 | |
| 861 | .macro erratum_set_dcsr offset value |
| 862 | addis r3, r6, \offset@ha |
| 863 | lis r4, \value@h |
| 864 | addi r3, r3, \offset@l |
| 865 | ori r4, r4, \value@l |
| 866 | bl erratum_set_value |
| 867 | .endm |
| 868 | |
| 869 | erratum_set_dcsr 0xb0e08 0xe0201800 |
| 870 | erratum_set_dcsr 0xb0e18 0xe0201800 |
| 871 | erratum_set_dcsr 0xb0e38 0xe0400000 |
| 872 | erratum_set_dcsr 0xb0008 0x00900000 |
| 873 | erratum_set_dcsr 0xb0e40 0xe00a0000 |
| 874 | erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY |
Dave Liu | 501c010 | 2013-11-28 14:58:08 +0800 | [diff] [blame] | 875 | #ifdef CONFIG_RAMBOOT_PBL |
| 876 | erratum_set_ccsr 0x10f00 0x495e5000 |
| 877 | #else |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 878 | erratum_set_ccsr 0x10f00 0x415e5000 |
Dave Liu | 501c010 | 2013-11-28 14:58:08 +0800 | [diff] [blame] | 879 | #endif |
Scott Wood | 8080696 | 2012-08-14 10:14:53 +0000 | [diff] [blame] | 880 | erratum_set_ccsr 0x11f00 0x415e5000 |
| 881 | |
| 882 | /* Make temp mapping uncacheable again, if it was initially */ |
| 883 | bl 2f |
| 884 | 2: mflr r3 |
| 885 | tlbsx 0, r3 |
| 886 | mfspr r4, MAS2 |
| 887 | rlwimi r4, r15, 0, MAS2_I |
| 888 | rlwimi r4, r15, 0, MAS2_G |
| 889 | mtspr MAS2, r4 |
| 890 | isync |
| 891 | tlbwe |
| 892 | isync |
| 893 | msync |
| 894 | |
| 895 | /* Clear the cache */ |
| 896 | lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h |
| 897 | ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l |
| 898 | sync |
| 899 | isync |
| 900 | mtspr SPRN_L1CSR1,r3 |
| 901 | isync |
| 902 | 2: sync |
| 903 | mfspr r4,SPRN_L1CSR1 |
| 904 | and. r4,r4,r3 |
| 905 | bne 2b |
| 906 | |
| 907 | lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h |
| 908 | ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l |
| 909 | sync |
| 910 | isync |
| 911 | mtspr SPRN_L1CSR1,r3 |
| 912 | isync |
| 913 | 2: sync |
| 914 | mfspr r4,SPRN_L1CSR1 |
| 915 | and. r4,r4,r3 |
| 916 | beq 2b |
| 917 | |
| 918 | /* Remove temporary mappings */ |
| 919 | lis r0, MAS0_TLBSEL(1)@h |
| 920 | rlwimi r0, r9, 16, MAS0_ESEL_MSK |
| 921 | li r3, 0 |
| 922 | mtspr MAS0, r0 |
| 923 | mtspr MAS1, r3 |
| 924 | isync |
| 925 | tlbwe |
| 926 | isync |
| 927 | msync |
| 928 | |
| 929 | li r3, 0 |
| 930 | stw r3, 0xc08(r7) /* LAWAR0 */ |
| 931 | lwz r3, 0xc08(r7) |
| 932 | isync |
| 933 | |
| 934 | lis r0, MAS0_TLBSEL(1)@h |
| 935 | rlwimi r0, r8, 16, MAS0_ESEL_MSK |
| 936 | li r3, 0 |
| 937 | mtspr MAS0, r0 |
| 938 | mtspr MAS1, r3 |
| 939 | isync |
| 940 | tlbwe |
| 941 | isync |
| 942 | msync |
| 943 | |
| 944 | b 9f |
| 945 | |
| 946 | /* r3 = addr, r4 = value, clobbers r5, r11, r12 */ |
| 947 | erratum_set_value: |
| 948 | /* Lock two cache lines into I-Cache */ |
| 949 | sync |
| 950 | mfspr r11, SPRN_L1CSR1 |
| 951 | rlwinm r11, r11, 0, ~L1CSR1_ICUL |
| 952 | sync |
| 953 | isync |
| 954 | mtspr SPRN_L1CSR1, r11 |
| 955 | isync |
| 956 | |
| 957 | mflr r12 |
| 958 | bl 5f |
| 959 | 5: mflr r5 |
| 960 | addi r5, r5, 2f - 5b |
| 961 | icbtls 0, 0, r5 |
| 962 | addi r5, r5, 64 |
| 963 | |
| 964 | sync |
| 965 | mfspr r11, SPRN_L1CSR1 |
| 966 | 3: andi. r11, r11, L1CSR1_ICUL |
| 967 | bne 3b |
| 968 | |
| 969 | icbtls 0, 0, r5 |
| 970 | addi r5, r5, 64 |
| 971 | |
| 972 | sync |
| 973 | mfspr r11, SPRN_L1CSR1 |
| 974 | 3: andi. r11, r11, L1CSR1_ICUL |
| 975 | bne 3b |
| 976 | |
| 977 | b 2f |
| 978 | .align 6 |
| 979 | /* Inside a locked cacheline, wait a while, write, then wait a while */ |
| 980 | 2: sync |
| 981 | |
| 982 | mfspr r5, SPRN_TBRL |
| 983 | addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ |
| 984 | 4: mfspr r5, SPRN_TBRL |
| 985 | subf. r5, r5, r11 |
| 986 | bgt 4b |
| 987 | |
| 988 | stw r4, 0(r3) |
| 989 | |
| 990 | mfspr r5, SPRN_TBRL |
| 991 | addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ |
| 992 | 4: mfspr r5, SPRN_TBRL |
| 993 | subf. r5, r5, r11 |
| 994 | bgt 4b |
| 995 | |
| 996 | sync |
| 997 | |
| 998 | /* |
| 999 | * Fill out the rest of this cache line and the next with nops, |
| 1000 | * to ensure that nothing outside the locked area will be |
| 1001 | * fetched due to a branch. |
| 1002 | */ |
| 1003 | .rept 19 |
| 1004 | nop |
| 1005 | .endr |
| 1006 | |
| 1007 | sync |
| 1008 | mfspr r11, SPRN_L1CSR1 |
| 1009 | rlwinm r11, r11, 0, ~L1CSR1_ICUL |
| 1010 | sync |
| 1011 | isync |
| 1012 | mtspr SPRN_L1CSR1, r11 |
| 1013 | isync |
| 1014 | |
| 1015 | mtlr r12 |
| 1016 | blr |
| 1017 | |
| 1018 | 9: |
| 1019 | #endif |
| 1020 | |
Timur Tabi | e769dea | 2011-08-03 16:30:10 -0500 | [diff] [blame] | 1021 | create_init_ram_area: |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 1022 | lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h |
| 1023 | ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l |
| 1024 | |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 1025 | #ifdef NOR_BOOT |
Mingkai Hu | 0255cd7 | 2009-09-11 14:19:10 +0800 | [diff] [blame] | 1026 | /* create a temp mapping in AS=1 to the 4M boot window */ |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1027 | create_tlb1_entry 15, \ |
| 1028 | 1, BOOKE_PAGESZ_4M, \ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1029 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xffc00000, MAS2_I|MAS2_G, \ |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1030 | 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ |
| 1031 | 0, r6 |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 1032 | |
Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 1033 | #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC) |
Ruchika Gupta | 8ca8d82 | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 1034 | /* create a temp mapping in AS = 1 for Flash mapping |
| 1035 | * created by PBL for ISBC code |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 1036 | */ |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1037 | create_tlb1_entry 15, \ |
| 1038 | 1, BOOKE_PAGESZ_1M, \ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1039 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ |
Scott Wood | f217316 | 2012-09-20 18:34:49 -0500 | [diff] [blame] | 1040 | CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1041 | 0, r6 |
Aneesh Bansal | e0f5015 | 2015-06-16 10:36:00 +0530 | [diff] [blame] | 1042 | |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 1043 | /* |
| 1044 | * For Targets without CONFIG_SPL like P3, P5 |
| 1045 | * and for targets with CONFIG_SPL like T1, T2, T4, only for |
| 1046 | * u-boot-spl i.e. CONFIG_SPL_BUILD |
| 1047 | */ |
Udit Agarwal | d2dd2f7 | 2019-11-07 16:11:39 +0000 | [diff] [blame] | 1048 | #elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \ |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 1049 | (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1050 | /* create a temp mapping in AS = 1 for mapping CONFIG_VAL(SYS_MONITOR_BASE) |
Aneesh Bansal | e0f5015 | 2015-06-16 10:36:00 +0530 | [diff] [blame] | 1051 | * to L3 Address configured by PBL for ISBC code |
Sumit Garg | afaca2a | 2016-07-14 12:27:52 -0400 | [diff] [blame] | 1052 | */ |
Aneesh Bansal | e0f5015 | 2015-06-16 10:36:00 +0530 | [diff] [blame] | 1053 | create_tlb1_entry 15, \ |
| 1054 | 1, BOOKE_PAGESZ_1M, \ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1055 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ |
Aneesh Bansal | e0f5015 | 2015-06-16 10:36:00 +0530 | [diff] [blame] | 1056 | CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ |
| 1057 | 0, r6 |
| 1058 | |
Mingkai Hu | 0255cd7 | 2009-09-11 14:19:10 +0800 | [diff] [blame] | 1059 | #else |
| 1060 | /* |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1061 | * create a temp mapping in AS=1 to the 1M CONFIG_VAL(SYS_MONITOR_BASE) space, the main |
| 1062 | * image has been relocated to CONFIG_VAL(SYS_MONITOR_BASE) on the second stage. |
Mingkai Hu | 0255cd7 | 2009-09-11 14:19:10 +0800 | [diff] [blame] | 1063 | */ |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1064 | create_tlb1_entry 15, \ |
| 1065 | 1, BOOKE_PAGESZ_1M, \ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1066 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ |
| 1067 | CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1068 | 0, r6 |
Mingkai Hu | 0255cd7 | 2009-09-11 14:19:10 +0800 | [diff] [blame] | 1069 | #endif |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 1070 | |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 1071 | /* create a temp mapping in AS=1 to the stack */ |
york | c609332 | 2010-07-02 22:25:57 +0000 | [diff] [blame] | 1072 | #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ |
| 1073 | defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1074 | create_tlb1_entry 14, \ |
| 1075 | 1, BOOKE_PAGESZ_16K, \ |
| 1076 | CONFIG_SYS_INIT_RAM_ADDR, 0, \ |
| 1077 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ |
| 1078 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 |
| 1079 | |
york | c609332 | 2010-07-02 22:25:57 +0000 | [diff] [blame] | 1080 | #else |
York Sun | 0f2f2a3 | 2012-10-08 07:44:07 +0000 | [diff] [blame] | 1081 | create_tlb1_entry 14, \ |
| 1082 | 1, BOOKE_PAGESZ_16K, \ |
| 1083 | CONFIG_SYS_INIT_RAM_ADDR, 0, \ |
| 1084 | CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ |
| 1085 | 0, r6 |
york | c609332 | 2010-07-02 22:25:57 +0000 | [diff] [blame] | 1086 | #endif |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 1087 | |
Prabhakar Kushwaha | 8f3e892 | 2012-04-29 23:56:30 +0000 | [diff] [blame] | 1088 | lis r6,MSR_IS|MSR_DS|MSR_DE@h |
| 1089 | ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 1090 | lis r7,switch_as@h |
| 1091 | ori r7,r7,switch_as@l |
| 1092 | |
| 1093 | mtspr SPRN_SRR0,r7 |
| 1094 | mtspr SPRN_SRR1,r6 |
| 1095 | rfi |
| 1096 | |
| 1097 | switch_as: |
Kumar Gala | 76e276b | 2007-08-07 18:07:27 -0500 | [diff] [blame] | 1098 | /* L1 DCache is used for initial RAM */ |
| 1099 | |
| 1100 | /* Allocate Initial RAM in data cache. |
| 1101 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 1102 | lis r3,CONFIG_SYS_INIT_RAM_ADDR@h |
| 1103 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l |
Kumar Gala | 938e14e | 2008-01-08 01:22:21 -0600 | [diff] [blame] | 1104 | mfspr r2, L1CFG0 |
| 1105 | andi. r2, r2, 0x1ff |
| 1106 | /* cache size * 1024 / (2 * L1 line size) */ |
| 1107 | slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) |
Kumar Gala | 76e276b | 2007-08-07 18:07:27 -0500 | [diff] [blame] | 1108 | mtctr r2 |
| 1109 | li r0,0 |
| 1110 | 1: |
| 1111 | dcbz r0,r3 |
Ruchika Gupta | bba41d9 | 2017-03-02 14:12:41 +0530 | [diff] [blame] | 1112 | #ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */ |
York Sun | 8d45cc1 | 2015-08-17 13:31:52 -0700 | [diff] [blame] | 1113 | dcbtls 2, r0, r3 |
Ruchika Gupta | bba41d9 | 2017-03-02 14:12:41 +0530 | [diff] [blame] | 1114 | dcbtls 0, r0, r3 |
York Sun | 8d45cc1 | 2015-08-17 13:31:52 -0700 | [diff] [blame] | 1115 | #else |
| 1116 | dcbtls 0, r0, r3 |
| 1117 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 1118 | addi r3,r3,CONFIG_SYS_CACHELINE_SIZE |
Kumar Gala | 76e276b | 2007-08-07 18:07:27 -0500 | [diff] [blame] | 1119 | bdnz 1b |
| 1120 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1121 | /* Jump out the last 4K page and continue to 'normal' start */ |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 1122 | #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) |
| 1123 | /* We assume that we're already running at the address we're linked at */ |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1124 | b _start_cont |
Kumar Gala | 76e276b | 2007-08-07 18:07:27 -0500 | [diff] [blame] | 1125 | #else |
| 1126 | /* Calculate absolute address in FLASH and jump there */ |
| 1127 | /*--------------------------------------------------------------*/ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1128 | lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h |
| 1129 | ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l |
Pali Rohár | 674642c | 2022-04-25 09:29:08 +0530 | [diff] [blame^] | 1130 | addi r3,r3,_start_cont - _start_cont |
Kumar Gala | 76e276b | 2007-08-07 18:07:27 -0500 | [diff] [blame] | 1131 | mtlr r3 |
urwithsughosh@gmail.com | e9f4e34 | 2007-09-24 13:36:01 -0400 | [diff] [blame] | 1132 | blr |
Kumar Gala | 76e276b | 2007-08-07 18:07:27 -0500 | [diff] [blame] | 1133 | #endif |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1134 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1135 | .text |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1136 | .globl _start_cont |
| 1137 | _start_cont: |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1138 | /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ |
Joakim Tjernlund | 258120c | 2012-07-23 10:58:02 +0000 | [diff] [blame] | 1139 | lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h |
| 1140 | ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ |
mario.six@gdsys.cc | d5928cd | 2016-04-05 15:05:37 +0200 | [diff] [blame] | 1141 | |
Andy Yan | ad0ac4b | 2017-07-24 17:47:27 +0800 | [diff] [blame] | 1142 | #if CONFIG_VAL(SYS_MALLOC_F_LEN) |
| 1143 | #if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE |
| 1144 | #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." |
mario.six@gdsys.cc | d5928cd | 2016-04-05 15:05:37 +0200 | [diff] [blame] | 1145 | #endif |
| 1146 | |
| 1147 | /* Leave 16+ byte for back chain termination and NULL return address */ |
Andy Yan | ad0ac4b | 2017-07-24 17:47:27 +0800 | [diff] [blame] | 1148 | subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf) |
mario.six@gdsys.cc | d5928cd | 2016-04-05 15:05:37 +0200 | [diff] [blame] | 1149 | #endif |
| 1150 | |
| 1151 | /* End of RAM */ |
| 1152 | lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h |
| 1153 | ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l |
| 1154 | |
| 1155 | li r0,0 |
| 1156 | |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 1157 | 1: subi r4,r4,4 |
| 1158 | stw r0,0(r4) |
| 1159 | cmplw r4,r3 |
mario.six@gdsys.cc | d5928cd | 2016-04-05 15:05:37 +0200 | [diff] [blame] | 1160 | bne 1b |
| 1161 | |
Andy Yan | ad0ac4b | 2017-07-24 17:47:27 +0800 | [diff] [blame] | 1162 | #if CONFIG_VAL(SYS_MALLOC_F_LEN) |
mario.six@gdsys.cc | d5928cd | 2016-04-05 15:05:37 +0200 | [diff] [blame] | 1163 | lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h |
| 1164 | ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l |
| 1165 | |
| 1166 | addi r3,r3,16 /* Pre-relocation malloc area */ |
| 1167 | stw r3,GD_MALLOC_BASE(r4) |
| 1168 | subi r3,r3,16 |
| 1169 | #endif |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1170 | li r0,0 |
Joakim Tjernlund | 258120c | 2012-07-23 10:58:02 +0000 | [diff] [blame] | 1171 | stw r0,0(r3) /* Terminate Back Chain */ |
| 1172 | stw r0,+4(r3) /* NULL return address. */ |
| 1173 | mr r1,r3 /* Transfer to SP(r1) */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1174 | |
| 1175 | GET_GOT |
Joakim Tjernlund | f2c2c30 | 2018-12-06 17:20:53 +0100 | [diff] [blame] | 1176 | /* Needed for -msingle-pic-base */ |
| 1177 | bl _GLOBAL_OFFSET_TABLE_@local-4 |
| 1178 | mflr r30 |
Alexander Graf | c346848 | 2014-04-11 17:09:45 +0200 | [diff] [blame] | 1179 | |
| 1180 | /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */ |
| 1181 | mr r3, r24 |
| 1182 | |
Kumar Gala | 9772ee7 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 1183 | bl cpu_init_early_f |
| 1184 | |
| 1185 | /* switch back to AS = 0 */ |
| 1186 | lis r3,(MSR_CE|MSR_ME|MSR_DE)@h |
| 1187 | ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l |
| 1188 | mtmsr r3 |
| 1189 | isync |
| 1190 | |
York Sun | 695c0c3 | 2014-04-30 14:43:47 -0700 | [diff] [blame] | 1191 | bl cpu_init_f /* return boot_flag for calling board_init_f */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1192 | bl board_init_f |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 1193 | isync |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1194 | |
Peter Tyser | 0c44caf | 2010-09-14 19:13:53 -0500 | [diff] [blame] | 1195 | /* NOTREACHED - board_init_f() does not return */ |
| 1196 | |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 1197 | #ifndef MINIMAL_SPL |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1198 | .globl _start_of_vectors |
| 1199 | _start_of_vectors: |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1200 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1201 | /* Critical input. */ |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1202 | CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) |
| 1203 | |
| 1204 | /* Machine check */ |
| 1205 | MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1206 | |
| 1207 | /* Data Storage exception. */ |
| 1208 | STD_EXCEPTION(0x0300, DataStorage, UnknownException) |
| 1209 | |
| 1210 | /* Instruction Storage exception. */ |
| 1211 | STD_EXCEPTION(0x0400, InstStorage, UnknownException) |
| 1212 | |
| 1213 | /* External Interrupt exception. */ |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1214 | STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1215 | |
| 1216 | /* Alignment exception. */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1217 | Alignment: |
Rafal Jaworowski | 06244e4 | 2007-06-22 14:58:04 +0200 | [diff] [blame] | 1218 | EXCEPTION_PROLOG(SRR0, SRR1) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1219 | mfspr r4,DAR |
| 1220 | stw r4,_DAR(r21) |
| 1221 | mfspr r5,DSISR |
| 1222 | stw r5,_DSISR(r21) |
| 1223 | addi r3,r1,STACK_FRAME_OVERHEAD |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1224 | EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException, |
| 1225 | MSR_KERNEL, COPY_EE) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1226 | |
| 1227 | /* Program check exception */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1228 | ProgramCheck: |
Rafal Jaworowski | 06244e4 | 2007-06-22 14:58:04 +0200 | [diff] [blame] | 1229 | EXCEPTION_PROLOG(SRR0, SRR1) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1230 | addi r3,r1,STACK_FRAME_OVERHEAD |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1231 | EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException, |
Joakim Tjernlund | 4ff6bc0 | 2010-01-19 14:41:55 +0100 | [diff] [blame] | 1232 | MSR_KERNEL, COPY_EE) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1233 | |
| 1234 | /* No FPU on MPC85xx. This exception is not supposed to happen. |
| 1235 | */ |
| 1236 | STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) |
Scott Wood | 5b4d7ff | 2015-04-07 20:20:01 -0500 | [diff] [blame] | 1237 | STD_EXCEPTION(0x0900, SystemCall, UnknownException) |
wdenk | f3da7cc | 2005-05-13 22:49:36 +0000 | [diff] [blame] | 1238 | STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) |
| 1239 | STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) |
| 1240 | STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1241 | |
wdenk | f3da7cc | 2005-05-13 22:49:36 +0000 | [diff] [blame] | 1242 | STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) |
| 1243 | STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1244 | |
wdenk | f3da7cc | 2005-05-13 22:49:36 +0000 | [diff] [blame] | 1245 | CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1246 | |
wdenk | f3da7cc | 2005-05-13 22:49:36 +0000 | [diff] [blame] | 1247 | .globl _end_of_vectors |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1248 | _end_of_vectors: |
| 1249 | |
| 1250 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1251 | . = . + (0x100 - ( . & 0xff )) /* align for debug */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1252 | |
| 1253 | /* |
| 1254 | * This code finishes saving the registers to the exception frame |
| 1255 | * and jumps to the appropriate handler for the exception. |
| 1256 | * Register r21 is pointer into trap frame, r1 has new stack pointer. |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1257 | * r23 is the address of the handler. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1258 | */ |
| 1259 | .globl transfer_to_handler |
| 1260 | transfer_to_handler: |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1261 | SAVE_GPR(7, r21) |
| 1262 | SAVE_4GPRS(8, r21) |
| 1263 | SAVE_8GPRS(12, r21) |
| 1264 | SAVE_8GPRS(24, r21) |
| 1265 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1266 | li r22,0 |
| 1267 | stw r22,RESULT(r21) |
| 1268 | mtspr SPRG2,r22 /* r1 is now kernel sp */ |
| 1269 | |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1270 | mtctr r23 /* virtual address of handler */ |
| 1271 | mtmsr r20 |
| 1272 | bctrl |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1273 | |
| 1274 | int_return: |
| 1275 | mfmsr r28 /* Disable interrupts */ |
| 1276 | li r4,0 |
| 1277 | ori r4,r4,MSR_EE |
| 1278 | andc r28,r28,r4 |
| 1279 | SYNC /* Some chip revs need this... */ |
| 1280 | mtmsr r28 |
| 1281 | SYNC |
| 1282 | lwz r2,_CTR(r1) |
| 1283 | lwz r0,_LINK(r1) |
| 1284 | mtctr r2 |
| 1285 | mtlr r0 |
| 1286 | lwz r2,_XER(r1) |
| 1287 | lwz r0,_CCR(r1) |
| 1288 | mtspr XER,r2 |
| 1289 | mtcrf 0xFF,r0 |
| 1290 | REST_10GPRS(3, r1) |
| 1291 | REST_10GPRS(13, r1) |
| 1292 | REST_8GPRS(23, r1) |
| 1293 | REST_GPR(31, r1) |
| 1294 | lwz r2,_NIP(r1) /* Restore environment */ |
| 1295 | lwz r0,_MSR(r1) |
| 1296 | mtspr SRR0,r2 |
| 1297 | mtspr SRR1,r0 |
| 1298 | lwz r0,GPR0(r1) |
| 1299 | lwz r2,GPR2(r1) |
| 1300 | lwz r1,GPR1(r1) |
| 1301 | SYNC |
| 1302 | rfi |
| 1303 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1304 | /* Cache functions. |
| 1305 | */ |
Matthew McClintock | c83e7ef | 2011-05-23 08:38:53 +0000 | [diff] [blame] | 1306 | .globl flush_icache |
| 1307 | flush_icache: |
Kumar Gala | 32090b3 | 2008-09-22 14:11:10 -0500 | [diff] [blame] | 1308 | .globl invalidate_icache |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1309 | invalidate_icache: |
| 1310 | mfspr r0,L1CSR1 |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1311 | ori r0,r0,L1CSR1_ICFI |
| 1312 | msync |
| 1313 | isync |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1314 | mtspr L1CSR1,r0 |
| 1315 | isync |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1316 | blr /* entire I cache */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1317 | |
Kumar Gala | 32090b3 | 2008-09-22 14:11:10 -0500 | [diff] [blame] | 1318 | .globl invalidate_dcache |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1319 | invalidate_dcache: |
| 1320 | mfspr r0,L1CSR0 |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1321 | ori r0,r0,L1CSR0_DCFI |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1322 | msync |
| 1323 | isync |
| 1324 | mtspr L1CSR0,r0 |
| 1325 | isync |
| 1326 | blr |
| 1327 | |
| 1328 | .globl icache_enable |
| 1329 | icache_enable: |
| 1330 | mflr r8 |
| 1331 | bl invalidate_icache |
| 1332 | mtlr r8 |
| 1333 | isync |
| 1334 | mfspr r4,L1CSR1 |
Mark Marshall | f2770f4 | 2017-01-24 15:40:23 +0100 | [diff] [blame] | 1335 | ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l |
| 1336 | oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1337 | mtspr L1CSR1,r4 |
| 1338 | isync |
| 1339 | blr |
| 1340 | |
| 1341 | .globl icache_disable |
| 1342 | icache_disable: |
| 1343 | mfspr r0,L1CSR1 |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1344 | lis r3,0 |
| 1345 | ori r3,r3,L1CSR1_ICE |
| 1346 | andc r0,r0,r3 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1347 | mtspr L1CSR1,r0 |
| 1348 | isync |
| 1349 | blr |
| 1350 | |
| 1351 | .globl icache_status |
| 1352 | icache_status: |
| 1353 | mfspr r3,L1CSR1 |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1354 | andi. r3,r3,L1CSR1_ICE |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1355 | blr |
| 1356 | |
| 1357 | .globl dcache_enable |
| 1358 | dcache_enable: |
| 1359 | mflr r8 |
| 1360 | bl invalidate_dcache |
| 1361 | mtlr r8 |
| 1362 | isync |
| 1363 | mfspr r0,L1CSR0 |
Mark Marshall | f2770f4 | 2017-01-24 15:40:23 +0100 | [diff] [blame] | 1364 | ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l |
| 1365 | oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1366 | msync |
| 1367 | isync |
| 1368 | mtspr L1CSR0,r0 |
| 1369 | isync |
| 1370 | blr |
| 1371 | |
| 1372 | .globl dcache_disable |
| 1373 | dcache_disable: |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1374 | mfspr r3,L1CSR0 |
| 1375 | lis r4,0 |
| 1376 | ori r4,r4,L1CSR0_DCE |
| 1377 | andc r3,r3,r4 |
Kumar Gala | fa103bf | 2011-01-05 10:33:46 -0600 | [diff] [blame] | 1378 | mtspr L1CSR0,r3 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1379 | isync |
| 1380 | blr |
| 1381 | |
| 1382 | .globl dcache_status |
| 1383 | dcache_status: |
| 1384 | mfspr r3,L1CSR0 |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1385 | andi. r3,r3,L1CSR0_DCE |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1386 | blr |
| 1387 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1388 | /*------------------------------------------------------------------------------- */ |
| 1389 | /* Function: in8 */ |
| 1390 | /* Description: Input 8 bits */ |
| 1391 | /*------------------------------------------------------------------------------- */ |
| 1392 | .globl in8 |
| 1393 | in8: |
| 1394 | lbz r3,0x0000(r3) |
| 1395 | blr |
| 1396 | |
| 1397 | /*------------------------------------------------------------------------------- */ |
| 1398 | /* Function: out8 */ |
| 1399 | /* Description: Output 8 bits */ |
| 1400 | /*------------------------------------------------------------------------------- */ |
| 1401 | .globl out8 |
| 1402 | out8: |
| 1403 | stb r4,0x0000(r3) |
Ed Swarthout | 7d6be30 | 2007-09-26 16:35:54 -0500 | [diff] [blame] | 1404 | sync |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1405 | blr |
| 1406 | |
| 1407 | /*------------------------------------------------------------------------------- */ |
| 1408 | /* Function: out16 */ |
| 1409 | /* Description: Output 16 bits */ |
| 1410 | /*------------------------------------------------------------------------------- */ |
| 1411 | .globl out16 |
| 1412 | out16: |
| 1413 | sth r4,0x0000(r3) |
Ed Swarthout | 7d6be30 | 2007-09-26 16:35:54 -0500 | [diff] [blame] | 1414 | sync |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1415 | blr |
| 1416 | |
| 1417 | /*------------------------------------------------------------------------------- */ |
| 1418 | /* Function: out16r */ |
| 1419 | /* Description: Byte reverse and output 16 bits */ |
| 1420 | /*------------------------------------------------------------------------------- */ |
| 1421 | .globl out16r |
| 1422 | out16r: |
| 1423 | sthbrx r4,r0,r3 |
Ed Swarthout | 7d6be30 | 2007-09-26 16:35:54 -0500 | [diff] [blame] | 1424 | sync |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1425 | blr |
| 1426 | |
| 1427 | /*------------------------------------------------------------------------------- */ |
| 1428 | /* Function: out32 */ |
| 1429 | /* Description: Output 32 bits */ |
| 1430 | /*------------------------------------------------------------------------------- */ |
| 1431 | .globl out32 |
| 1432 | out32: |
| 1433 | stw r4,0x0000(r3) |
Ed Swarthout | 7d6be30 | 2007-09-26 16:35:54 -0500 | [diff] [blame] | 1434 | sync |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1435 | blr |
| 1436 | |
| 1437 | /*------------------------------------------------------------------------------- */ |
| 1438 | /* Function: out32r */ |
| 1439 | /* Description: Byte reverse and output 32 bits */ |
| 1440 | /*------------------------------------------------------------------------------- */ |
| 1441 | .globl out32r |
| 1442 | out32r: |
| 1443 | stwbrx r4,r0,r3 |
Ed Swarthout | 7d6be30 | 2007-09-26 16:35:54 -0500 | [diff] [blame] | 1444 | sync |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1445 | blr |
| 1446 | |
| 1447 | /*------------------------------------------------------------------------------- */ |
| 1448 | /* Function: in16 */ |
| 1449 | /* Description: Input 16 bits */ |
| 1450 | /*------------------------------------------------------------------------------- */ |
| 1451 | .globl in16 |
| 1452 | in16: |
| 1453 | lhz r3,0x0000(r3) |
| 1454 | blr |
| 1455 | |
| 1456 | /*------------------------------------------------------------------------------- */ |
| 1457 | /* Function: in16r */ |
| 1458 | /* Description: Input 16 bits and byte reverse */ |
| 1459 | /*------------------------------------------------------------------------------- */ |
| 1460 | .globl in16r |
| 1461 | in16r: |
| 1462 | lhbrx r3,r0,r3 |
| 1463 | blr |
| 1464 | |
| 1465 | /*------------------------------------------------------------------------------- */ |
| 1466 | /* Function: in32 */ |
| 1467 | /* Description: Input 32 bits */ |
| 1468 | /*------------------------------------------------------------------------------- */ |
| 1469 | .globl in32 |
| 1470 | in32: |
| 1471 | lwz 3,0x0000(3) |
| 1472 | blr |
| 1473 | |
| 1474 | /*------------------------------------------------------------------------------- */ |
| 1475 | /* Function: in32r */ |
| 1476 | /* Description: Input 32 bits and byte reverse */ |
| 1477 | /*------------------------------------------------------------------------------- */ |
| 1478 | .globl in32r |
| 1479 | in32r: |
| 1480 | lwbrx r3,r0,r3 |
| 1481 | blr |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 1482 | #endif /* !MINIMAL_SPL */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1483 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1484 | /*------------------------------------------------------------------------------*/ |
| 1485 | |
| 1486 | /* |
Kumar Gala | c417c91 | 2009-09-11 11:27:00 -0500 | [diff] [blame] | 1487 | * void write_tlb(mas0, mas1, mas2, mas3, mas7) |
| 1488 | */ |
| 1489 | .globl write_tlb |
| 1490 | write_tlb: |
| 1491 | mtspr MAS0,r3 |
| 1492 | mtspr MAS1,r4 |
| 1493 | mtspr MAS2,r5 |
| 1494 | mtspr MAS3,r6 |
| 1495 | #ifdef CONFIG_ENABLE_36BIT_PHYS |
| 1496 | mtspr MAS7,r7 |
| 1497 | #endif |
| 1498 | li r3,0 |
| 1499 | #ifdef CONFIG_SYS_BOOK3E_HV |
| 1500 | mtspr MAS8,r3 |
| 1501 | #endif |
| 1502 | isync |
| 1503 | tlbwe |
| 1504 | msync |
| 1505 | isync |
| 1506 | blr |
| 1507 | |
| 1508 | /* |
Simon Glass | 284f71b | 2019-12-28 10:44:45 -0700 | [diff] [blame] | 1509 | * void relocate_code(addr_sp, gd, addr_moni) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1510 | * |
| 1511 | * This "function" does not return, instead it continues in RAM |
| 1512 | * after relocating the monitor code. |
| 1513 | * |
| 1514 | * r3 = dest |
| 1515 | * r4 = src |
| 1516 | * r5 = length in bytes |
| 1517 | * r6 = cachelinesize |
| 1518 | */ |
| 1519 | .globl relocate_code |
| 1520 | relocate_code: |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1521 | mr r1,r3 /* Set new stack pointer */ |
| 1522 | mr r9,r4 /* Save copy of Init Data pointer */ |
| 1523 | mr r10,r5 /* Save copy of Destination Address */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1524 | |
Joakim Tjernlund | 3fbaa4d | 2010-01-19 14:41:56 +0100 | [diff] [blame] | 1525 | GET_GOT |
Prabhakar Kushwaha | 6e2b9a3 | 2014-04-08 19:12:31 +0530 | [diff] [blame] | 1526 | #ifndef CONFIG_SPL_SKIP_RELOCATE |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1527 | mr r3,r5 /* Destination Address */ |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1528 | lis r4,CONFIG_VAL(SYS_MONITOR_BASE)@h /* Source Address */ |
| 1529 | ori r4,r4,CONFIG_VAL(SYS_MONITOR_BASE)@l |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1530 | lwz r5,GOT(__init_end) |
| 1531 | sub r5,r5,r4 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 1532 | li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1533 | |
| 1534 | /* |
| 1535 | * Fix GOT pointer: |
| 1536 | * |
Tom Rini | 03becca | 2022-03-24 17:18:05 -0400 | [diff] [blame] | 1537 | * New GOT-PTR = (old GOT-PTR - CONFIG_VAL(SYS_MONITOR_BASE)) + Destination Address |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1538 | * |
| 1539 | * Offset: |
| 1540 | */ |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1541 | sub r15,r10,r4 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1542 | |
| 1543 | /* First our own GOT */ |
Joakim Tjernlund | 3fbaa4d | 2010-01-19 14:41:56 +0100 | [diff] [blame] | 1544 | add r12,r12,r15 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1545 | /* the the one used by the C code */ |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1546 | add r30,r30,r15 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1547 | |
| 1548 | /* |
| 1549 | * Now relocate code |
| 1550 | */ |
| 1551 | |
| 1552 | cmplw cr1,r3,r4 |
| 1553 | addi r0,r5,3 |
| 1554 | srwi. r0,r0,2 |
| 1555 | beq cr1,4f /* In place copy is not necessary */ |
| 1556 | beq 7f /* Protect against 0 count */ |
| 1557 | mtctr r0 |
| 1558 | bge cr1,2f |
| 1559 | |
| 1560 | la r8,-4(r4) |
| 1561 | la r7,-4(r3) |
| 1562 | 1: lwzu r0,4(r8) |
| 1563 | stwu r0,4(r7) |
| 1564 | bdnz 1b |
| 1565 | b 4f |
| 1566 | |
| 1567 | 2: slwi r0,r0,2 |
| 1568 | add r8,r4,r0 |
| 1569 | add r7,r3,r0 |
| 1570 | 3: lwzu r0,-4(r8) |
| 1571 | stwu r0,-4(r7) |
| 1572 | bdnz 3b |
| 1573 | |
| 1574 | /* |
| 1575 | * Now flush the cache: note that we must start from a cache aligned |
| 1576 | * address. Otherwise we might miss one cache line. |
| 1577 | */ |
| 1578 | 4: cmpwi r6,0 |
| 1579 | add r5,r3,r5 |
| 1580 | beq 7f /* Always flush prefetch queue in any case */ |
| 1581 | subi r0,r6,1 |
| 1582 | andc r3,r3,r0 |
| 1583 | mr r4,r3 |
| 1584 | 5: dcbst 0,r4 |
| 1585 | add r4,r4,r6 |
| 1586 | cmplw r4,r5 |
| 1587 | blt 5b |
| 1588 | sync /* Wait for all dcbst to complete on bus */ |
| 1589 | mr r4,r3 |
| 1590 | 6: icbi 0,r4 |
| 1591 | add r4,r4,r6 |
| 1592 | cmplw r4,r5 |
| 1593 | blt 6b |
| 1594 | 7: sync /* Wait for all icbi to complete on bus */ |
| 1595 | isync |
| 1596 | |
| 1597 | /* |
| 1598 | * We are done. Do not return, instead branch to second part of board |
| 1599 | * initialization, now running from RAM. |
| 1600 | */ |
| 1601 | |
Pali Rohár | 674642c | 2022-04-25 09:29:08 +0530 | [diff] [blame^] | 1602 | addi r0,r10,in_ram - _start_cont |
Prabhakar Kushwaha | bc8d57c | 2012-04-29 23:56:43 +0000 | [diff] [blame] | 1603 | |
| 1604 | /* |
| 1605 | * As IVPR is going to point RAM address, |
| 1606 | * Make sure IVOR15 has valid opcode to support debugger |
| 1607 | */ |
| 1608 | mtspr IVOR15,r0 |
| 1609 | |
| 1610 | /* |
| 1611 | * Re-point the IVPR at RAM |
| 1612 | */ |
| 1613 | mtspr IVPR,r10 |
| 1614 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1615 | mtlr r0 |
| 1616 | blr /* NEVER RETURNS! */ |
Prabhakar Kushwaha | 6e2b9a3 | 2014-04-08 19:12:31 +0530 | [diff] [blame] | 1617 | #endif |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1618 | .globl in_ram |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1619 | in_ram: |
| 1620 | |
| 1621 | /* |
Joakim Tjernlund | 3fbaa4d | 2010-01-19 14:41:56 +0100 | [diff] [blame] | 1622 | * Relocation Function, r12 point to got2+0x8000 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1623 | * |
| 1624 | * Adjust got2 pointers, no need to check for 0, this code |
| 1625 | * already puts a few entries in the table. |
| 1626 | */ |
| 1627 | li r0,__got2_entries@sectoff@l |
| 1628 | la r3,GOT(_GOT2_TABLE_) |
| 1629 | lwz r11,GOT(_GOT2_TABLE_) |
| 1630 | mtctr r0 |
| 1631 | sub r11,r3,r11 |
| 1632 | addi r3,r3,-4 |
| 1633 | 1: lwzu r0,4(r3) |
Joakim Tjernlund | 4f2fdac | 2009-10-08 02:03:51 +0200 | [diff] [blame] | 1634 | cmpwi r0,0 |
| 1635 | beq- 2f |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1636 | add r0,r0,r11 |
| 1637 | stw r0,0(r3) |
Joakim Tjernlund | 4f2fdac | 2009-10-08 02:03:51 +0200 | [diff] [blame] | 1638 | 2: bdnz 1b |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1639 | |
| 1640 | /* |
| 1641 | * Now adjust the fixups and the pointers to the fixups |
| 1642 | * in case we need to move ourselves again. |
| 1643 | */ |
Joakim Tjernlund | 4f2fdac | 2009-10-08 02:03:51 +0200 | [diff] [blame] | 1644 | li r0,__fixup_entries@sectoff@l |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1645 | lwz r3,GOT(_FIXUP_TABLE_) |
| 1646 | cmpwi r0,0 |
| 1647 | mtctr r0 |
| 1648 | addi r3,r3,-4 |
| 1649 | beq 4f |
| 1650 | 3: lwzu r4,4(r3) |
| 1651 | lwzux r0,r4,r11 |
Joakim Tjernlund | c61b25a | 2010-10-14 11:51:44 +0200 | [diff] [blame] | 1652 | cmpwi r0,0 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1653 | add r0,r0,r11 |
Joakim Tjernlund | 401b592 | 2010-11-04 19:02:00 +0100 | [diff] [blame] | 1654 | stw r4,0(r3) |
Joakim Tjernlund | c61b25a | 2010-10-14 11:51:44 +0200 | [diff] [blame] | 1655 | beq- 5f |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1656 | stw r0,0(r4) |
Joakim Tjernlund | c61b25a | 2010-10-14 11:51:44 +0200 | [diff] [blame] | 1657 | 5: bdnz 3b |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1658 | 4: |
| 1659 | clear_bss: |
| 1660 | /* |
| 1661 | * Now clear BSS segment |
| 1662 | */ |
| 1663 | lwz r3,GOT(__bss_start) |
Simon Glass | ed70c8f | 2013-03-14 06:54:53 +0000 | [diff] [blame] | 1664 | lwz r4,GOT(__bss_end) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1665 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1666 | cmplw 0,r3,r4 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1667 | beq 6f |
| 1668 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1669 | li r0,0 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1670 | 5: |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1671 | stw r0,0(r3) |
| 1672 | addi r3,r3,4 |
| 1673 | cmplw 0,r3,r4 |
Ying Zhang | 5ca62f2 | 2013-06-07 17:25:16 +0800 | [diff] [blame] | 1674 | blt 5b |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1675 | 6: |
| 1676 | |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1677 | mr r3,r9 /* Init Data pointer */ |
| 1678 | mr r4,r10 /* Destination Address */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1679 | bl board_init_r |
| 1680 | |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 1681 | #ifndef MINIMAL_SPL |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1682 | /* |
| 1683 | * Copy exception vector code to low memory |
| 1684 | * |
| 1685 | * r3: dest_addr |
| 1686 | * r7: source address, r8: end address, r9: target address |
| 1687 | */ |
wdenk | f3da7cc | 2005-05-13 22:49:36 +0000 | [diff] [blame] | 1688 | .globl trap_init |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1689 | trap_init: |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1690 | mflr r11 |
| 1691 | bl _GLOBAL_OFFSET_TABLE_-4 |
| 1692 | mflr r12 |
| 1693 | |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1694 | /* Update IVORs as per relocation */ |
| 1695 | mtspr IVPR,r3 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1696 | |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1697 | lwz r4,CriticalInput@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1698 | mtspr IVOR0,r4 /* 0: Critical input */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1699 | lwz r4,MachineCheck@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1700 | mtspr IVOR1,r4 /* 1: Machine check */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1701 | lwz r4,DataStorage@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1702 | mtspr IVOR2,r4 /* 2: Data storage */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1703 | lwz r4,InstStorage@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1704 | mtspr IVOR3,r4 /* 3: Instruction storage */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1705 | lwz r4,ExtInterrupt@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1706 | mtspr IVOR4,r4 /* 4: External interrupt */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1707 | lwz r4,Alignment@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1708 | mtspr IVOR5,r4 /* 5: Alignment */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1709 | lwz r4,ProgramCheck@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1710 | mtspr IVOR6,r4 /* 6: Program check */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1711 | lwz r4,FPUnavailable@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1712 | mtspr IVOR7,r4 /* 7: floating point unavailable */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1713 | lwz r4,SystemCall@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1714 | mtspr IVOR8,r4 /* 8: System call */ |
Prabhakar Kushwaha | f838786 | 2012-02-14 22:49:49 +0000 | [diff] [blame] | 1715 | /* 9: Auxiliary processor unavailable(unsupported) */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1716 | lwz r4,Decrementer@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1717 | mtspr IVOR10,r4 /* 10: Decrementer */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1718 | lwz r4,IntervalTimer@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1719 | mtspr IVOR11,r4 /* 11: Interval timer */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1720 | lwz r4,WatchdogTimer@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1721 | mtspr IVOR12,r4 /* 12: Watchdog timer */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1722 | lwz r4,DataTLBError@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1723 | mtspr IVOR13,r4 /* 13: Data TLB error */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1724 | lwz r4,InstructionTLBError@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1725 | mtspr IVOR14,r4 /* 14: Instruction TLB error */ |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1726 | lwz r4,DebugBreakpoint@got(r12) |
Scott Wood | f21e758 | 2015-04-07 20:20:00 -0500 | [diff] [blame] | 1727 | mtspr IVOR15,r4 /* 15: Debug */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1728 | |
Scott Wood | c4dfbee | 2015-04-23 20:01:56 -0500 | [diff] [blame] | 1729 | mtlr r11 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1730 | blr |
| 1731 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1732 | .globl unlock_ram_in_cache |
| 1733 | unlock_ram_in_cache: |
| 1734 | /* invalidate the INIT_RAM section */ |
Kumar Gala | 5c953ca | 2008-10-23 01:47:37 -0500 | [diff] [blame] | 1735 | lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h |
| 1736 | ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l |
Kumar Gala | 938e14e | 2008-01-08 01:22:21 -0600 | [diff] [blame] | 1737 | mfspr r4,L1CFG0 |
| 1738 | andi. r4,r4,0x1ff |
| 1739 | slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 1740 | mtctr r4 |
Kumar Gala | 2a44121 | 2008-02-27 16:30:47 -0600 | [diff] [blame] | 1741 | 1: dcbi r0,r3 |
Ruchika Gupta | bba41d9 | 2017-03-02 14:12:41 +0530 | [diff] [blame] | 1742 | #ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */ |
York Sun | 8d45cc1 | 2015-08-17 13:31:52 -0700 | [diff] [blame] | 1743 | dcblc 2, r0, r3 |
Ruchika Gupta | bba41d9 | 2017-03-02 14:12:41 +0530 | [diff] [blame] | 1744 | dcblc 0, r0, r3 |
York Sun | 8d45cc1 | 2015-08-17 13:31:52 -0700 | [diff] [blame] | 1745 | #else |
York Sun | 52bf102 | 2013-04-05 13:07:13 +0000 | [diff] [blame] | 1746 | dcblc r0,r3 |
York Sun | 8d45cc1 | 2015-08-17 13:31:52 -0700 | [diff] [blame] | 1747 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 1748 | addi r3,r3,CONFIG_SYS_CACHELINE_SIZE |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1749 | bdnz 1b |
Kumar Gala | 2a44121 | 2008-02-27 16:30:47 -0600 | [diff] [blame] | 1750 | sync |
Andy Fleming | 5ba61fe | 2008-02-27 14:29:58 -0600 | [diff] [blame] | 1751 | |
| 1752 | /* Invalidate the TLB entries for the cache */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 1753 | lis r3,CONFIG_SYS_INIT_RAM_ADDR@h |
| 1754 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l |
Andy Fleming | 5ba61fe | 2008-02-27 14:29:58 -0600 | [diff] [blame] | 1755 | tlbivax 0,r3 |
| 1756 | addi r3,r3,0x1000 |
| 1757 | tlbivax 0,r3 |
| 1758 | addi r3,r3,0x1000 |
| 1759 | tlbivax 0,r3 |
| 1760 | addi r3,r3,0x1000 |
| 1761 | tlbivax 0,r3 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1762 | isync |
| 1763 | blr |
Kumar Gala | 32090b3 | 2008-09-22 14:11:10 -0500 | [diff] [blame] | 1764 | |
| 1765 | .globl flush_dcache |
| 1766 | flush_dcache: |
| 1767 | mfspr r3,SPRN_L1CFG0 |
| 1768 | |
| 1769 | rlwinm r5,r3,9,3 /* Extract cache block size */ |
| 1770 | twlgti r5,1 /* Only 32 and 64 byte cache blocks |
| 1771 | * are currently defined. |
| 1772 | */ |
| 1773 | li r4,32 |
| 1774 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - |
| 1775 | * log2(number of ways) |
| 1776 | */ |
| 1777 | slw r5,r4,r5 /* r5 = cache block size */ |
| 1778 | |
| 1779 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ |
| 1780 | mulli r7,r7,13 /* An 8-way cache will require 13 |
| 1781 | * loads per set. |
| 1782 | */ |
| 1783 | slw r7,r7,r6 |
| 1784 | |
| 1785 | /* save off HID0 and set DCFA */ |
| 1786 | mfspr r8,SPRN_HID0 |
| 1787 | ori r9,r8,HID0_DCFA@l |
| 1788 | mtspr SPRN_HID0,r9 |
| 1789 | isync |
| 1790 | |
| 1791 | lis r4,0 |
| 1792 | mtctr r7 |
| 1793 | |
| 1794 | 1: lwz r3,0(r4) /* Load... */ |
| 1795 | add r4,r4,r5 |
| 1796 | bdnz 1b |
| 1797 | |
| 1798 | msync |
| 1799 | lis r4,0 |
| 1800 | mtctr r7 |
| 1801 | |
| 1802 | 1: dcbf 0,r4 /* ...and flush. */ |
| 1803 | add r4,r4,r5 |
| 1804 | bdnz 1b |
| 1805 | |
| 1806 | /* restore HID0 */ |
| 1807 | mtspr SPRN_HID0,r8 |
| 1808 | isync |
| 1809 | |
| 1810 | blr |
Scott Wood | 7c81090 | 2012-09-20 16:35:21 -0500 | [diff] [blame] | 1811 | #endif /* !MINIMAL_SPL */ |