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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04002/*
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +00003 * Common configuration settings for IGEP technology based boards
4 *
5 * (C) Copyright 2012
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04006 * ISEE 2007 SL, <www.iseebcn.com>
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04007 */
8
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +00009#ifndef __IGEP00X0_H
10#define __IGEP00X0_H
11
Enric Balletbò i Serraed116482013-12-06 21:30:24 +010012#include <configs/ti_omap3_common.h>
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040013
Tom Rinicfff4aa2016-08-26 13:30:43 -040014/*
15 * We are only ever GP parts and will utilize all of the "downloaded image"
16 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
17 */
Enric Balletbo i Serra8aa10d42016-05-03 08:59:24 +020018
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040019#define CONFIG_REVISION_TAG 1
20
Pau Pajuelo4ddc3092017-08-17 03:09:14 +020021/* TPS65950 */
22#define PBIASLITEVMODE1 (1 << 8)
23
24/* LED */
25#define IGEP0020_GPIO_LED 27
26#define IGEP0030_GPIO_LED 16
27
28/* Board and revision detection GPIOs */
29#define IGEP0030_USB_TRANSCEIVER_RESET 54
30#define GPIO_IGEP00X0_BOARD_DETECTION 28
31#define GPIO_IGEP00X0_REVISION_DETECTION 129
Javier Martinez Canillasd549ace2012-12-27 03:36:01 +000032
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020033#ifndef CONFIG_SPL_BUILD
34
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020035/* Environment */
36#define ENV_DEVICE_SETTINGS \
37 "stdin=serial\0" \
38 "stdout=serial\0" \
39 "stderr=serial\0"
40
41#define MEM_LAYOUT_SETTINGS \
42 DEFAULT_LINUX_BOOT_ENV \
43 "scriptaddr=0x87E00000\0" \
44 "pxefile_addr_r=0x87F00000\0"
45
46#define BOOT_TARGET_DEVICES(func) \
47 func(MMC, mmc, 0)
48
49#include <config_distro_bootcmd.h>
50
Pau Pajuelo4ddc3092017-08-17 03:09:14 +020051#define ENV_FINDFDT \
52 "findfdt="\
53 "if test ${board_name} = igep0020; then " \
54 "if test ${board_rev} = F; then " \
55 "setenv fdtfile omap3-igep0020-rev-f.dtb; " \
56 "else " \
57 "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
58 "if test ${board_name} = igep0030; then " \
59 "if test ${board_rev} = G; then " \
60 "setenv fdtfile omap3-igep0030-rev-g.dtb; " \
61 "else " \
62 "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
63 "if test ${fdtfile} = ''; then " \
64 "echo WARNING: Could not determine device tree to use; fi; \0"
65
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040066#define CONFIG_EXTRA_ENV_SETTINGS \
Pau Pajuelo4ddc3092017-08-17 03:09:14 +020067 ENV_FINDFDT \
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020068 ENV_DEVICE_SETTINGS \
69 MEM_LAYOUT_SETTINGS \
70 BOOTENV
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -040071
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020072#endif
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040073
Ladislav Michlc44e29f2016-07-12 20:28:33 +020074#define CONFIG_SYS_MTDPARTS_RUNTIME
Javier Martinez Canillas361fc832012-07-28 01:19:34 +000075
Ladislav Michl43a60622016-07-12 20:28:32 +020076/* OneNAND config */
Ladislav Michl43a60622016-07-12 20:28:32 +020077#define CONFIG_USE_ONENAND_BOARD_INIT
78#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
79#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
Javier Martinez Canillas361fc832012-07-28 01:19:34 +000080
Ladislav Michl43a60622016-07-12 20:28:32 +020081/* NAND config */
Javier Martinez Canillas361fc832012-07-28 01:19:34 +000082#define CONFIG_SYS_NAND_5_ADDR_CYCLE
83#define CONFIG_SYS_NAND_PAGE_COUNT 64
84#define CONFIG_SYS_NAND_PAGE_SIZE 2048
85#define CONFIG_SYS_NAND_OOBSIZE 64
86#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +020087#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
88#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
89 10, 11, 12, 13, 14, 15, 16, 17, \
90 18, 19, 20, 21, 22, 23, 24, 25, \
91 26, 27, 28, 29, 30, 31, 32, 33, \
92 34, 35, 36, 37, 38, 39, 40, 41, \
93 42, 43, 44, 45, 46, 47, 48, 49, \
94 50, 51, 52, 53, 54, 55, 56, 57, }
Javier Martinez Canillas361fc832012-07-28 01:19:34 +000095#define CONFIG_SYS_NAND_ECCSIZE 512
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +020096#define CONFIG_SYS_NAND_ECCBYTES 14
97#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +020098
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +000099#endif /* __IGEP00X0_H */