Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 6558d278c6561e265fdb08b3b9566b67de46e15f / . / arch / arm / include / asm / arch-exynos / dmc.h
blob: f65c676cc590d301ed144266a206b77bb6ef8214 [file] [log] [blame]
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]1#ifndef __DMC_H__
2#define __DMC_H__
3
4#ifndef __ASSEMBLY__
Chander Kashyapecf95fa2012-03-02 03:25:34 +0000[diff] [blame]5struct exynos4_dmc {
6 unsigned int concontrol;
7 unsigned int memcontrol;
8 unsigned int memconfig0;
9 unsigned int memconfig1;
10 unsigned int directcmd;
11 unsigned int prechconfig;
12 unsigned int phycontrol0;
13 unsigned int phycontrol1;
14 unsigned int phycontrol2;
15 unsigned int phycontrol3;
16 unsigned int pwrdnconfig;
17 unsigned char res1[0x4];
18 unsigned int timingref;
19 unsigned int timingrow;
20 unsigned int timingdata;
21 unsigned int timingpower;
22 unsigned int phystatus;
23 unsigned int phyzqcontrol;
24 unsigned int chip0status;
25 unsigned int chip1status;
26 unsigned int arefstatus;
27 unsigned int mrstatus;
28 unsigned int phytest0;
29 unsigned int phytest1;
30 unsigned int qoscontrol0;
31 unsigned int qosconfig0;
32 unsigned int qoscontrol1;
33 unsigned int qosconfig1;
34 unsigned int qoscontrol2;
35 unsigned int qosconfig2;
36 unsigned int qoscontrol3;
37 unsigned int qosconfig3;
38 unsigned int qoscontrol4;
39 unsigned int qosconfig4;
40 unsigned int qoscontrol5;
41 unsigned int qosconfig5;
42 unsigned int qoscontrol6;
43 unsigned int qosconfig6;
44 unsigned int qoscontrol7;
45 unsigned int qosconfig7;
46 unsigned int qoscontrol8;
47 unsigned int qosconfig8;
48 unsigned int qoscontrol9;
49 unsigned int qosconfig9;
50 unsigned int qoscontrol10;
51 unsigned int qosconfig10;
52 unsigned int qoscontrol11;
53 unsigned int qosconfig11;
54 unsigned int qoscontrol12;
55 unsigned int qosconfig12;
56 unsigned int qoscontrol13;
57 unsigned int qosconfig13;
58 unsigned int qoscontrol14;
59 unsigned int qosconfig14;
60 unsigned int qoscontrol15;
61 unsigned int qosconfig15;
62 unsigned int qostimeout0;
63 unsigned int qostimeout1;
64 unsigned char res2[0x8];
65 unsigned int ivcontrol;
66 unsigned char res3[0x8];
67 unsigned int perevconfig;
68 unsigned char res4[0xDF00];
69 unsigned int pmnc_ppc_a;
70 unsigned char res5[0xC];
71 unsigned int cntens_ppc_a;
72 unsigned char res6[0xC];
73 unsigned int cntenc_ppc_a;
74 unsigned char res7[0xC];
75 unsigned int intens_ppc_a;
76 unsigned char res8[0xC];
77 unsigned int intenc_ppc_a;
78 unsigned char res9[0xC];
79 unsigned int flag_ppc_a;
80 unsigned char res10[0xAC];
81 unsigned int ccnt_ppc_a;
82 unsigned char res11[0xC];
83 unsigned int pmcnt0_ppc_a;
84 unsigned char res12[0xC];
85 unsigned int pmcnt1_ppc_a;
86 unsigned char res13[0xC];
87 unsigned int pmcnt2_ppc_a;
88 unsigned char res14[0xC];
89 unsigned int pmcnt3_ppc_a;
90 unsigned char res15[0xEBC];
91 unsigned int pmnc_ppc_m;
92 unsigned char res16[0xC];
93 unsigned int cntens_ppc_m;
94 unsigned char res17[0xC];
95 unsigned int cntenc_ppc_m;
96 unsigned char res18[0xC];
97 unsigned int intens_ppc_m;
98 unsigned char res19[0xC];
99 unsigned int intenc_ppc_m;
100 unsigned char res20[0xC];
101 unsigned int flag_ppc_m;
102 unsigned char res21[0xAC];
103 unsigned int ccnt_ppc_m;
104 unsigned char res22[0xC];
105 unsigned int pmcnt0_ppc_m;
106 unsigned char res23[0xC];
107 unsigned int pmcnt1_ppc_m;
108 unsigned char res24[0xC];
109 unsigned int pmcnt2_ppc_m;
110 unsigned char res25[0xC];
111 unsigned int pmcnt3_ppc_m;
112};
113
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]114struct exynos5_dmc {
115 unsigned int concontrol;
116 unsigned int memcontrol;
117 unsigned int memconfig0;
118 unsigned int memconfig1;
119 unsigned int directcmd;
120 unsigned int prechconfig;
121 unsigned int phycontrol0;
122 unsigned char res1[0xc];
123 unsigned int pwrdnconfig;
124 unsigned int timingpzq;
125 unsigned int timingref;
126 unsigned int timingrow;
127 unsigned int timingdata;
128 unsigned int timingpower;
129 unsigned int phystatus;
130 unsigned char res2[0x4];
131 unsigned int chipstatus_ch0;
132 unsigned int chipstatus_ch1;
133 unsigned char res3[0x4];
134 unsigned int mrstatus;
135 unsigned char res4[0x8];
136 unsigned int qoscontrol0;
137 unsigned char resr5[0x4];
138 unsigned int qoscontrol1;
139 unsigned char res6[0x4];
140 unsigned int qoscontrol2;
141 unsigned char res7[0x4];
142 unsigned int qoscontrol3;
143 unsigned char res8[0x4];
144 unsigned int qoscontrol4;
145 unsigned char res9[0x4];
146 unsigned int qoscontrol5;
147 unsigned char res10[0x4];
148 unsigned int qoscontrol6;
149 unsigned char res11[0x4];
150 unsigned int qoscontrol7;
151 unsigned char res12[0x4];
152 unsigned int qoscontrol8;
153 unsigned char res13[0x4];
154 unsigned int qoscontrol9;
155 unsigned char res14[0x4];
156 unsigned int qoscontrol10;
157 unsigned char res15[0x4];
158 unsigned int qoscontrol11;
159 unsigned char res16[0x4];
160 unsigned int qoscontrol12;
161 unsigned char res17[0x4];
162 unsigned int qoscontrol13;
163 unsigned char res18[0x4];
164 unsigned int qoscontrol14;
165 unsigned char res19[0x4];
166 unsigned int qoscontrol15;
167 unsigned char res20[0x14];
168 unsigned int ivcontrol;
169 unsigned int wrtra_config;
170 unsigned int rdlvl_config;
171 unsigned char res21[0x8];
172 unsigned int brbrsvconfig;
173 unsigned int brbqosconfig;
174 unsigned int membaseconfig0;
175 unsigned int membaseconfig1;
176 unsigned char res22[0xc];
177 unsigned int wrlvl_config;
178 unsigned char res23[0xc];
179 unsigned int perevcontrol;
180 unsigned int perev0config;
181 unsigned int perev1config;
182 unsigned int perev2config;
183 unsigned int perev3config;
184 unsigned char res24[0xdebc];
185 unsigned int pmnc_ppc_a;
186 unsigned char res25[0xc];
187 unsigned int cntens_ppc_a;
188 unsigned char res26[0xc];
189 unsigned int cntenc_ppc_a;
190 unsigned char res27[0xc];
191 unsigned int intens_ppc_a;
192 unsigned char res28[0xc];
193 unsigned int intenc_ppc_a;
194 unsigned char res29[0xc];
195 unsigned int flag_ppc_a;
196 unsigned char res30[0xac];
197 unsigned int ccnt_ppc_a;
198 unsigned char res31[0xc];
199 unsigned int pmcnt0_ppc_a;
200 unsigned char res32[0xc];
201 unsigned int pmcnt1_ppc_a;
202 unsigned char res33[0xc];
203 unsigned int pmcnt2_ppc_a;
204 unsigned char res34[0xc];
205 unsigned int pmcnt3_ppc_a;
206};
207
208struct exynos5_phy_control {
209 unsigned int phy_con0;
210 unsigned int phy_con1;
211 unsigned int phy_con2;
212 unsigned int phy_con3;
213 unsigned int phy_con4;
214 unsigned char res1[4];
215 unsigned int phy_con6;
216 unsigned char res2[4];
217 unsigned int phy_con8;
218 unsigned int phy_con9;
219 unsigned int phy_con10;
220 unsigned char res3[4];
221 unsigned int phy_con12;
222 unsigned int phy_con13;
223 unsigned int phy_con14;
224 unsigned int phy_con15;
225 unsigned int phy_con16;
226 unsigned char res4[4];
227 unsigned int phy_con17;
228 unsigned int phy_con18;
229 unsigned int phy_con19;
230 unsigned int phy_con20;
231 unsigned int phy_con21;
232 unsigned int phy_con22;
233 unsigned int phy_con23;
234 unsigned int phy_con24;
235 unsigned int phy_con25;
236 unsigned int phy_con26;
237 unsigned int phy_con27;
238 unsigned int phy_con28;
239 unsigned int phy_con29;
240 unsigned int phy_con30;
241 unsigned int phy_con31;
242 unsigned int phy_con32;
243 unsigned int phy_con33;
244 unsigned int phy_con34;
245 unsigned int phy_con35;
246 unsigned int phy_con36;
247 unsigned int phy_con37;
248 unsigned int phy_con38;
249 unsigned int phy_con39;
250 unsigned int phy_con40;
251 unsigned int phy_con41;
252 unsigned int phy_con42;
253};
Rajeshwari Shinde6558d272012-07-03 20:02:56 +0000[diff] [blame^]254
255enum ddr_mode {
256 DDR_MODE_DDR2,
257 DDR_MODE_DDR3,
258 DDR_MODE_LPDDR2,
259 DDR_MODE_LPDDR3,
260
261 DDR_MODE_COUNT,
262};
263
264enum mem_manuf {
265 MEM_MANUF_AUTODETECT,
266 MEM_MANUF_ELPIDA,
267 MEM_MANUF_SAMSUNG,
268
269 MEM_MANUF_COUNT,
270};
271
272/* CONCONTROL register fields */
273#define CONCONTROL_DFI_INIT_START_SHIFT 28
274#define CONCONTROL_RD_FETCH_SHIFT 12
275#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
276#define CONCONTROL_AREF_EN_SHIFT 5
277
278/* PRECHCONFIG register field */
279#define PRECHCONFIG_TP_CNT_SHIFT 24
280
281/* PWRDNCONFIG register field */
282#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
283#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
284
285/* PHY_CON0 register fields */
286#define PHY_CON0_T_WRRDCMD_SHIFT 17
287#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
288#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
289
290/* PHY_CON1 register fields */
291#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
292
293/* PHY_CON12 register fields */
294#define PHY_CON12_CTRL_START_POINT_SHIFT 24
295#define PHY_CON12_CTRL_INC_SHIFT 16
296#define PHY_CON12_CTRL_FORCE_SHIFT 8
297#define PHY_CON12_CTRL_START_SHIFT 6
298#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
299#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
300#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
301#define PHY_CON12_CTRL_REF_SHIFT 1
302
303/* PHY_CON16 register fields */
304#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
305#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
306
307#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
308#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
309
310#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
311
312/* PHY_CON42 register fields */
313#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
314#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
315
316#define PHY_CON42_CTRL_RDLAT_SHIFT 0
317#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
318
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]319#endif
320#endif