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Chander Kashyap34076a02012-02-05 23:01:46 +00001#ifndef __DMC_H__
2#define __DMC_H__
3
4#ifndef __ASSEMBLY__
5struct exynos5_dmc {
6 unsigned int concontrol;
7 unsigned int memcontrol;
8 unsigned int memconfig0;
9 unsigned int memconfig1;
10 unsigned int directcmd;
11 unsigned int prechconfig;
12 unsigned int phycontrol0;
13 unsigned char res1[0xc];
14 unsigned int pwrdnconfig;
15 unsigned int timingpzq;
16 unsigned int timingref;
17 unsigned int timingrow;
18 unsigned int timingdata;
19 unsigned int timingpower;
20 unsigned int phystatus;
21 unsigned char res2[0x4];
22 unsigned int chipstatus_ch0;
23 unsigned int chipstatus_ch1;
24 unsigned char res3[0x4];
25 unsigned int mrstatus;
26 unsigned char res4[0x8];
27 unsigned int qoscontrol0;
28 unsigned char resr5[0x4];
29 unsigned int qoscontrol1;
30 unsigned char res6[0x4];
31 unsigned int qoscontrol2;
32 unsigned char res7[0x4];
33 unsigned int qoscontrol3;
34 unsigned char res8[0x4];
35 unsigned int qoscontrol4;
36 unsigned char res9[0x4];
37 unsigned int qoscontrol5;
38 unsigned char res10[0x4];
39 unsigned int qoscontrol6;
40 unsigned char res11[0x4];
41 unsigned int qoscontrol7;
42 unsigned char res12[0x4];
43 unsigned int qoscontrol8;
44 unsigned char res13[0x4];
45 unsigned int qoscontrol9;
46 unsigned char res14[0x4];
47 unsigned int qoscontrol10;
48 unsigned char res15[0x4];
49 unsigned int qoscontrol11;
50 unsigned char res16[0x4];
51 unsigned int qoscontrol12;
52 unsigned char res17[0x4];
53 unsigned int qoscontrol13;
54 unsigned char res18[0x4];
55 unsigned int qoscontrol14;
56 unsigned char res19[0x4];
57 unsigned int qoscontrol15;
58 unsigned char res20[0x14];
59 unsigned int ivcontrol;
60 unsigned int wrtra_config;
61 unsigned int rdlvl_config;
62 unsigned char res21[0x8];
63 unsigned int brbrsvconfig;
64 unsigned int brbqosconfig;
65 unsigned int membaseconfig0;
66 unsigned int membaseconfig1;
67 unsigned char res22[0xc];
68 unsigned int wrlvl_config;
69 unsigned char res23[0xc];
70 unsigned int perevcontrol;
71 unsigned int perev0config;
72 unsigned int perev1config;
73 unsigned int perev2config;
74 unsigned int perev3config;
75 unsigned char res24[0xdebc];
76 unsigned int pmnc_ppc_a;
77 unsigned char res25[0xc];
78 unsigned int cntens_ppc_a;
79 unsigned char res26[0xc];
80 unsigned int cntenc_ppc_a;
81 unsigned char res27[0xc];
82 unsigned int intens_ppc_a;
83 unsigned char res28[0xc];
84 unsigned int intenc_ppc_a;
85 unsigned char res29[0xc];
86 unsigned int flag_ppc_a;
87 unsigned char res30[0xac];
88 unsigned int ccnt_ppc_a;
89 unsigned char res31[0xc];
90 unsigned int pmcnt0_ppc_a;
91 unsigned char res32[0xc];
92 unsigned int pmcnt1_ppc_a;
93 unsigned char res33[0xc];
94 unsigned int pmcnt2_ppc_a;
95 unsigned char res34[0xc];
96 unsigned int pmcnt3_ppc_a;
97};
98
99struct exynos5_phy_control {
100 unsigned int phy_con0;
101 unsigned int phy_con1;
102 unsigned int phy_con2;
103 unsigned int phy_con3;
104 unsigned int phy_con4;
105 unsigned char res1[4];
106 unsigned int phy_con6;
107 unsigned char res2[4];
108 unsigned int phy_con8;
109 unsigned int phy_con9;
110 unsigned int phy_con10;
111 unsigned char res3[4];
112 unsigned int phy_con12;
113 unsigned int phy_con13;
114 unsigned int phy_con14;
115 unsigned int phy_con15;
116 unsigned int phy_con16;
117 unsigned char res4[4];
118 unsigned int phy_con17;
119 unsigned int phy_con18;
120 unsigned int phy_con19;
121 unsigned int phy_con20;
122 unsigned int phy_con21;
123 unsigned int phy_con22;
124 unsigned int phy_con23;
125 unsigned int phy_con24;
126 unsigned int phy_con25;
127 unsigned int phy_con26;
128 unsigned int phy_con27;
129 unsigned int phy_con28;
130 unsigned int phy_con29;
131 unsigned int phy_con30;
132 unsigned int phy_con31;
133 unsigned int phy_con32;
134 unsigned int phy_con33;
135 unsigned int phy_con34;
136 unsigned int phy_con35;
137 unsigned int phy_con36;
138 unsigned int phy_con37;
139 unsigned int phy_con38;
140 unsigned int phy_con39;
141 unsigned int phy_con40;
142 unsigned int phy_con41;
143 unsigned int phy_con42;
144};
145#endif
146#endif