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Dinh Nguyenad51f7c2012-10-04 06:46:02 +00001/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00005 */
6
7#include <common.h>
8#include <asm/io.h>
Pavel Machekce340e92014-07-14 14:14:17 +02009#include <miiphy.h>
10#include <netdev.h>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +000011
12DECLARE_GLOBAL_DATA_PTR;
13
Dinh Nguyenad51f7c2012-10-04 06:46:02 +000014int dram_init(void)
15{
16 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
17 return 0;
18}
Chin Liang Seebff262c2014-06-10 02:23:45 -050019
20#if defined(CONFIG_DISPLAY_CPUINFO)
21/*
22 * Print CPU information
23 */
24int print_cpuinfo(void)
25{
26 puts("CPU : Altera SOCFPGA Platform\n");
27 return 0;
28}
29#endif
30
31#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
32defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
33int overwrite_console(void)
34{
35 return 0;
36}
37#endif
38
39int misc_init_r(void)
40{
41 return 0;
42}
Pavel Machekce340e92014-07-14 14:14:17 +020043
44
45/*
46 * DesignWare Ethernet initialization
47 */
48int cpu_eth_init(bd_t *bis)
49{
50#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
51 /* initialize and register the emac */
52 return designware_initialize(CONFIG_EMAC_BASE,
53 CONFIG_PHY_INTERFACE_MODE);
54#else
55 return 0;
56#endif
57}