Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
Pavel Machek | ce340e9 | 2014-07-14 14:14:17 +0200 | [diff] [blame] | 9 | #include <miiphy.h> |
| 10 | #include <netdev.h> |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 11 | |
| 12 | DECLARE_GLOBAL_DATA_PTR; |
| 13 | |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 14 | int dram_init(void) |
| 15 | { |
| 16 | gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); |
| 17 | return 0; |
| 18 | } |
Chin Liang See | bff262c | 2014-06-10 02:23:45 -0500 | [diff] [blame] | 19 | |
| 20 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 21 | /* |
| 22 | * Print CPU information |
| 23 | */ |
| 24 | int print_cpuinfo(void) |
| 25 | { |
| 26 | puts("CPU : Altera SOCFPGA Platform\n"); |
| 27 | return 0; |
| 28 | } |
| 29 | #endif |
| 30 | |
| 31 | #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ |
| 32 | defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) |
| 33 | int overwrite_console(void) |
| 34 | { |
| 35 | return 0; |
| 36 | } |
| 37 | #endif |
| 38 | |
| 39 | int misc_init_r(void) |
| 40 | { |
| 41 | return 0; |
| 42 | } |
Pavel Machek | ce340e9 | 2014-07-14 14:14:17 +0200 | [diff] [blame] | 43 | |
| 44 | |
| 45 | /* |
| 46 | * DesignWare Ethernet initialization |
| 47 | */ |
| 48 | int cpu_eth_init(bd_t *bis) |
| 49 | { |
| 50 | #if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD) |
| 51 | /* initialize and register the emac */ |
| 52 | return designware_initialize(CONFIG_EMAC_BASE, |
| 53 | CONFIG_PHY_INTERFACE_MODE); |
| 54 | #else |
| 55 | return 0; |
| 56 | #endif |
| 57 | } |