Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_TARGET_LS1046AQDS=y |
Tom Rini | 2c7a8d4 | 2019-08-14 08:11:27 -0400 | [diff] [blame] | 3 | CONFIG_TFABOOT=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 4 | CONFIG_SYS_TEXT_BASE=0x82000000 |
Tom Rini | e25a03a | 2021-11-01 12:19:22 +0000 | [diff] [blame] | 5 | CONFIG_SYS_MALLOC_LEN=0x102000 |
Tom Rini | 2e262c4 | 2020-08-10 15:31:07 -0400 | [diff] [blame] | 6 | CONFIG_NR_DRAM_BANKS=2 |
Tom Rini | 56fd1e1 | 2020-11-30 12:50:32 -0500 | [diff] [blame] | 7 | CONFIG_SYS_MEMTEST_START=0x80000000 |
| 8 | CONFIG_SYS_MEMTEST_END=0x9fffffff |
Tom Rini | 5cd7ece | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 9 | CONFIG_ENV_SIZE=0x2000 |
Tom Rini | 47dece3 | 2020-04-28 16:15:47 -0400 | [diff] [blame] | 10 | CONFIG_NXP_ESBC=y |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 11 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C4=y |
Tom Rini | 47dece3 | 2020-04-28 16:15:47 -0400 | [diff] [blame] | 15 | CONFIG_DM_GPIO=y |
Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 16 | CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" |
Tom Rini | 2c082ab | 2021-07-26 21:10:37 -0400 | [diff] [blame] | 17 | CONFIG_FSL_USE_PCA9547_MUX=y |
Tom Rini | 929ea65 | 2019-01-07 17:46:19 -0500 | [diff] [blame] | 18 | CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y |
| 19 | CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y |
| 20 | CONFIG_AHCI=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 21 | CONFIG_DISTRO_DEFAULTS=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 22 | CONFIG_FIT_VERBOSE=y |
| 23 | CONFIG_OF_BOARD_SETUP=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 24 | CONFIG_BOOTDELAY=10 |
| 25 | CONFIG_USE_BOOTARGS=y |
| 26 | CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" |
| 27 | # CONFIG_USE_BOOTCOMMAND is not set |
| 28 | CONFIG_MISC_INIT_R=y |
| 29 | CONFIG_CMD_BOOTZ=y |
| 30 | CONFIG_CMD_IMLS=y |
| 31 | CONFIG_CMD_GREPENV=y |
Tom Rini | faed567 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 32 | CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 33 | CONFIG_CMD_MEMINFO=y |
| 34 | CONFIG_CMD_MEMTEST=y |
Biwen Li | 2ffefc3 | 2021-02-05 19:02:13 +0800 | [diff] [blame] | 35 | CONFIG_CMD_GPIO=y |
Tom Rini | 3c0d7a2 | 2021-02-15 13:34:30 -0500 | [diff] [blame] | 36 | CONFIG_CMD_GPT=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 37 | CONFIG_CMD_I2C=y |
| 38 | CONFIG_CMD_MMC=y |
| 39 | CONFIG_CMD_NAND=y |
| 40 | CONFIG_CMD_PCI=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 41 | CONFIG_CMD_USB=y |
| 42 | CONFIG_CMD_CACHE=y |
| 43 | CONFIG_MP=y |
| 44 | CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" |
| 45 | CONFIG_OF_CONTROL=y |
Kuldeep Singh | 248a293 | 2020-07-30 15:38:07 +0530 | [diff] [blame] | 46 | CONFIG_ENV_OVERWRITE=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 47 | CONFIG_DM=y |
Tom Rini | 929ea65 | 2019-01-07 17:46:19 -0500 | [diff] [blame] | 48 | CONFIG_SATA_CEVA=y |
Tom Rini | f7246c2 | 2021-08-21 13:50:17 -0400 | [diff] [blame] | 49 | CONFIG_DYNAMIC_DDR_CLK_FREQ=y |
Tom Rini | 468c2d5 | 2021-08-21 13:50:18 -0400 | [diff] [blame] | 50 | CONFIG_DDR_ECC=y |
| 51 | CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y |
Tom Rini | 47dece3 | 2020-04-28 16:15:47 -0400 | [diff] [blame] | 52 | CONFIG_DM_I2C=y |
Tom Rini | 714482a | 2021-08-18 23:12:25 -0400 | [diff] [blame] | 53 | CONFIG_SYS_I2C_EARLY_INIT=y |
Tom Rini | b1b1307 | 2021-08-18 23:12:37 -0400 | [diff] [blame] | 54 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
Tom Rini | faed567 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 55 | CONFIG_SYS_I2C_EEPROM_ADDR=0x57 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 56 | CONFIG_FSL_ESDHC=y |
Tom Rini | e799f92 | 2019-12-04 17:18:38 -0500 | [diff] [blame] | 57 | CONFIG_MTD=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 58 | CONFIG_MTD_NOR_FLASH=y |
| 59 | CONFIG_FLASH_CFI_DRIVER=y |
| 60 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y |
| 61 | CONFIG_SYS_FLASH_CFI=y |
Tom Rini | e799f92 | 2019-12-04 17:18:38 -0500 | [diff] [blame] | 62 | CONFIG_MTD_RAW_NAND=y |
Tom Rini | a73788c | 2021-09-22 14:50:37 -0400 | [diff] [blame] | 63 | CONFIG_NAND_FSL_IFC=y |
Tom Rini | fdae007 | 2021-09-22 14:50:34 -0400 | [diff] [blame] | 64 | CONFIG_SYS_NAND_ONFI_DETECTION=y |
Patrick Delaunay | 0df8104 | 2019-02-27 15:20:36 +0100 | [diff] [blame] | 65 | CONFIG_SF_DEFAULT_BUS=1 |
Kuldeep Singh | 6301280 | 2021-11-09 14:52:26 +0530 | [diff] [blame^] | 66 | CONFIG_SPI_FLASH_EON=y |
Kuldeep Singh | 1c481a8 | 2020-05-12 14:32:39 +0530 | [diff] [blame] | 67 | CONFIG_SPI_FLASH_SPANSION=y |
Kuldeep Singh | 6301280 | 2021-11-09 14:52:26 +0530 | [diff] [blame^] | 68 | CONFIG_SPI_FLASH_STMICRO=y |
| 69 | CONFIG_SPI_FLASH_SST=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 70 | CONFIG_PHYLIB=y |
Tom Rini | 5d15419 | 2020-04-24 15:35:53 -0400 | [diff] [blame] | 71 | CONFIG_PHYLIB_10G=y |
| 72 | CONFIG_PHY_REALTEK=y |
| 73 | CONFIG_PHY_VITESSE=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 74 | CONFIG_E1000=y |
Tom Rini | fa911f8 | 2019-05-12 07:59:12 -0400 | [diff] [blame] | 75 | CONFIG_FMAN_ENET=y |
Tom Rini | fa94316 | 2020-10-29 10:48:01 -0400 | [diff] [blame] | 76 | CONFIG_NVME=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 77 | CONFIG_PCI=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 78 | CONFIG_DM_PCI_COMPAT=y |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 79 | CONFIG_PCIE_LAYERSCAPE_RC=y |
| 80 | CONFIG_PCIE_LAYERSCAPE_EP=y |
Tom Rini | 929ea65 | 2019-01-07 17:46:19 -0500 | [diff] [blame] | 81 | CONFIG_DM_SCSI=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 82 | CONFIG_SYS_NS16550=y |
| 83 | CONFIG_SPI=y |
| 84 | CONFIG_DM_SPI=y |
| 85 | CONFIG_FSL_DSPI=y |
| 86 | CONFIG_USB=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 87 | CONFIG_USB_XHCI_HCD=y |
| 88 | CONFIG_USB_XHCI_DWC3=y |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 89 | CONFIG_RSA=y |