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git01.mediatek.com / filogic / uboot / 622b7b3dea4f178b923bcc1340346dfc3c8b8064 / . / board / nvidia / seaboard / seaboard.c
blob: 0d5eec9dd82dafcd85bb980c872113c3e80304dd [file] [log] [blame]
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]1/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]6 */
7
8#include <common.h>
9#include <asm/io.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]10#include <asm/mach-types.h>
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]11#include <asm/arch/tegra.h>
Jeroen Hofstee93dfae72014-10-08 22:57:46 +0200[diff] [blame]12#include <asm/arch-tegra/board.h>
Simon Glassea160b12012-01-11 12:42:28 +0000[diff] [blame]13#include <asm/arch/clock.h>
14#include <asm/arch/funcmux.h>
Stephen Warren63315d92012-10-22 06:19:36 +0000[diff] [blame]15#include <asm/arch/gpio.h>
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]16#include <asm/arch/pinmux.h>
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]17#include <asm/gpio.h>
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]18
Simon Glass704e60d2011-11-05 04:46:51 +0000[diff] [blame]19/* TODO: Remove this code when the SPI switch is working */
Allen Martine0158b82013-03-16 18:58:02 +0000[diff] [blame]20#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
Stephen Warren63315d92012-10-22 06:19:36 +0000[diff] [blame]21void gpio_early_init_uart(void)
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]22{
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]23 /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
Stephen Warren7f20bb22016-05-12 12:07:39 -0600[diff] [blame]24 gpio_request(TEGRA_GPIO(I, 3), "uart_en");
25 gpio_direction_output(TEGRA_GPIO(I, 3), 0);
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]26}
Simon Glass704e60d2011-11-05 04:46:51 +0000[diff] [blame]27#endif
Stephen Warrenffac82e2011-10-31 06:51:37 +0000[diff] [blame]28
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900[diff] [blame]29#ifdef CONFIG_MMC_SDHCI_TEGRA
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]30/*
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]31 * Routine: pin_mux_mmc
32 * Description: setup the pin muxes/tristate values for the SDMMC(s)
33 */
Tom Warren9745cf82013-02-21 12:31:30 +0000[diff] [blame]34void pin_mux_mmc(void)
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]35{
Simon Glassea160b12012-01-11 12:42:28 +0000[diff] [blame]36 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
37 funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]38
39 /* For power GPIO PI6 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]40 pinmux_tristate_disable(PMUX_PINGRP_ATA);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]41 /* For CD GPIO PI5 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]42 pinmux_tristate_disable(PMUX_PINGRP_ATC);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]43}
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]44#endif
Simon Glass5d73a8d2012-02-27 10:52:50 +0000[diff] [blame]45
46void pin_mux_usb(void)
47{
Stephen Warrenf0231872016-09-15 12:19:39 -0600[diff] [blame]48 /* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]49 pinmux_tristate_disable(PMUX_PINGRP_SLXK);
Stephen Warrenf0231872016-09-15 12:19:39 -0600[diff] [blame]50 /* For USB1's ULPI signals */
51 funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
52 pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
53 pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
54 /* USB1 PHY reset GPIO */
55 pinmux_tristate_disable(PMUX_PINGRP_UAC);
Simon Glass5d73a8d2012-02-27 10:52:50 +0000[diff] [blame]56}