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huang lin1115b642015-11-17 14:20:27 +08001/*
2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#ifndef __CONFIG_RK3036_COMMON_H
7#define __CONFIG_RK3036_COMMON_H
8
Xu Ziyuane71ce522016-07-28 11:42:34 +08009#define CONFIG_SYS_CACHELINE_SIZE 64
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +010010
huang lin1115b642015-11-17 14:20:27 +080011#include <asm/arch/hardware.h>
12
13#define CONFIG_SYS_NO_FLASH
14#define CONFIG_NR_DRAM_BANKS 1
15#define CONFIG_ENV_IS_NOWHERE
16#define CONFIG_ENV_SIZE 0x2000
17#define CONFIG_SYS_MAXARGS 16
18#define CONFIG_BAUDRATE 115200
19#define CONFIG_SYS_MALLOC_LEN (32 << 20)
20#define CONFIG_SYS_CBSIZE 1024
21#define CONFIG_SKIP_LOWLEVEL_INIT
22#define CONFIG_SYS_THUMB_BUILD
23#define CONFIG_DISPLAY_BOARDINFO
24
25#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
26#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
27#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
28
Simon Glasse0f177b2015-12-13 21:37:00 -070029#define CONFIG_SPL_SERIAL_SUPPORT
30
huang lin1115b642015-11-17 14:20:27 +080031#define CONFIG_SYS_NS16550
32#define CONFIG_SYS_NS16550_MEM32
33
huang lin1115b642015-11-17 14:20:27 +080034#define CONFIG_SYS_TEXT_BASE 0x60000000
35#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
36#define CONFIG_SYS_LOAD_ADDR 0x60800800
37#define CONFIG_SPL_STACK 0x10081fff
38#define CONFIG_SPL_TEXT_BASE 0x10081004
39
40#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
41#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
42
huang lin1115b642015-11-17 14:20:27 +080043/* MMC/SD IP block */
44#define CONFIG_MMC
45#define CONFIG_GENERIC_MMC
huang lin1115b642015-11-17 14:20:27 +080046#define CONFIG_DWMMC
47#define CONFIG_BOUNCE_BUFFER
48
huang lin1115b642015-11-17 14:20:27 +080049#define CONFIG_FAT_WRITE
huang lin1115b642015-11-17 14:20:27 +080050#define CONFIG_PARTITION_UUIDS
51#define CONFIG_CMD_PART
52
huang lin1115b642015-11-17 14:20:27 +080053#define CONFIG_SYS_SDRAM_BASE 0x60000000
54#define CONFIG_NR_DRAM_BANKS 1
55#define SDRAM_BANK_SIZE (512UL << 20UL)
56
57#define CONFIG_SPI_FLASH
58#define CONFIG_SPI
huang lin1115b642015-11-17 14:20:27 +080059#define CONFIG_SPI_FLASH_GIGADEVICE
60#define CONFIG_SF_DEFAULT_SPEED 20000000
61
huang lin1115b642015-11-17 14:20:27 +080062#ifndef CONFIG_SPL_BUILD
Xu Ziyuane71ce522016-07-28 11:42:34 +080063/* usb otg */
64#define CONFIG_USB_GADGET
65#define CONFIG_USB_GADGET_DUALSPEED
66#define CONFIG_USB_GADGET_DWC2_OTG
67#define CONFIG_USB_GADGET_VBUS_DRAW 0
68
69/* fastboot */
70#define CONFIG_CMD_FASTBOOT
71#define CONFIG_USB_FUNCTION_FASTBOOT
72#define CONFIG_FASTBOOT_FLASH
73#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
74#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
75#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
76
77#define CONFIG_USB_GADGET_DOWNLOAD
78#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
79#define CONFIG_G_DNL_VENDOR_NUM 0x2207
80#define CONFIG_G_DNL_PRODUCT_NUM 0x310a
81
huang lin1115b642015-11-17 14:20:27 +080082#include <config_distro_defaults.h>
83
84#define ENV_MEM_LAYOUT_SETTINGS \
85 "scriptaddr=0x60000000\0" \
86 "pxefile_addr_r=0x60100000\0" \
87 "fdt_addr_r=0x61f00000\0" \
88 "kernel_addr_r=0x62000000\0" \
89 "ramdisk_addr_r=0x64000000\0"
90
91/* First try to boot from SD (index 0), then eMMC (index 1 */
92#define BOOT_TARGET_DEVICES(func) \
93 func(MMC, mmc, 0) \
94 func(MMC, mmc, 1)
95
96#include <config_distro_bootcmd.h>
97
98/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
99 * so limit the fdt reallocation to that */
100#define CONFIG_EXTRA_ENV_SETTINGS \
101 "fdt_high=0x7fffffff\0" \
102 ENV_MEM_LAYOUT_SETTINGS \
103 BOOTENV
104#endif
105
106#endif