Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 1 | /* |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 2 | * Copyright (C) 2014 Panasonic Corporation |
| 3 | * Copyright (C) 2015-2016 Socionext Inc. |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
Masahiro Yamada | 609cd53 | 2017-10-13 19:21:55 +0900 | [diff] [blame^] | 8 | #include <linux/bitops.h> |
Masahiro Yamada | e4e789d | 2017-01-21 18:05:24 +0900 | [diff] [blame] | 9 | #include <linux/errno.h> |
Masahiro Yamada | 663a23f | 2015-05-29 17:30:00 +0900 | [diff] [blame] | 10 | #include <linux/io.h> |
Masahiro Yamada | 609cd53 | 2017-10-13 19:21:55 +0900 | [diff] [blame^] | 11 | #include <linux/printk.h> |
Masahiro Yamada | efdf340 | 2016-01-09 01:51:13 +0900 | [diff] [blame] | 12 | |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 13 | #include "ddrphy-init.h" |
Masahiro Yamada | efdf340 | 2016-01-09 01:51:13 +0900 | [diff] [blame] | 14 | #include "ddrphy-regs.h" |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 15 | |
Masahiro Yamada | a1e2422 | 2016-02-26 14:21:43 +0900 | [diff] [blame] | 16 | enum dram_freq { |
| 17 | DRAM_FREQ_1333M, |
| 18 | DRAM_FREQ_1600M, |
| 19 | DRAM_FREQ_NR, |
| 20 | }; |
| 21 | |
| 22 | static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04}; |
| 23 | static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E}; |
| 24 | static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80}; |
| 25 | static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100}; |
| 26 | static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66}; |
| 27 | static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400}; |
| 28 | static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8}; |
| 29 | static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71}; |
| 30 | static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298}; |
| 31 | |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 32 | int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 33 | { |
Masahiro Yamada | a1e2422 | 2016-02-26 14:21:43 +0900 | [diff] [blame] | 34 | enum dram_freq freq_e; |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 35 | u32 tmp; |
| 36 | |
Masahiro Yamada | a1e2422 | 2016-02-26 14:21:43 +0900 | [diff] [blame] | 37 | switch (freq) { |
| 38 | case 1333: |
| 39 | freq_e = DRAM_FREQ_1333M; |
| 40 | break; |
| 41 | case 1600: |
| 42 | freq_e = DRAM_FREQ_1600M; |
| 43 | break; |
| 44 | default: |
Masahiro Yamada | 609cd53 | 2017-10-13 19:21:55 +0900 | [diff] [blame^] | 45 | pr_err("unsupported DRAM frequency %d MHz\n", freq); |
Masahiro Yamada | a1e2422 | 2016-02-26 14:21:43 +0900 | [diff] [blame] | 46 | return -EINVAL; |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 47 | } |
Masahiro Yamada | a1e2422 | 2016-02-26 14:21:43 +0900 | [diff] [blame] | 48 | |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 49 | writel(0x0300c473, phy_base + PHY_PGCR1); |
| 50 | writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); |
| 51 | writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); |
| 52 | writel(0x00083DEF, phy_base + PHY_PTR2); |
| 53 | writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); |
| 54 | writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); |
| 55 | writel(0xF004001A, phy_base + PHY_DSGCR); |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 56 | |
| 57 | /* change the value of the on-die pull-up/pull-down registors */ |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 58 | tmp = readl(phy_base + PHY_DXCCR); |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 59 | tmp &= ~0x0ee0; |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 60 | tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM; |
| 61 | writel(tmp, phy_base + PHY_DXCCR); |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 62 | |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 63 | writel(0x0000040B, phy_base + PHY_DCR); |
| 64 | writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0); |
| 65 | writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1); |
| 66 | writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2); |
| 67 | writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0); |
| 68 | writel(0x00000006, phy_base + PHY_MR1); |
| 69 | writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2); |
| 70 | writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3); |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 71 | |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 72 | while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 73 | ; |
| 74 | |
Masahiro Yamada | b464ff9 | 2016-10-27 23:47:07 +0900 | [diff] [blame] | 75 | writel(0x0300C473, phy_base + PHY_PGCR1); |
| 76 | writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1); |
Masahiro Yamada | 75f16f8 | 2015-09-22 00:27:39 +0900 | [diff] [blame] | 77 | |
| 78 | return 0; |
Masahiro Yamada | 04191e5 | 2014-12-19 20:20:52 +0900 | [diff] [blame] | 79 | } |