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Masahiro Yamada04191e52014-12-19 20:20:52 +09001/*
Masahiro Yamadab464ff92016-10-27 23:47:07 +09002 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
Masahiro Yamada04191e52014-12-19 20:20:52 +09004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
Masahiro Yamada609cd532017-10-13 19:21:55 +09008#include <linux/bitops.h>
Masahiro Yamadae4e789d2017-01-21 18:05:24 +09009#include <linux/errno.h>
Masahiro Yamada663a23f2015-05-29 17:30:00 +090010#include <linux/io.h>
Masahiro Yamada609cd532017-10-13 19:21:55 +090011#include <linux/printk.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +090012
Masahiro Yamadab464ff92016-10-27 23:47:07 +090013#include "ddrphy-init.h"
Masahiro Yamadaefdf3402016-01-09 01:51:13 +090014#include "ddrphy-regs.h"
Masahiro Yamada04191e52014-12-19 20:20:52 +090015
Masahiro Yamadaa1e24222016-02-26 14:21:43 +090016enum dram_freq {
17 DRAM_FREQ_1333M,
18 DRAM_FREQ_1600M,
19 DRAM_FREQ_NR,
20};
21
22static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
23static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
24static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
25static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
26static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
27static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
28static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
29static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
30static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
31
Masahiro Yamadab464ff92016-10-27 23:47:07 +090032int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
Masahiro Yamada04191e52014-12-19 20:20:52 +090033{
Masahiro Yamadaa1e24222016-02-26 14:21:43 +090034 enum dram_freq freq_e;
Masahiro Yamada04191e52014-12-19 20:20:52 +090035 u32 tmp;
36
Masahiro Yamadaa1e24222016-02-26 14:21:43 +090037 switch (freq) {
38 case 1333:
39 freq_e = DRAM_FREQ_1333M;
40 break;
41 case 1600:
42 freq_e = DRAM_FREQ_1600M;
43 break;
44 default:
Masahiro Yamada609cd532017-10-13 19:21:55 +090045 pr_err("unsupported DRAM frequency %d MHz\n", freq);
Masahiro Yamadaa1e24222016-02-26 14:21:43 +090046 return -EINVAL;
Masahiro Yamada04191e52014-12-19 20:20:52 +090047 }
Masahiro Yamadaa1e24222016-02-26 14:21:43 +090048
Masahiro Yamadab464ff92016-10-27 23:47:07 +090049 writel(0x0300c473, phy_base + PHY_PGCR1);
50 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
51 writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
52 writel(0x00083DEF, phy_base + PHY_PTR2);
53 writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
54 writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
55 writel(0xF004001A, phy_base + PHY_DSGCR);
Masahiro Yamada04191e52014-12-19 20:20:52 +090056
57 /* change the value of the on-die pull-up/pull-down registors */
Masahiro Yamadab464ff92016-10-27 23:47:07 +090058 tmp = readl(phy_base + PHY_DXCCR);
Masahiro Yamada04191e52014-12-19 20:20:52 +090059 tmp &= ~0x0ee0;
Masahiro Yamadab464ff92016-10-27 23:47:07 +090060 tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
61 writel(tmp, phy_base + PHY_DXCCR);
Masahiro Yamada04191e52014-12-19 20:20:52 +090062
Masahiro Yamadab464ff92016-10-27 23:47:07 +090063 writel(0x0000040B, phy_base + PHY_DCR);
64 writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
65 writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
66 writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
67 writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
68 writel(0x00000006, phy_base + PHY_MR1);
69 writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
70 writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
Masahiro Yamada04191e52014-12-19 20:20:52 +090071
Masahiro Yamadab464ff92016-10-27 23:47:07 +090072 while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
Masahiro Yamada04191e52014-12-19 20:20:52 +090073 ;
74
Masahiro Yamadab464ff92016-10-27 23:47:07 +090075 writel(0x0300C473, phy_base + PHY_PGCR1);
76 writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
Masahiro Yamada75f16f82015-09-22 00:27:39 +090077
78 return 0;
Masahiro Yamada04191e52014-12-19 20:20:52 +090079}