Chin Liang See | 1922dad | 2013-08-07 10:08:03 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Altera Corporation <www.altera.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/reset_manager.h> |
Marek Vasut | 8d8c648 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 11 | #include <asm/arch/fpga_manager.h> |
Chin Liang See | 1922dad | 2013-08-07 10:08:03 -0500 | [diff] [blame] | 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
| 15 | static const struct socfpga_reset_manager *reset_manager_base = |
| 16 | (void *)SOCFPGA_RSTMGR_ADDRESS; |
| 17 | |
Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 18 | /* Toggle reset signal to watchdog (WDT is disabled after this operation!) */ |
| 19 | void socfpga_watchdog_reset(void) |
| 20 | { |
| 21 | /* assert reset for watchdog */ |
| 22 | setbits_le32(&reset_manager_base->per_mod_reset, |
| 23 | 1 << RSTMGR_PERMODRST_L4WD0_LSB); |
| 24 | |
| 25 | /* deassert watchdog from reset (watchdog in not running state) */ |
| 26 | clrbits_le32(&reset_manager_base->per_mod_reset, |
| 27 | 1 << RSTMGR_PERMODRST_L4WD0_LSB); |
| 28 | } |
| 29 | |
Chin Liang See | 1922dad | 2013-08-07 10:08:03 -0500 | [diff] [blame] | 30 | /* |
| 31 | * Write the reset manager register to cause reset |
| 32 | */ |
| 33 | void reset_cpu(ulong addr) |
| 34 | { |
| 35 | /* request a warm reset */ |
| 36 | writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), |
| 37 | &reset_manager_base->ctrl); |
| 38 | /* |
| 39 | * infinite loop here as watchdog will trigger and reset |
| 40 | * the processor |
| 41 | */ |
| 42 | while (1) |
| 43 | ; |
| 44 | } |
| 45 | |
| 46 | /* |
| 47 | * Release peripherals from reset based on handoff |
| 48 | */ |
| 49 | void reset_deassert_peripherals_handoff(void) |
| 50 | { |
| 51 | writel(0, &reset_manager_base->per_mod_reset); |
| 52 | } |
Marek Vasut | c38c869 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 53 | |
Marek Vasut | 8d8c648 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 54 | #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) |
| 55 | void socfpga_bridges_reset(int enable) |
| 56 | { |
| 57 | /* For SoCFPGA-VT, this is NOP. */ |
| 58 | } |
| 59 | #else |
| 60 | |
| 61 | #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 |
| 62 | #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 |
| 63 | #define L3REGS_REMAP_OCRAM_MASK 0x01 |
| 64 | |
| 65 | void socfpga_bridges_reset(int enable) |
| 66 | { |
| 67 | const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | |
| 68 | L3REGS_REMAP_HPS2FPGA_MASK | |
| 69 | L3REGS_REMAP_OCRAM_MASK; |
| 70 | |
| 71 | if (enable) { |
| 72 | /* brdmodrst */ |
| 73 | writel(0xffffffff, &reset_manager_base->brg_mod_reset); |
| 74 | } else { |
| 75 | /* Check signal from FPGA. */ |
| 76 | if (fpgamgr_poll_fpga_ready()) { |
| 77 | /* FPGA not ready. Wait for watchdog timeout. */ |
| 78 | printf("%s: fpga not ready, hanging.\n", __func__); |
| 79 | hang(); |
| 80 | } |
| 81 | |
| 82 | /* brdmodrst */ |
| 83 | writel(0, &reset_manager_base->brg_mod_reset); |
| 84 | |
| 85 | /* Remap the bridges into memory map */ |
| 86 | writel(l3mask, SOCFPGA_L3REGS_ADDRESS); |
| 87 | } |
| 88 | } |
| 89 | #endif |
| 90 | |
Marek Vasut | c38c869 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 91 | /* Change the reset state for EMAC 0 and EMAC 1 */ |
| 92 | void socfpga_emac_reset(int enable) |
| 93 | { |
| 94 | const void *reset = &reset_manager_base->per_mod_reset; |
| 95 | |
| 96 | if (enable) { |
| 97 | setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); |
| 98 | setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); |
| 99 | } else { |
| 100 | #if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) |
| 101 | clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); |
| 102 | #elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) |
| 103 | clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); |
| 104 | #endif |
| 105 | } |
| 106 | } |
Stefan Roese | ca6b8fb | 2014-11-07 13:50:30 +0100 | [diff] [blame] | 107 | |
| 108 | /* SPI Master enable (its held in reset by the preloader) */ |
| 109 | void socfpga_spim_enable(void) |
| 110 | { |
| 111 | const void *reset = &reset_manager_base->per_mod_reset; |
| 112 | |
Stefan Roese | 5e87233 | 2014-11-16 12:46:59 +0100 | [diff] [blame^] | 113 | clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | |
| 114 | (1 << RSTMGR_PERMODRST_SPIM1_LSB)); |
Stefan Roese | ca6b8fb | 2014-11-07 13:50:30 +0100 | [diff] [blame] | 115 | } |