Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / drivers / pinctrl / renesas / pfc-r8a7796.c
blob: 7bc9fb709eab85529cc931c561ea56d6d8827691 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]12 */
13
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]14#include <dm.h>
15#include <errno.h>
16#include <dm/pinctrl.h>
17#include <linux/kernel.h>
18
19#include "sh_pfc.h"
20
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]21#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]22
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]23#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]36
37#define CPU_ALL_NOGP(fn) \
38 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
57 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]72 PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]73 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
76 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
77 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
78 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
79 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
80 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
81
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]82/*
83 * F_() : just information
84 * FM() : macro for FN_xxx / xxx_MARK
85 */
86
87/* GPSR0 */
88#define GPSR0_15 F_(D15, IP7_11_8)
89#define GPSR0_14 F_(D14, IP7_7_4)
90#define GPSR0_13 F_(D13, IP7_3_0)
91#define GPSR0_12 F_(D12, IP6_31_28)
92#define GPSR0_11 F_(D11, IP6_27_24)
93#define GPSR0_10 F_(D10, IP6_23_20)
94#define GPSR0_9 F_(D9, IP6_19_16)
95#define GPSR0_8 F_(D8, IP6_15_12)
96#define GPSR0_7 F_(D7, IP6_11_8)
97#define GPSR0_6 F_(D6, IP6_7_4)
98#define GPSR0_5 F_(D5, IP6_3_0)
99#define GPSR0_4 F_(D4, IP5_31_28)
100#define GPSR0_3 F_(D3, IP5_27_24)
101#define GPSR0_2 F_(D2, IP5_23_20)
102#define GPSR0_1 F_(D1, IP5_19_16)
103#define GPSR0_0 F_(D0, IP5_15_12)
104
105/* GPSR1 */
106#define GPSR1_28 FM(CLKOUT)
107#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
108#define GPSR1_26 F_(WE1_N, IP5_7_4)
109#define GPSR1_25 F_(WE0_N, IP5_3_0)
110#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
111#define GPSR1_23 F_(RD_N, IP4_27_24)
112#define GPSR1_22 F_(BS_N, IP4_23_20)
113#define GPSR1_21 F_(CS1_N, IP4_19_16)
114#define GPSR1_20 F_(CS0_N, IP4_15_12)
115#define GPSR1_19 F_(A19, IP4_11_8)
116#define GPSR1_18 F_(A18, IP4_7_4)
117#define GPSR1_17 F_(A17, IP4_3_0)
118#define GPSR1_16 F_(A16, IP3_31_28)
119#define GPSR1_15 F_(A15, IP3_27_24)
120#define GPSR1_14 F_(A14, IP3_23_20)
121#define GPSR1_13 F_(A13, IP3_19_16)
122#define GPSR1_12 F_(A12, IP3_15_12)
123#define GPSR1_11 F_(A11, IP3_11_8)
124#define GPSR1_10 F_(A10, IP3_7_4)
125#define GPSR1_9 F_(A9, IP3_3_0)
126#define GPSR1_8 F_(A8, IP2_31_28)
127#define GPSR1_7 F_(A7, IP2_27_24)
128#define GPSR1_6 F_(A6, IP2_23_20)
129#define GPSR1_5 F_(A5, IP2_19_16)
130#define GPSR1_4 F_(A4, IP2_15_12)
131#define GPSR1_3 F_(A3, IP2_11_8)
132#define GPSR1_2 F_(A2, IP2_7_4)
133#define GPSR1_1 F_(A1, IP2_3_0)
134#define GPSR1_0 F_(A0, IP1_31_28)
135
136/* GPSR2 */
137#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
138#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
139#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
140#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
141#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
142#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
143#define GPSR2_8 F_(PWM2_A, IP1_27_24)
144#define GPSR2_7 F_(PWM1_A, IP1_23_20)
145#define GPSR2_6 F_(PWM0, IP1_19_16)
146#define GPSR2_5 F_(IRQ5, IP1_15_12)
147#define GPSR2_4 F_(IRQ4, IP1_11_8)
148#define GPSR2_3 F_(IRQ3, IP1_7_4)
149#define GPSR2_2 F_(IRQ2, IP1_3_0)
150#define GPSR2_1 F_(IRQ1, IP0_31_28)
151#define GPSR2_0 F_(IRQ0, IP0_27_24)
152
153/* GPSR3 */
154#define GPSR3_15 F_(SD1_WP, IP11_23_20)
155#define GPSR3_14 F_(SD1_CD, IP11_19_16)
156#define GPSR3_13 F_(SD0_WP, IP11_15_12)
157#define GPSR3_12 F_(SD0_CD, IP11_11_8)
158#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
159#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
160#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
161#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
162#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
163#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
164#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
165#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
166#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
167#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
168#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
169#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
170
171/* GPSR4 */
172#define GPSR4_17 F_(SD3_DS, IP11_7_4)
173#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
174#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
175#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
176#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
177#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
178#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
179#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
180#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
181#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
182#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
183#define GPSR4_6 F_(SD2_DS, IP9_27_24)
184#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
185#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
186#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
187#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
188#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
189#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
190
191/* GPSR5 */
192#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
193#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
194#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
195#define GPSR5_22 FM(MSIOF0_RXD)
196#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
197#define GPSR5_20 FM(MSIOF0_TXD)
198#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
199#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
200#define GPSR5_17 FM(MSIOF0_SCK)
201#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
202#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
203#define GPSR5_14 F_(HTX0, IP13_19_16)
204#define GPSR5_13 F_(HRX0, IP13_15_12)
205#define GPSR5_12 F_(HSCK0, IP13_11_8)
206#define GPSR5_11 F_(RX2_A, IP13_7_4)
207#define GPSR5_10 F_(TX2_A, IP13_3_0)
208#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]209#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]210#define GPSR5_7 F_(CTS1_N, IP12_23_20)
211#define GPSR5_6 F_(TX1_A, IP12_19_16)
212#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]213#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]214#define GPSR5_3 F_(CTS0_N, IP12_7_4)
215#define GPSR5_2 F_(TX0, IP12_3_0)
216#define GPSR5_1 F_(RX0, IP11_31_28)
217#define GPSR5_0 F_(SCK0, IP11_27_24)
218
219/* GPSR6 */
220#define GPSR6_31 F_(GP6_31, IP18_7_4)
221#define GPSR6_30 F_(GP6_30, IP18_3_0)
222#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
223#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
224#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
225#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
226#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
227#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
228#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
229#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
230#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
231#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
232#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
233#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
234#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
235#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
236#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
237#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
238#define GPSR6_13 FM(SSI_SDATA5)
239#define GPSR6_12 FM(SSI_WS5)
240#define GPSR6_11 FM(SSI_SCK5)
241#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
242#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
243#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
244#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
245#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
246#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
247#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
248#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
249#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
250#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
251#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
252
253/* GPSR7 */
254#define GPSR7_3 FM(GP7_03)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]255#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]256#define GPSR7_1 FM(AVS2)
257#define GPSR7_0 FM(AVS1)
258
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]259/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
260#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]265#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]266#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]269#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]275#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]285#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]286#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287
288/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
289#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]303#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]304#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]316#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]317#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
319/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
355/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
356#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]363#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]364#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]367#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]368#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
377#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384
385/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
386#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]403#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]404#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
406#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
407#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
408#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
409#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
410#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
412#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413
414#define PINMUX_GPSR \
415\
416 GPSR6_31 \
417 GPSR6_30 \
418 GPSR6_29 \
419 GPSR1_28 GPSR6_28 \
420 GPSR1_27 GPSR6_27 \
421 GPSR1_26 GPSR6_26 \
422 GPSR1_25 GPSR5_25 GPSR6_25 \
423 GPSR1_24 GPSR5_24 GPSR6_24 \
424 GPSR1_23 GPSR5_23 GPSR6_23 \
425 GPSR1_22 GPSR5_22 GPSR6_22 \
426 GPSR1_21 GPSR5_21 GPSR6_21 \
427 GPSR1_20 GPSR5_20 GPSR6_20 \
428 GPSR1_19 GPSR5_19 GPSR6_19 \
429 GPSR1_18 GPSR5_18 GPSR6_18 \
430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
432GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
433GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
434GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
435GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
436GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
437GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
438GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
439GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
440GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
441GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
442GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
443GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
444GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
445GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
446GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
447GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448
449#define PINMUX_IPSR \
450\
451FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
452FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
453FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
454FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
455FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
456FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
457FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
458FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
459\
460FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
461FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
462FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
463FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
464FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
465FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
466FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
467FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
468\
469FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
470FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
471FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
472FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
473FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
474FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
475FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
476FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
477\
478FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
479FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
480FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
481FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
482FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
483FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
484FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
485FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
486\
487FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
488FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
489FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
490FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
491FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
492FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
493FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
494FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495
496/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
498#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
499#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
500#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
501#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
502#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
503#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
504#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
505#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
506#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
507#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
508#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
509#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
510#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
511#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
512#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
513#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]514#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]515
516/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
517#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
518#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
519#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
520#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
521#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]522#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]523#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
524#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
525#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
526#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
527#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
528#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
529#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
530#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
531#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
532#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
533#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
534#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
535#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
536#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
537#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
538#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
539
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]540/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]541#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
542#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
543#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
544#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
545#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
546#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]547#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]548#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
549#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
550#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]551#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
552#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]553#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554
555#define PINMUX_MOD_SELS \
556\
557MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
558 MOD_SEL2_30 \
559 MOD_SEL1_29_28_27 MOD_SEL2_29 \
560MOD_SEL0_28_27 MOD_SEL2_28_27 \
561MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
563MOD_SEL0_23 MOD_SEL1_23_22_21 \
564MOD_SEL0_22 MOD_SEL2_22 \
565MOD_SEL0_21 MOD_SEL2_21 \
566MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
567MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
568MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
569 MOD_SEL2_17 \
570MOD_SEL0_16 MOD_SEL1_16 \
571 MOD_SEL1_15_14 \
572MOD_SEL0_14_13 \
573 MOD_SEL1_13 \
574MOD_SEL0_12 MOD_SEL1_12 \
575MOD_SEL0_11 MOD_SEL1_11 \
576MOD_SEL0_10 MOD_SEL1_10 \
577MOD_SEL0_9_8 MOD_SEL1_9 \
578MOD_SEL0_7_6 \
579 MOD_SEL1_6 \
580MOD_SEL0_5 MOD_SEL1_5 \
581MOD_SEL0_4_3 MOD_SEL1_4 \
582 MOD_SEL1_3 \
583 MOD_SEL1_2 \
584 MOD_SEL1_1 \
585 MOD_SEL1_0 MOD_SEL2_0
586
587/*
588 * These pins are not able to be muxed but have other properties
589 * that can be set, such as drive-strength or pull-up/pull-down enable.
590 */
591#define PINMUX_STATIC \
592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
593 FM(QSPI0_IO2) FM(QSPI0_IO3) \
594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
595 FM(QSPI1_IO2) FM(QSPI1_IO3) \
596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
600 FM(PRESETOUT) \
601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]604#define PINMUX_PHYS \
605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
606
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]607enum {
608 PINMUX_RESERVED = 0,
609
610 PINMUX_DATA_BEGIN,
611 GP_ALL(DATA),
612 PINMUX_DATA_END,
613
614#define F_(x, y)
615#define FM(x) FN_##x,
616 PINMUX_FUNCTION_BEGIN,
617 GP_ALL(FN),
618 PINMUX_GPSR
619 PINMUX_IPSR
620 PINMUX_MOD_SELS
621 PINMUX_FUNCTION_END,
622#undef F_
623#undef FM
624
625#define F_(x, y)
626#define FM(x) x##_MARK,
627 PINMUX_MARK_BEGIN,
628 PINMUX_GPSR
629 PINMUX_IPSR
630 PINMUX_MOD_SELS
631 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]632 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]633 PINMUX_MARK_END,
634#undef F_
635#undef FM
636};
637
638static const u16 pinmux_data[] = {
639 PINMUX_DATA_GP_ALL(),
640
641 PINMUX_SINGLE(AVS1),
642 PINMUX_SINGLE(AVS2),
643 PINMUX_SINGLE(CLKOUT),
644 PINMUX_SINGLE(GP7_03),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]645 PINMUX_SINGLE(GP7_02),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]646 PINMUX_SINGLE(MSIOF0_RXD),
647 PINMUX_SINGLE(MSIOF0_SCK),
648 PINMUX_SINGLE(MSIOF0_TXD),
649 PINMUX_SINGLE(SSI_SCK5),
650 PINMUX_SINGLE(SSI_SDATA5),
651 PINMUX_SINGLE(SSI_WS5),
652
653 /* IPSR0 */
654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
656
657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
660
661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
664
665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
668
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
672 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]673
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
677 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]678
679 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
680 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
681 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
682 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
686
687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
694
695 /* IPSR1 */
696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
702
703 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
704 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]705 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
706 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
707 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
709
710 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
711 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]712 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
713 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
714 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
715 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
716
717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
723
724 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
725 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]726 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
727 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
728
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]733 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]734
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]735 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
738 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]739
740 PINMUX_IPSR_GPSR(IP1_31_28, A0),
741 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
742 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
743 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
744 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
745 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
746
747 /* IPSR2 */
748 PINMUX_IPSR_GPSR(IP2_3_0, A1),
749 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
750 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
751 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
752 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
753 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
754
755 PINMUX_IPSR_GPSR(IP2_7_4, A2),
756 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
757 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
758 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
759 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
760 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
761
762 PINMUX_IPSR_GPSR(IP2_11_8, A3),
763 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
764 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
765 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
766 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
767 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
768
769 PINMUX_IPSR_GPSR(IP2_15_12, A4),
770 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
771 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
772 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
773 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
774 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
775
776 PINMUX_IPSR_GPSR(IP2_19_16, A5),
777 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
778 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
779 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
780 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
781 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
782 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
783
784 PINMUX_IPSR_GPSR(IP2_23_20, A6),
785 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
786 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
787 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
788 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
789 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
790 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
791
792 PINMUX_IPSR_GPSR(IP2_27_24, A7),
793 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
794 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
795 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
796 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
797 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
798 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
799
800 PINMUX_IPSR_GPSR(IP2_31_28, A8),
801 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
802 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
803 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
804 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
805 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
806 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
807
808 /* IPSR3 */
809 PINMUX_IPSR_GPSR(IP3_3_0, A9),
810 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
811 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
812 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
813
814 PINMUX_IPSR_GPSR(IP3_7_4, A10),
815 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]816 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]817 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
818
819 PINMUX_IPSR_GPSR(IP3_11_8, A11),
820 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
821 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
822 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
823 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
824 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
825 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
826 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
827 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
828
829 PINMUX_IPSR_GPSR(IP3_15_12, A12),
830 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
831 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
832 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
833 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
834 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
835
836 PINMUX_IPSR_GPSR(IP3_19_16, A13),
837 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
838 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
839 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
840 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
841 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
842
843 PINMUX_IPSR_GPSR(IP3_23_20, A14),
844 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
845 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
846 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
847 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
848 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
849
850 PINMUX_IPSR_GPSR(IP3_27_24, A15),
851 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
852 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
853 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
854 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
855 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
856
857 PINMUX_IPSR_GPSR(IP3_31_28, A16),
858 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
859 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
860 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
861
862 /* IPSR4 */
863 PINMUX_IPSR_GPSR(IP4_3_0, A17),
864 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
865 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
866 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
867
868 PINMUX_IPSR_GPSR(IP4_7_4, A18),
869 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
870 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
871 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
872
873 PINMUX_IPSR_GPSR(IP4_11_8, A19),
874 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
875 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
876 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
877
878 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
879 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
880
881 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
882 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
883 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
884
885 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
886 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
887 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
888 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
889 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
890 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
891 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
892 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
893
894 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
895 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
896 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
897 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
898 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
900
901 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
902 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
903 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
904 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
905 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
906 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
907
908 /* IPSR5 */
909 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
910 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
911 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
912 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
913 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
914 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
915 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
916
917 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
918 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]919 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]920 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
921 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
922 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
923 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
924 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
925
926 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
927 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
928 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
929 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
930
931 PINMUX_IPSR_GPSR(IP5_15_12, D0),
932 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
933 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
934 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
935 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
936
937 PINMUX_IPSR_GPSR(IP5_19_16, D1),
938 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
939 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
940 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
941 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
942
943 PINMUX_IPSR_GPSR(IP5_23_20, D2),
944 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
945 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
946 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
947
948 PINMUX_IPSR_GPSR(IP5_27_24, D3),
949 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
950 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
951 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
952
953 PINMUX_IPSR_GPSR(IP5_31_28, D4),
954 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
955 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
956 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
957
958 /* IPSR6 */
959 PINMUX_IPSR_GPSR(IP6_3_0, D5),
960 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
961 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
962 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
963
964 PINMUX_IPSR_GPSR(IP6_7_4, D6),
965 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
966 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
967 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
968
969 PINMUX_IPSR_GPSR(IP6_11_8, D7),
970 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
971 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
972 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
973
974 PINMUX_IPSR_GPSR(IP6_15_12, D8),
975 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
976 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
977 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
978 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
979 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
980
981 PINMUX_IPSR_GPSR(IP6_19_16, D9),
982 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
983 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
984 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
985 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
986
987 PINMUX_IPSR_GPSR(IP6_23_20, D10),
988 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
989 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
990 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
991 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
992 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
993 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
994
995 PINMUX_IPSR_GPSR(IP6_27_24, D11),
996 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
997 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
998 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
999 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1000 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1001 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1002
1003 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1004 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1005 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1006 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1007 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1008 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1009
1010 /* IPSR7 */
1011 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1012 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1013 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1014 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1015 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1016 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1017
1018 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1019 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1020 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1021 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1022 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1023 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1024 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1025
1026 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1027 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1028 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1029 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1030 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1031 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1032 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1033
1034 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1035 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1036 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1037
1038 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1039 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1040 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1041
1042 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1043 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1044 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1045 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1046
1047 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1048 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1049 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1050 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1051
1052 /* IPSR8 */
1053 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1054 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1055 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1056 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1057
1058 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1059 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1060 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1061 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1062
1063 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1064 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1065 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1066
1067 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1068 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1069 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1070 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1071 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1072
1073 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1074 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1075 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1076 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1077 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1078 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1079
1080 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1081 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1082 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1083 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1084 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1085 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1086
1087 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1088 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1089 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1090 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1091 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1092 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1093
1094 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1095 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1096 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1097 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1098 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1099 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1100
1101 /* IPSR9 */
1102 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1103 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1104
1105 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1106 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1107
1108 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1109 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1110
1111 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1112 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1113
1114 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1115 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1116
1117 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1118 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1119
1120 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1121 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1122
1123 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1124 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1125
1126 /* IPSR10 */
1127 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1128 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1129
1130 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1131 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1132
1133 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1134 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1135
1136 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1137 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1138
1139 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1140 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1141
1142 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1143 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1144 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1145
1146 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1147 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1148 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1149
1150 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1151 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1152 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1153
1154 /* IPSR11 */
1155 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1156 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1157 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1158
1159 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1160 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1161
1162 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1163 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1164 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1165 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1166
1167 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1168 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1169 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1170
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1171 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1172 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1173 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1174 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1175
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1176 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1177 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1178 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1179 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1180
1181 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1182 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1183 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1184 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1185 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1186 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1187 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1188 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1189 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1190 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1191
1192 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1193 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1194 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1195 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1196 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1197
1198 /* IPSR12 */
1199 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1200 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1201 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1202 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1203 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1204
1205 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1206 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1207 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1208 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1209 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1210 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1211 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1212 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1213
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1214 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1215 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1216 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1217 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1218 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1219 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1220 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1221 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1222
1223 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1224 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1225 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1226 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1227 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1228
1229 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1231 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1232 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1233 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1234
1235 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1236 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1237 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1238 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1239 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1240 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1241 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1242
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1243 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1244 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1245 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1246 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1247 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1248 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1249 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1250
1251 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1252 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1253 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1254 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1255 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1256 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1257 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1258
1259 /* IPSR13 */
1260 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1261 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1262 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1263 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1264 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1265 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1266
1267 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1268 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1269 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1270 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1271 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1272 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1273
1274 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1275 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1276 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1277 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1278 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1279 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1280 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1281 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1282
1283 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1284 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1285 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1286 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1287 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1288 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1289
1290 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1291 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1292 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1293 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1294 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1295 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1296
1297 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1298 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1299 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1300 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1301 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1302 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1303 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1304 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1305
1306 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1307 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1308 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1309 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1310 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1311 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1312 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1313
1314 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1315 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1316 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1317 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1318
1319 /* IPSR14 */
1320 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1321 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1322 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1323 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1324 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1325 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1326 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1327 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1328
1329 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1330 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1331 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1332 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1333 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1334 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1335 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1336 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1337
1338 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1339 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1340 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1341
1342 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1343 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1344 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1345 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1346
1347 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1348 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1349 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1350
1351 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1352 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1353
1354 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1355 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1356
1357 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1358 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1359
1360 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1361 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1362
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1363 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1364 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1365
1366 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1367 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1368 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1369
1370 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1371 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1372 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1373 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1374
1375 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1376 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1377 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1378 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1379 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1381 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1382
1383 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1384 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1385 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1386 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1387 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1389 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1390
1391 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1392 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1393 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1394 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1395 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1397 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1398
1399 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1400 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1401 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1402 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1403 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1405 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1406
1407 /* IPSR16 */
1408 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1409 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1410
1411 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1412 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1413
1414 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1415 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1416
1417 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1418 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1419 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1420 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1421 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1422 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1423 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1424
1425 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1426 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1427 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1428 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1429 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1430 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1431 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1432
1433 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1434 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1435 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1436 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1437 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1438 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1439 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1440 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1441
1442 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1443 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1444 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1445 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1446 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1447 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1448 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1449
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1451 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1452 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1453 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1455 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1456 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1457 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1458
1459 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1460 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1461
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1462 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1463 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1464 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1465 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1466 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1467
1468 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1469 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1470 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1473 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1475
1476 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1477 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1478 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1479 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1480 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1481 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1482
1483 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1484 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1485 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1486 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1487 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1488 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1489 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1490 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1491 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1492
1493 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1494 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1495 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1496 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1497 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1498 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1499 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1500 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1501 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1502
1503 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1504 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1505 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1506 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1507 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1508 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1509 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1510 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1511 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1512 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1513 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1514
1515 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1516 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1517 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1518 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1519 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1520 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1521 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1522 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1523 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1524
1525 /* IPSR18 */
1526 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1527 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1528 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1529 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1530 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1531 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1532 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1533 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1534 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1535
1536 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1537 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1538 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1539 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1540 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1541 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1542 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1543 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1544 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1545
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1546/*
1547 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1548 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1549 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1550 * core will do the right thing and skip trying to mux the pin
1551 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1552 */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]1553#define FM(x) PINMUX_DATA(x##_MARK, 0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1554 PINMUX_STATIC
1555#undef FM
1556};
1557
1558/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1559 * Pins not associated with a GPIO port.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1560 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1561enum {
1562 GP_ASSIGN_LAST(),
1563 NOGP_ALL(),
1564};
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1565
1566static const struct sh_pfc_pin pinmux_pins[] = {
1567 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1568 PINMUX_NOGP_ALL(),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1569};
1570
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]1571#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1572/* - AUDIO CLOCK ------------------------------------------------------------ */
1573static const unsigned int audio_clk_a_a_pins[] = {
1574 /* CLK A */
1575 RCAR_GP_PIN(6, 22),
1576};
1577static const unsigned int audio_clk_a_a_mux[] = {
1578 AUDIO_CLKA_A_MARK,
1579};
1580static const unsigned int audio_clk_a_b_pins[] = {
1581 /* CLK A */
1582 RCAR_GP_PIN(5, 4),
1583};
1584static const unsigned int audio_clk_a_b_mux[] = {
1585 AUDIO_CLKA_B_MARK,
1586};
1587static const unsigned int audio_clk_a_c_pins[] = {
1588 /* CLK A */
1589 RCAR_GP_PIN(5, 19),
1590};
1591static const unsigned int audio_clk_a_c_mux[] = {
1592 AUDIO_CLKA_C_MARK,
1593};
1594static const unsigned int audio_clk_b_a_pins[] = {
1595 /* CLK B */
1596 RCAR_GP_PIN(5, 12),
1597};
1598static const unsigned int audio_clk_b_a_mux[] = {
1599 AUDIO_CLKB_A_MARK,
1600};
1601static const unsigned int audio_clk_b_b_pins[] = {
1602 /* CLK B */
1603 RCAR_GP_PIN(6, 23),
1604};
1605static const unsigned int audio_clk_b_b_mux[] = {
1606 AUDIO_CLKB_B_MARK,
1607};
1608static const unsigned int audio_clk_c_a_pins[] = {
1609 /* CLK C */
1610 RCAR_GP_PIN(5, 21),
1611};
1612static const unsigned int audio_clk_c_a_mux[] = {
1613 AUDIO_CLKC_A_MARK,
1614};
1615static const unsigned int audio_clk_c_b_pins[] = {
1616 /* CLK C */
1617 RCAR_GP_PIN(5, 0),
1618};
1619static const unsigned int audio_clk_c_b_mux[] = {
1620 AUDIO_CLKC_B_MARK,
1621};
1622static const unsigned int audio_clkout_a_pins[] = {
1623 /* CLKOUT */
1624 RCAR_GP_PIN(5, 18),
1625};
1626static const unsigned int audio_clkout_a_mux[] = {
1627 AUDIO_CLKOUT_A_MARK,
1628};
1629static const unsigned int audio_clkout_b_pins[] = {
1630 /* CLKOUT */
1631 RCAR_GP_PIN(6, 28),
1632};
1633static const unsigned int audio_clkout_b_mux[] = {
1634 AUDIO_CLKOUT_B_MARK,
1635};
1636static const unsigned int audio_clkout_c_pins[] = {
1637 /* CLKOUT */
1638 RCAR_GP_PIN(5, 3),
1639};
1640static const unsigned int audio_clkout_c_mux[] = {
1641 AUDIO_CLKOUT_C_MARK,
1642};
1643static const unsigned int audio_clkout_d_pins[] = {
1644 /* CLKOUT */
1645 RCAR_GP_PIN(5, 21),
1646};
1647static const unsigned int audio_clkout_d_mux[] = {
1648 AUDIO_CLKOUT_D_MARK,
1649};
1650static const unsigned int audio_clkout1_a_pins[] = {
1651 /* CLKOUT1 */
1652 RCAR_GP_PIN(5, 15),
1653};
1654static const unsigned int audio_clkout1_a_mux[] = {
1655 AUDIO_CLKOUT1_A_MARK,
1656};
1657static const unsigned int audio_clkout1_b_pins[] = {
1658 /* CLKOUT1 */
1659 RCAR_GP_PIN(6, 29),
1660};
1661static const unsigned int audio_clkout1_b_mux[] = {
1662 AUDIO_CLKOUT1_B_MARK,
1663};
1664static const unsigned int audio_clkout2_a_pins[] = {
1665 /* CLKOUT2 */
1666 RCAR_GP_PIN(5, 16),
1667};
1668static const unsigned int audio_clkout2_a_mux[] = {
1669 AUDIO_CLKOUT2_A_MARK,
1670};
1671static const unsigned int audio_clkout2_b_pins[] = {
1672 /* CLKOUT2 */
1673 RCAR_GP_PIN(6, 30),
1674};
1675static const unsigned int audio_clkout2_b_mux[] = {
1676 AUDIO_CLKOUT2_B_MARK,
1677};
1678
1679static const unsigned int audio_clkout3_a_pins[] = {
1680 /* CLKOUT3 */
1681 RCAR_GP_PIN(5, 19),
1682};
1683static const unsigned int audio_clkout3_a_mux[] = {
1684 AUDIO_CLKOUT3_A_MARK,
1685};
1686static const unsigned int audio_clkout3_b_pins[] = {
1687 /* CLKOUT3 */
1688 RCAR_GP_PIN(6, 31),
1689};
1690static const unsigned int audio_clkout3_b_mux[] = {
1691 AUDIO_CLKOUT3_B_MARK,
1692};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]1693#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1694
1695/* - EtherAVB --------------------------------------------------------------- */
1696static const unsigned int avb_link_pins[] = {
1697 /* AVB_LINK */
1698 RCAR_GP_PIN(2, 12),
1699};
1700static const unsigned int avb_link_mux[] = {
1701 AVB_LINK_MARK,
1702};
1703static const unsigned int avb_magic_pins[] = {
1704 /* AVB_MAGIC_ */
1705 RCAR_GP_PIN(2, 10),
1706};
1707static const unsigned int avb_magic_mux[] = {
1708 AVB_MAGIC_MARK,
1709};
1710static const unsigned int avb_phy_int_pins[] = {
1711 /* AVB_PHY_INT */
1712 RCAR_GP_PIN(2, 11),
1713};
1714static const unsigned int avb_phy_int_mux[] = {
1715 AVB_PHY_INT_MARK,
1716};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1717static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1718 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1719 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1720};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1721static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1722 AVB_MDC_MARK, AVB_MDIO_MARK,
1723};
1724static const unsigned int avb_mii_pins[] = {
1725 /*
1726 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1727 * AVB_TD1, AVB_TD2, AVB_TD3,
1728 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1729 * AVB_RD1, AVB_RD2, AVB_RD3,
1730 * AVB_TXCREFCLK
1731 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1732 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1733 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1734 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1735 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1736 PIN_AVB_TXCREFCLK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1737};
1738static const unsigned int avb_mii_mux[] = {
1739 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1740 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1741 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1742 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1743 AVB_TXCREFCLK_MARK,
1744};
1745static const unsigned int avb_avtp_pps_pins[] = {
1746 /* AVB_AVTP_PPS */
1747 RCAR_GP_PIN(2, 6),
1748};
1749static const unsigned int avb_avtp_pps_mux[] = {
1750 AVB_AVTP_PPS_MARK,
1751};
1752static const unsigned int avb_avtp_match_a_pins[] = {
1753 /* AVB_AVTP_MATCH_A */
1754 RCAR_GP_PIN(2, 13),
1755};
1756static const unsigned int avb_avtp_match_a_mux[] = {
1757 AVB_AVTP_MATCH_A_MARK,
1758};
1759static const unsigned int avb_avtp_capture_a_pins[] = {
1760 /* AVB_AVTP_CAPTURE_A */
1761 RCAR_GP_PIN(2, 14),
1762};
1763static const unsigned int avb_avtp_capture_a_mux[] = {
1764 AVB_AVTP_CAPTURE_A_MARK,
1765};
1766static const unsigned int avb_avtp_match_b_pins[] = {
1767 /* AVB_AVTP_MATCH_B */
1768 RCAR_GP_PIN(1, 8),
1769};
1770static const unsigned int avb_avtp_match_b_mux[] = {
1771 AVB_AVTP_MATCH_B_MARK,
1772};
1773static const unsigned int avb_avtp_capture_b_pins[] = {
1774 /* AVB_AVTP_CAPTURE_B */
1775 RCAR_GP_PIN(1, 11),
1776};
1777static const unsigned int avb_avtp_capture_b_mux[] = {
1778 AVB_AVTP_CAPTURE_B_MARK,
1779};
1780
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]1781#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1782/* - CAN ------------------------------------------------------------------ */
1783static const unsigned int can0_data_a_pins[] = {
1784 /* TX, RX */
1785 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1786};
1787static const unsigned int can0_data_a_mux[] = {
1788 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1789};
1790static const unsigned int can0_data_b_pins[] = {
1791 /* TX, RX */
1792 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1793};
1794static const unsigned int can0_data_b_mux[] = {
1795 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1796};
1797static const unsigned int can1_data_pins[] = {
1798 /* TX, RX */
1799 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1800};
1801static const unsigned int can1_data_mux[] = {
1802 CAN1_TX_MARK, CAN1_RX_MARK,
1803};
1804
1805/* - CAN Clock -------------------------------------------------------------- */
1806static const unsigned int can_clk_pins[] = {
1807 /* CLK */
1808 RCAR_GP_PIN(1, 25),
1809};
1810static const unsigned int can_clk_mux[] = {
1811 CAN_CLK_MARK,
1812};
1813
1814/* - CAN FD --------------------------------------------------------------- */
1815static const unsigned int canfd0_data_a_pins[] = {
1816 /* TX, RX */
1817 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1818};
1819static const unsigned int canfd0_data_a_mux[] = {
1820 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1821};
1822static const unsigned int canfd0_data_b_pins[] = {
1823 /* TX, RX */
1824 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1825};
1826static const unsigned int canfd0_data_b_mux[] = {
1827 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1828};
1829static const unsigned int canfd1_data_pins[] = {
1830 /* TX, RX */
1831 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1832};
1833static const unsigned int canfd1_data_mux[] = {
1834 CANFD1_TX_MARK, CANFD1_RX_MARK,
1835};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]1836#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1837
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]1838#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1839/* - DRIF0 --------------------------------------------------------------- */
1840static const unsigned int drif0_ctrl_a_pins[] = {
1841 /* CLK, SYNC */
1842 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1843};
1844static const unsigned int drif0_ctrl_a_mux[] = {
1845 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1846};
1847static const unsigned int drif0_data0_a_pins[] = {
1848 /* D0 */
1849 RCAR_GP_PIN(6, 10),
1850};
1851static const unsigned int drif0_data0_a_mux[] = {
1852 RIF0_D0_A_MARK,
1853};
1854static const unsigned int drif0_data1_a_pins[] = {
1855 /* D1 */
1856 RCAR_GP_PIN(6, 7),
1857};
1858static const unsigned int drif0_data1_a_mux[] = {
1859 RIF0_D1_A_MARK,
1860};
1861static const unsigned int drif0_ctrl_b_pins[] = {
1862 /* CLK, SYNC */
1863 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1864};
1865static const unsigned int drif0_ctrl_b_mux[] = {
1866 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1867};
1868static const unsigned int drif0_data0_b_pins[] = {
1869 /* D0 */
1870 RCAR_GP_PIN(5, 1),
1871};
1872static const unsigned int drif0_data0_b_mux[] = {
1873 RIF0_D0_B_MARK,
1874};
1875static const unsigned int drif0_data1_b_pins[] = {
1876 /* D1 */
1877 RCAR_GP_PIN(5, 2),
1878};
1879static const unsigned int drif0_data1_b_mux[] = {
1880 RIF0_D1_B_MARK,
1881};
1882static const unsigned int drif0_ctrl_c_pins[] = {
1883 /* CLK, SYNC */
1884 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1885};
1886static const unsigned int drif0_ctrl_c_mux[] = {
1887 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1888};
1889static const unsigned int drif0_data0_c_pins[] = {
1890 /* D0 */
1891 RCAR_GP_PIN(5, 13),
1892};
1893static const unsigned int drif0_data0_c_mux[] = {
1894 RIF0_D0_C_MARK,
1895};
1896static const unsigned int drif0_data1_c_pins[] = {
1897 /* D1 */
1898 RCAR_GP_PIN(5, 14),
1899};
1900static const unsigned int drif0_data1_c_mux[] = {
1901 RIF0_D1_C_MARK,
1902};
1903/* - DRIF1 --------------------------------------------------------------- */
1904static const unsigned int drif1_ctrl_a_pins[] = {
1905 /* CLK, SYNC */
1906 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1907};
1908static const unsigned int drif1_ctrl_a_mux[] = {
1909 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1910};
1911static const unsigned int drif1_data0_a_pins[] = {
1912 /* D0 */
1913 RCAR_GP_PIN(6, 19),
1914};
1915static const unsigned int drif1_data0_a_mux[] = {
1916 RIF1_D0_A_MARK,
1917};
1918static const unsigned int drif1_data1_a_pins[] = {
1919 /* D1 */
1920 RCAR_GP_PIN(6, 20),
1921};
1922static const unsigned int drif1_data1_a_mux[] = {
1923 RIF1_D1_A_MARK,
1924};
1925static const unsigned int drif1_ctrl_b_pins[] = {
1926 /* CLK, SYNC */
1927 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1928};
1929static const unsigned int drif1_ctrl_b_mux[] = {
1930 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1931};
1932static const unsigned int drif1_data0_b_pins[] = {
1933 /* D0 */
1934 RCAR_GP_PIN(5, 7),
1935};
1936static const unsigned int drif1_data0_b_mux[] = {
1937 RIF1_D0_B_MARK,
1938};
1939static const unsigned int drif1_data1_b_pins[] = {
1940 /* D1 */
1941 RCAR_GP_PIN(5, 8),
1942};
1943static const unsigned int drif1_data1_b_mux[] = {
1944 RIF1_D1_B_MARK,
1945};
1946static const unsigned int drif1_ctrl_c_pins[] = {
1947 /* CLK, SYNC */
1948 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1949};
1950static const unsigned int drif1_ctrl_c_mux[] = {
1951 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1952};
1953static const unsigned int drif1_data0_c_pins[] = {
1954 /* D0 */
1955 RCAR_GP_PIN(5, 6),
1956};
1957static const unsigned int drif1_data0_c_mux[] = {
1958 RIF1_D0_C_MARK,
1959};
1960static const unsigned int drif1_data1_c_pins[] = {
1961 /* D1 */
1962 RCAR_GP_PIN(5, 10),
1963};
1964static const unsigned int drif1_data1_c_mux[] = {
1965 RIF1_D1_C_MARK,
1966};
1967/* - DRIF2 --------------------------------------------------------------- */
1968static const unsigned int drif2_ctrl_a_pins[] = {
1969 /* CLK, SYNC */
1970 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1971};
1972static const unsigned int drif2_ctrl_a_mux[] = {
1973 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1974};
1975static const unsigned int drif2_data0_a_pins[] = {
1976 /* D0 */
1977 RCAR_GP_PIN(6, 7),
1978};
1979static const unsigned int drif2_data0_a_mux[] = {
1980 RIF2_D0_A_MARK,
1981};
1982static const unsigned int drif2_data1_a_pins[] = {
1983 /* D1 */
1984 RCAR_GP_PIN(6, 10),
1985};
1986static const unsigned int drif2_data1_a_mux[] = {
1987 RIF2_D1_A_MARK,
1988};
1989static const unsigned int drif2_ctrl_b_pins[] = {
1990 /* CLK, SYNC */
1991 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1992};
1993static const unsigned int drif2_ctrl_b_mux[] = {
1994 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1995};
1996static const unsigned int drif2_data0_b_pins[] = {
1997 /* D0 */
1998 RCAR_GP_PIN(6, 30),
1999};
2000static const unsigned int drif2_data0_b_mux[] = {
2001 RIF2_D0_B_MARK,
2002};
2003static const unsigned int drif2_data1_b_pins[] = {
2004 /* D1 */
2005 RCAR_GP_PIN(6, 31),
2006};
2007static const unsigned int drif2_data1_b_mux[] = {
2008 RIF2_D1_B_MARK,
2009};
2010/* - DRIF3 --------------------------------------------------------------- */
2011static const unsigned int drif3_ctrl_a_pins[] = {
2012 /* CLK, SYNC */
2013 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2014};
2015static const unsigned int drif3_ctrl_a_mux[] = {
2016 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2017};
2018static const unsigned int drif3_data0_a_pins[] = {
2019 /* D0 */
2020 RCAR_GP_PIN(6, 19),
2021};
2022static const unsigned int drif3_data0_a_mux[] = {
2023 RIF3_D0_A_MARK,
2024};
2025static const unsigned int drif3_data1_a_pins[] = {
2026 /* D1 */
2027 RCAR_GP_PIN(6, 20),
2028};
2029static const unsigned int drif3_data1_a_mux[] = {
2030 RIF3_D1_A_MARK,
2031};
2032static const unsigned int drif3_ctrl_b_pins[] = {
2033 /* CLK, SYNC */
2034 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2035};
2036static const unsigned int drif3_ctrl_b_mux[] = {
2037 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2038};
2039static const unsigned int drif3_data0_b_pins[] = {
2040 /* D0 */
2041 RCAR_GP_PIN(6, 28),
2042};
2043static const unsigned int drif3_data0_b_mux[] = {
2044 RIF3_D0_B_MARK,
2045};
2046static const unsigned int drif3_data1_b_pins[] = {
2047 /* D1 */
2048 RCAR_GP_PIN(6, 29),
2049};
2050static const unsigned int drif3_data1_b_mux[] = {
2051 RIF3_D1_B_MARK,
2052};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]2053#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2054
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]2055#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2056/* - DU --------------------------------------------------------------------- */
2057static const unsigned int du_rgb666_pins[] = {
2058 /* R[7:2], G[7:2], B[7:2] */
2059 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2060 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2061 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2062 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2063 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2064 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2065};
2066static const unsigned int du_rgb666_mux[] = {
2067 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2068 DU_DR3_MARK, DU_DR2_MARK,
2069 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2070 DU_DG3_MARK, DU_DG2_MARK,
2071 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2072 DU_DB3_MARK, DU_DB2_MARK,
2073};
2074static const unsigned int du_rgb888_pins[] = {
2075 /* R[7:0], G[7:0], B[7:0] */
2076 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2077 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2078 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2079 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2080 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2081 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2082 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2083 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2084 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2085};
2086static const unsigned int du_rgb888_mux[] = {
2087 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2088 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2089 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2090 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2091 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2092 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2093};
2094static const unsigned int du_clk_out_0_pins[] = {
2095 /* CLKOUT */
2096 RCAR_GP_PIN(1, 27),
2097};
2098static const unsigned int du_clk_out_0_mux[] = {
2099 DU_DOTCLKOUT0_MARK
2100};
2101static const unsigned int du_clk_out_1_pins[] = {
2102 /* CLKOUT */
2103 RCAR_GP_PIN(2, 3),
2104};
2105static const unsigned int du_clk_out_1_mux[] = {
2106 DU_DOTCLKOUT1_MARK
2107};
2108static const unsigned int du_sync_pins[] = {
2109 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2110 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2111};
2112static const unsigned int du_sync_mux[] = {
2113 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2114};
2115static const unsigned int du_oddf_pins[] = {
2116 /* EXDISP/EXODDF/EXCDE */
2117 RCAR_GP_PIN(2, 2),
2118};
2119static const unsigned int du_oddf_mux[] = {
2120 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2121};
2122static const unsigned int du_cde_pins[] = {
2123 /* CDE */
2124 RCAR_GP_PIN(2, 0),
2125};
2126static const unsigned int du_cde_mux[] = {
2127 DU_CDE_MARK,
2128};
2129static const unsigned int du_disp_pins[] = {
2130 /* DISP */
2131 RCAR_GP_PIN(2, 1),
2132};
2133static const unsigned int du_disp_mux[] = {
2134 DU_DISP_MARK,
2135};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]2136#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2137
2138/* - HSCIF0 ----------------------------------------------------------------- */
2139static const unsigned int hscif0_data_pins[] = {
2140 /* RX, TX */
2141 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2142};
2143static const unsigned int hscif0_data_mux[] = {
2144 HRX0_MARK, HTX0_MARK,
2145};
2146static const unsigned int hscif0_clk_pins[] = {
2147 /* SCK */
2148 RCAR_GP_PIN(5, 12),
2149};
2150static const unsigned int hscif0_clk_mux[] = {
2151 HSCK0_MARK,
2152};
2153static const unsigned int hscif0_ctrl_pins[] = {
2154 /* RTS, CTS */
2155 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2156};
2157static const unsigned int hscif0_ctrl_mux[] = {
2158 HRTS0_N_MARK, HCTS0_N_MARK,
2159};
2160/* - HSCIF1 ----------------------------------------------------------------- */
2161static const unsigned int hscif1_data_a_pins[] = {
2162 /* RX, TX */
2163 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2164};
2165static const unsigned int hscif1_data_a_mux[] = {
2166 HRX1_A_MARK, HTX1_A_MARK,
2167};
2168static const unsigned int hscif1_clk_a_pins[] = {
2169 /* SCK */
2170 RCAR_GP_PIN(6, 21),
2171};
2172static const unsigned int hscif1_clk_a_mux[] = {
2173 HSCK1_A_MARK,
2174};
2175static const unsigned int hscif1_ctrl_a_pins[] = {
2176 /* RTS, CTS */
2177 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2178};
2179static const unsigned int hscif1_ctrl_a_mux[] = {
2180 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2181};
2182
2183static const unsigned int hscif1_data_b_pins[] = {
2184 /* RX, TX */
2185 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2186};
2187static const unsigned int hscif1_data_b_mux[] = {
2188 HRX1_B_MARK, HTX1_B_MARK,
2189};
2190static const unsigned int hscif1_clk_b_pins[] = {
2191 /* SCK */
2192 RCAR_GP_PIN(5, 0),
2193};
2194static const unsigned int hscif1_clk_b_mux[] = {
2195 HSCK1_B_MARK,
2196};
2197static const unsigned int hscif1_ctrl_b_pins[] = {
2198 /* RTS, CTS */
2199 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2200};
2201static const unsigned int hscif1_ctrl_b_mux[] = {
2202 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2203};
2204/* - HSCIF2 ----------------------------------------------------------------- */
2205static const unsigned int hscif2_data_a_pins[] = {
2206 /* RX, TX */
2207 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2208};
2209static const unsigned int hscif2_data_a_mux[] = {
2210 HRX2_A_MARK, HTX2_A_MARK,
2211};
2212static const unsigned int hscif2_clk_a_pins[] = {
2213 /* SCK */
2214 RCAR_GP_PIN(6, 10),
2215};
2216static const unsigned int hscif2_clk_a_mux[] = {
2217 HSCK2_A_MARK,
2218};
2219static const unsigned int hscif2_ctrl_a_pins[] = {
2220 /* RTS, CTS */
2221 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2222};
2223static const unsigned int hscif2_ctrl_a_mux[] = {
2224 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2225};
2226
2227static const unsigned int hscif2_data_b_pins[] = {
2228 /* RX, TX */
2229 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2230};
2231static const unsigned int hscif2_data_b_mux[] = {
2232 HRX2_B_MARK, HTX2_B_MARK,
2233};
2234static const unsigned int hscif2_clk_b_pins[] = {
2235 /* SCK */
2236 RCAR_GP_PIN(6, 21),
2237};
2238static const unsigned int hscif2_clk_b_mux[] = {
2239 HSCK2_B_MARK,
2240};
2241static const unsigned int hscif2_ctrl_b_pins[] = {
2242 /* RTS, CTS */
2243 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2244};
2245static const unsigned int hscif2_ctrl_b_mux[] = {
2246 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2247};
2248
2249static const unsigned int hscif2_data_c_pins[] = {
2250 /* RX, TX */
2251 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2252};
2253static const unsigned int hscif2_data_c_mux[] = {
2254 HRX2_C_MARK, HTX2_C_MARK,
2255};
2256static const unsigned int hscif2_clk_c_pins[] = {
2257 /* SCK */
2258 RCAR_GP_PIN(6, 24),
2259};
2260static const unsigned int hscif2_clk_c_mux[] = {
2261 HSCK2_C_MARK,
2262};
2263static const unsigned int hscif2_ctrl_c_pins[] = {
2264 /* RTS, CTS */
2265 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2266};
2267static const unsigned int hscif2_ctrl_c_mux[] = {
2268 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2269};
2270/* - HSCIF3 ----------------------------------------------------------------- */
2271static const unsigned int hscif3_data_a_pins[] = {
2272 /* RX, TX */
2273 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2274};
2275static const unsigned int hscif3_data_a_mux[] = {
2276 HRX3_A_MARK, HTX3_A_MARK,
2277};
2278static const unsigned int hscif3_clk_pins[] = {
2279 /* SCK */
2280 RCAR_GP_PIN(1, 22),
2281};
2282static const unsigned int hscif3_clk_mux[] = {
2283 HSCK3_MARK,
2284};
2285static const unsigned int hscif3_ctrl_pins[] = {
2286 /* RTS, CTS */
2287 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2288};
2289static const unsigned int hscif3_ctrl_mux[] = {
2290 HRTS3_N_MARK, HCTS3_N_MARK,
2291};
2292
2293static const unsigned int hscif3_data_b_pins[] = {
2294 /* RX, TX */
2295 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2296};
2297static const unsigned int hscif3_data_b_mux[] = {
2298 HRX3_B_MARK, HTX3_B_MARK,
2299};
2300static const unsigned int hscif3_data_c_pins[] = {
2301 /* RX, TX */
2302 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2303};
2304static const unsigned int hscif3_data_c_mux[] = {
2305 HRX3_C_MARK, HTX3_C_MARK,
2306};
2307static const unsigned int hscif3_data_d_pins[] = {
2308 /* RX, TX */
2309 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2310};
2311static const unsigned int hscif3_data_d_mux[] = {
2312 HRX3_D_MARK, HTX3_D_MARK,
2313};
2314/* - HSCIF4 ----------------------------------------------------------------- */
2315static const unsigned int hscif4_data_a_pins[] = {
2316 /* RX, TX */
2317 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2318};
2319static const unsigned int hscif4_data_a_mux[] = {
2320 HRX4_A_MARK, HTX4_A_MARK,
2321};
2322static const unsigned int hscif4_clk_pins[] = {
2323 /* SCK */
2324 RCAR_GP_PIN(1, 11),
2325};
2326static const unsigned int hscif4_clk_mux[] = {
2327 HSCK4_MARK,
2328};
2329static const unsigned int hscif4_ctrl_pins[] = {
2330 /* RTS, CTS */
2331 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2332};
2333static const unsigned int hscif4_ctrl_mux[] = {
2334 HRTS4_N_MARK, HCTS4_N_MARK,
2335};
2336
2337static const unsigned int hscif4_data_b_pins[] = {
2338 /* RX, TX */
2339 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2340};
2341static const unsigned int hscif4_data_b_mux[] = {
2342 HRX4_B_MARK, HTX4_B_MARK,
2343};
2344
2345/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2346static const unsigned int i2c0_pins[] = {
2347 /* SCL, SDA */
2348 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2349};
2350
2351static const unsigned int i2c0_mux[] = {
2352 SCL0_MARK, SDA0_MARK,
2353};
2354
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2355static const unsigned int i2c1_a_pins[] = {
2356 /* SDA, SCL */
2357 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2358};
2359static const unsigned int i2c1_a_mux[] = {
2360 SDA1_A_MARK, SCL1_A_MARK,
2361};
2362static const unsigned int i2c1_b_pins[] = {
2363 /* SDA, SCL */
2364 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2365};
2366static const unsigned int i2c1_b_mux[] = {
2367 SDA1_B_MARK, SCL1_B_MARK,
2368};
2369static const unsigned int i2c2_a_pins[] = {
2370 /* SDA, SCL */
2371 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2372};
2373static const unsigned int i2c2_a_mux[] = {
2374 SDA2_A_MARK, SCL2_A_MARK,
2375};
2376static const unsigned int i2c2_b_pins[] = {
2377 /* SDA, SCL */
2378 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2379};
2380static const unsigned int i2c2_b_mux[] = {
2381 SDA2_B_MARK, SCL2_B_MARK,
2382};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2383
2384static const unsigned int i2c3_pins[] = {
2385 /* SCL, SDA */
2386 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2387};
2388
2389static const unsigned int i2c3_mux[] = {
2390 SCL3_MARK, SDA3_MARK,
2391};
2392
2393static const unsigned int i2c5_pins[] = {
2394 /* SCL, SDA */
2395 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2396};
2397
2398static const unsigned int i2c5_mux[] = {
2399 SCL5_MARK, SDA5_MARK,
2400};
2401
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2402static const unsigned int i2c6_a_pins[] = {
2403 /* SDA, SCL */
2404 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2405};
2406static const unsigned int i2c6_a_mux[] = {
2407 SDA6_A_MARK, SCL6_A_MARK,
2408};
2409static const unsigned int i2c6_b_pins[] = {
2410 /* SDA, SCL */
2411 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2412};
2413static const unsigned int i2c6_b_mux[] = {
2414 SDA6_B_MARK, SCL6_B_MARK,
2415};
2416static const unsigned int i2c6_c_pins[] = {
2417 /* SDA, SCL */
2418 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2419};
2420static const unsigned int i2c6_c_mux[] = {
2421 SDA6_C_MARK, SCL6_C_MARK,
2422};
2423
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]2424#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2425/* - INTC-EX ---------------------------------------------------------------- */
2426static const unsigned int intc_ex_irq0_pins[] = {
2427 /* IRQ0 */
2428 RCAR_GP_PIN(2, 0),
2429};
2430static const unsigned int intc_ex_irq0_mux[] = {
2431 IRQ0_MARK,
2432};
2433static const unsigned int intc_ex_irq1_pins[] = {
2434 /* IRQ1 */
2435 RCAR_GP_PIN(2, 1),
2436};
2437static const unsigned int intc_ex_irq1_mux[] = {
2438 IRQ1_MARK,
2439};
2440static const unsigned int intc_ex_irq2_pins[] = {
2441 /* IRQ2 */
2442 RCAR_GP_PIN(2, 2),
2443};
2444static const unsigned int intc_ex_irq2_mux[] = {
2445 IRQ2_MARK,
2446};
2447static const unsigned int intc_ex_irq3_pins[] = {
2448 /* IRQ3 */
2449 RCAR_GP_PIN(2, 3),
2450};
2451static const unsigned int intc_ex_irq3_mux[] = {
2452 IRQ3_MARK,
2453};
2454static const unsigned int intc_ex_irq4_pins[] = {
2455 /* IRQ4 */
2456 RCAR_GP_PIN(2, 4),
2457};
2458static const unsigned int intc_ex_irq4_mux[] = {
2459 IRQ4_MARK,
2460};
2461static const unsigned int intc_ex_irq5_pins[] = {
2462 /* IRQ5 */
2463 RCAR_GP_PIN(2, 5),
2464};
2465static const unsigned int intc_ex_irq5_mux[] = {
2466 IRQ5_MARK,
2467};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]2468#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2469
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]2470#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
2471/* - MLB+ ------------------------------------------------------------------- */
2472static const unsigned int mlb_3pin_pins[] = {
2473 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2474};
2475static const unsigned int mlb_3pin_mux[] = {
2476 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2477};
2478#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2479
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]2480#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2481/* - MSIOF0 ----------------------------------------------------------------- */
2482static const unsigned int msiof0_clk_pins[] = {
2483 /* SCK */
2484 RCAR_GP_PIN(5, 17),
2485};
2486static const unsigned int msiof0_clk_mux[] = {
2487 MSIOF0_SCK_MARK,
2488};
2489static const unsigned int msiof0_sync_pins[] = {
2490 /* SYNC */
2491 RCAR_GP_PIN(5, 18),
2492};
2493static const unsigned int msiof0_sync_mux[] = {
2494 MSIOF0_SYNC_MARK,
2495};
2496static const unsigned int msiof0_ss1_pins[] = {
2497 /* SS1 */
2498 RCAR_GP_PIN(5, 19),
2499};
2500static const unsigned int msiof0_ss1_mux[] = {
2501 MSIOF0_SS1_MARK,
2502};
2503static const unsigned int msiof0_ss2_pins[] = {
2504 /* SS2 */
2505 RCAR_GP_PIN(5, 21),
2506};
2507static const unsigned int msiof0_ss2_mux[] = {
2508 MSIOF0_SS2_MARK,
2509};
2510static const unsigned int msiof0_txd_pins[] = {
2511 /* TXD */
2512 RCAR_GP_PIN(5, 20),
2513};
2514static const unsigned int msiof0_txd_mux[] = {
2515 MSIOF0_TXD_MARK,
2516};
2517static const unsigned int msiof0_rxd_pins[] = {
2518 /* RXD */
2519 RCAR_GP_PIN(5, 22),
2520};
2521static const unsigned int msiof0_rxd_mux[] = {
2522 MSIOF0_RXD_MARK,
2523};
2524/* - MSIOF1 ----------------------------------------------------------------- */
2525static const unsigned int msiof1_clk_a_pins[] = {
2526 /* SCK */
2527 RCAR_GP_PIN(6, 8),
2528};
2529static const unsigned int msiof1_clk_a_mux[] = {
2530 MSIOF1_SCK_A_MARK,
2531};
2532static const unsigned int msiof1_sync_a_pins[] = {
2533 /* SYNC */
2534 RCAR_GP_PIN(6, 9),
2535};
2536static const unsigned int msiof1_sync_a_mux[] = {
2537 MSIOF1_SYNC_A_MARK,
2538};
2539static const unsigned int msiof1_ss1_a_pins[] = {
2540 /* SS1 */
2541 RCAR_GP_PIN(6, 5),
2542};
2543static const unsigned int msiof1_ss1_a_mux[] = {
2544 MSIOF1_SS1_A_MARK,
2545};
2546static const unsigned int msiof1_ss2_a_pins[] = {
2547 /* SS2 */
2548 RCAR_GP_PIN(6, 6),
2549};
2550static const unsigned int msiof1_ss2_a_mux[] = {
2551 MSIOF1_SS2_A_MARK,
2552};
2553static const unsigned int msiof1_txd_a_pins[] = {
2554 /* TXD */
2555 RCAR_GP_PIN(6, 7),
2556};
2557static const unsigned int msiof1_txd_a_mux[] = {
2558 MSIOF1_TXD_A_MARK,
2559};
2560static const unsigned int msiof1_rxd_a_pins[] = {
2561 /* RXD */
2562 RCAR_GP_PIN(6, 10),
2563};
2564static const unsigned int msiof1_rxd_a_mux[] = {
2565 MSIOF1_RXD_A_MARK,
2566};
2567static const unsigned int msiof1_clk_b_pins[] = {
2568 /* SCK */
2569 RCAR_GP_PIN(5, 9),
2570};
2571static const unsigned int msiof1_clk_b_mux[] = {
2572 MSIOF1_SCK_B_MARK,
2573};
2574static const unsigned int msiof1_sync_b_pins[] = {
2575 /* SYNC */
2576 RCAR_GP_PIN(5, 3),
2577};
2578static const unsigned int msiof1_sync_b_mux[] = {
2579 MSIOF1_SYNC_B_MARK,
2580};
2581static const unsigned int msiof1_ss1_b_pins[] = {
2582 /* SS1 */
2583 RCAR_GP_PIN(5, 4),
2584};
2585static const unsigned int msiof1_ss1_b_mux[] = {
2586 MSIOF1_SS1_B_MARK,
2587};
2588static const unsigned int msiof1_ss2_b_pins[] = {
2589 /* SS2 */
2590 RCAR_GP_PIN(5, 0),
2591};
2592static const unsigned int msiof1_ss2_b_mux[] = {
2593 MSIOF1_SS2_B_MARK,
2594};
2595static const unsigned int msiof1_txd_b_pins[] = {
2596 /* TXD */
2597 RCAR_GP_PIN(5, 8),
2598};
2599static const unsigned int msiof1_txd_b_mux[] = {
2600 MSIOF1_TXD_B_MARK,
2601};
2602static const unsigned int msiof1_rxd_b_pins[] = {
2603 /* RXD */
2604 RCAR_GP_PIN(5, 7),
2605};
2606static const unsigned int msiof1_rxd_b_mux[] = {
2607 MSIOF1_RXD_B_MARK,
2608};
2609static const unsigned int msiof1_clk_c_pins[] = {
2610 /* SCK */
2611 RCAR_GP_PIN(6, 17),
2612};
2613static const unsigned int msiof1_clk_c_mux[] = {
2614 MSIOF1_SCK_C_MARK,
2615};
2616static const unsigned int msiof1_sync_c_pins[] = {
2617 /* SYNC */
2618 RCAR_GP_PIN(6, 18),
2619};
2620static const unsigned int msiof1_sync_c_mux[] = {
2621 MSIOF1_SYNC_C_MARK,
2622};
2623static const unsigned int msiof1_ss1_c_pins[] = {
2624 /* SS1 */
2625 RCAR_GP_PIN(6, 21),
2626};
2627static const unsigned int msiof1_ss1_c_mux[] = {
2628 MSIOF1_SS1_C_MARK,
2629};
2630static const unsigned int msiof1_ss2_c_pins[] = {
2631 /* SS2 */
2632 RCAR_GP_PIN(6, 27),
2633};
2634static const unsigned int msiof1_ss2_c_mux[] = {
2635 MSIOF1_SS2_C_MARK,
2636};
2637static const unsigned int msiof1_txd_c_pins[] = {
2638 /* TXD */
2639 RCAR_GP_PIN(6, 20),
2640};
2641static const unsigned int msiof1_txd_c_mux[] = {
2642 MSIOF1_TXD_C_MARK,
2643};
2644static const unsigned int msiof1_rxd_c_pins[] = {
2645 /* RXD */
2646 RCAR_GP_PIN(6, 19),
2647};
2648static const unsigned int msiof1_rxd_c_mux[] = {
2649 MSIOF1_RXD_C_MARK,
2650};
2651static const unsigned int msiof1_clk_d_pins[] = {
2652 /* SCK */
2653 RCAR_GP_PIN(5, 12),
2654};
2655static const unsigned int msiof1_clk_d_mux[] = {
2656 MSIOF1_SCK_D_MARK,
2657};
2658static const unsigned int msiof1_sync_d_pins[] = {
2659 /* SYNC */
2660 RCAR_GP_PIN(5, 15),
2661};
2662static const unsigned int msiof1_sync_d_mux[] = {
2663 MSIOF1_SYNC_D_MARK,
2664};
2665static const unsigned int msiof1_ss1_d_pins[] = {
2666 /* SS1 */
2667 RCAR_GP_PIN(5, 16),
2668};
2669static const unsigned int msiof1_ss1_d_mux[] = {
2670 MSIOF1_SS1_D_MARK,
2671};
2672static const unsigned int msiof1_ss2_d_pins[] = {
2673 /* SS2 */
2674 RCAR_GP_PIN(5, 21),
2675};
2676static const unsigned int msiof1_ss2_d_mux[] = {
2677 MSIOF1_SS2_D_MARK,
2678};
2679static const unsigned int msiof1_txd_d_pins[] = {
2680 /* TXD */
2681 RCAR_GP_PIN(5, 14),
2682};
2683static const unsigned int msiof1_txd_d_mux[] = {
2684 MSIOF1_TXD_D_MARK,
2685};
2686static const unsigned int msiof1_rxd_d_pins[] = {
2687 /* RXD */
2688 RCAR_GP_PIN(5, 13),
2689};
2690static const unsigned int msiof1_rxd_d_mux[] = {
2691 MSIOF1_RXD_D_MARK,
2692};
2693static const unsigned int msiof1_clk_e_pins[] = {
2694 /* SCK */
2695 RCAR_GP_PIN(3, 0),
2696};
2697static const unsigned int msiof1_clk_e_mux[] = {
2698 MSIOF1_SCK_E_MARK,
2699};
2700static const unsigned int msiof1_sync_e_pins[] = {
2701 /* SYNC */
2702 RCAR_GP_PIN(3, 1),
2703};
2704static const unsigned int msiof1_sync_e_mux[] = {
2705 MSIOF1_SYNC_E_MARK,
2706};
2707static const unsigned int msiof1_ss1_e_pins[] = {
2708 /* SS1 */
2709 RCAR_GP_PIN(3, 4),
2710};
2711static const unsigned int msiof1_ss1_e_mux[] = {
2712 MSIOF1_SS1_E_MARK,
2713};
2714static const unsigned int msiof1_ss2_e_pins[] = {
2715 /* SS2 */
2716 RCAR_GP_PIN(3, 5),
2717};
2718static const unsigned int msiof1_ss2_e_mux[] = {
2719 MSIOF1_SS2_E_MARK,
2720};
2721static const unsigned int msiof1_txd_e_pins[] = {
2722 /* TXD */
2723 RCAR_GP_PIN(3, 3),
2724};
2725static const unsigned int msiof1_txd_e_mux[] = {
2726 MSIOF1_TXD_E_MARK,
2727};
2728static const unsigned int msiof1_rxd_e_pins[] = {
2729 /* RXD */
2730 RCAR_GP_PIN(3, 2),
2731};
2732static const unsigned int msiof1_rxd_e_mux[] = {
2733 MSIOF1_RXD_E_MARK,
2734};
2735static const unsigned int msiof1_clk_f_pins[] = {
2736 /* SCK */
2737 RCAR_GP_PIN(5, 23),
2738};
2739static const unsigned int msiof1_clk_f_mux[] = {
2740 MSIOF1_SCK_F_MARK,
2741};
2742static const unsigned int msiof1_sync_f_pins[] = {
2743 /* SYNC */
2744 RCAR_GP_PIN(5, 24),
2745};
2746static const unsigned int msiof1_sync_f_mux[] = {
2747 MSIOF1_SYNC_F_MARK,
2748};
2749static const unsigned int msiof1_ss1_f_pins[] = {
2750 /* SS1 */
2751 RCAR_GP_PIN(6, 1),
2752};
2753static const unsigned int msiof1_ss1_f_mux[] = {
2754 MSIOF1_SS1_F_MARK,
2755};
2756static const unsigned int msiof1_ss2_f_pins[] = {
2757 /* SS2 */
2758 RCAR_GP_PIN(6, 2),
2759};
2760static const unsigned int msiof1_ss2_f_mux[] = {
2761 MSIOF1_SS2_F_MARK,
2762};
2763static const unsigned int msiof1_txd_f_pins[] = {
2764 /* TXD */
2765 RCAR_GP_PIN(6, 0),
2766};
2767static const unsigned int msiof1_txd_f_mux[] = {
2768 MSIOF1_TXD_F_MARK,
2769};
2770static const unsigned int msiof1_rxd_f_pins[] = {
2771 /* RXD */
2772 RCAR_GP_PIN(5, 25),
2773};
2774static const unsigned int msiof1_rxd_f_mux[] = {
2775 MSIOF1_RXD_F_MARK,
2776};
2777static const unsigned int msiof1_clk_g_pins[] = {
2778 /* SCK */
2779 RCAR_GP_PIN(3, 6),
2780};
2781static const unsigned int msiof1_clk_g_mux[] = {
2782 MSIOF1_SCK_G_MARK,
2783};
2784static const unsigned int msiof1_sync_g_pins[] = {
2785 /* SYNC */
2786 RCAR_GP_PIN(3, 7),
2787};
2788static const unsigned int msiof1_sync_g_mux[] = {
2789 MSIOF1_SYNC_G_MARK,
2790};
2791static const unsigned int msiof1_ss1_g_pins[] = {
2792 /* SS1 */
2793 RCAR_GP_PIN(3, 10),
2794};
2795static const unsigned int msiof1_ss1_g_mux[] = {
2796 MSIOF1_SS1_G_MARK,
2797};
2798static const unsigned int msiof1_ss2_g_pins[] = {
2799 /* SS2 */
2800 RCAR_GP_PIN(3, 11),
2801};
2802static const unsigned int msiof1_ss2_g_mux[] = {
2803 MSIOF1_SS2_G_MARK,
2804};
2805static const unsigned int msiof1_txd_g_pins[] = {
2806 /* TXD */
2807 RCAR_GP_PIN(3, 9),
2808};
2809static const unsigned int msiof1_txd_g_mux[] = {
2810 MSIOF1_TXD_G_MARK,
2811};
2812static const unsigned int msiof1_rxd_g_pins[] = {
2813 /* RXD */
2814 RCAR_GP_PIN(3, 8),
2815};
2816static const unsigned int msiof1_rxd_g_mux[] = {
2817 MSIOF1_RXD_G_MARK,
2818};
2819/* - MSIOF2 ----------------------------------------------------------------- */
2820static const unsigned int msiof2_clk_a_pins[] = {
2821 /* SCK */
2822 RCAR_GP_PIN(1, 9),
2823};
2824static const unsigned int msiof2_clk_a_mux[] = {
2825 MSIOF2_SCK_A_MARK,
2826};
2827static const unsigned int msiof2_sync_a_pins[] = {
2828 /* SYNC */
2829 RCAR_GP_PIN(1, 8),
2830};
2831static const unsigned int msiof2_sync_a_mux[] = {
2832 MSIOF2_SYNC_A_MARK,
2833};
2834static const unsigned int msiof2_ss1_a_pins[] = {
2835 /* SS1 */
2836 RCAR_GP_PIN(1, 6),
2837};
2838static const unsigned int msiof2_ss1_a_mux[] = {
2839 MSIOF2_SS1_A_MARK,
2840};
2841static const unsigned int msiof2_ss2_a_pins[] = {
2842 /* SS2 */
2843 RCAR_GP_PIN(1, 7),
2844};
2845static const unsigned int msiof2_ss2_a_mux[] = {
2846 MSIOF2_SS2_A_MARK,
2847};
2848static const unsigned int msiof2_txd_a_pins[] = {
2849 /* TXD */
2850 RCAR_GP_PIN(1, 11),
2851};
2852static const unsigned int msiof2_txd_a_mux[] = {
2853 MSIOF2_TXD_A_MARK,
2854};
2855static const unsigned int msiof2_rxd_a_pins[] = {
2856 /* RXD */
2857 RCAR_GP_PIN(1, 10),
2858};
2859static const unsigned int msiof2_rxd_a_mux[] = {
2860 MSIOF2_RXD_A_MARK,
2861};
2862static const unsigned int msiof2_clk_b_pins[] = {
2863 /* SCK */
2864 RCAR_GP_PIN(0, 4),
2865};
2866static const unsigned int msiof2_clk_b_mux[] = {
2867 MSIOF2_SCK_B_MARK,
2868};
2869static const unsigned int msiof2_sync_b_pins[] = {
2870 /* SYNC */
2871 RCAR_GP_PIN(0, 5),
2872};
2873static const unsigned int msiof2_sync_b_mux[] = {
2874 MSIOF2_SYNC_B_MARK,
2875};
2876static const unsigned int msiof2_ss1_b_pins[] = {
2877 /* SS1 */
2878 RCAR_GP_PIN(0, 0),
2879};
2880static const unsigned int msiof2_ss1_b_mux[] = {
2881 MSIOF2_SS1_B_MARK,
2882};
2883static const unsigned int msiof2_ss2_b_pins[] = {
2884 /* SS2 */
2885 RCAR_GP_PIN(0, 1),
2886};
2887static const unsigned int msiof2_ss2_b_mux[] = {
2888 MSIOF2_SS2_B_MARK,
2889};
2890static const unsigned int msiof2_txd_b_pins[] = {
2891 /* TXD */
2892 RCAR_GP_PIN(0, 7),
2893};
2894static const unsigned int msiof2_txd_b_mux[] = {
2895 MSIOF2_TXD_B_MARK,
2896};
2897static const unsigned int msiof2_rxd_b_pins[] = {
2898 /* RXD */
2899 RCAR_GP_PIN(0, 6),
2900};
2901static const unsigned int msiof2_rxd_b_mux[] = {
2902 MSIOF2_RXD_B_MARK,
2903};
2904static const unsigned int msiof2_clk_c_pins[] = {
2905 /* SCK */
2906 RCAR_GP_PIN(2, 12),
2907};
2908static const unsigned int msiof2_clk_c_mux[] = {
2909 MSIOF2_SCK_C_MARK,
2910};
2911static const unsigned int msiof2_sync_c_pins[] = {
2912 /* SYNC */
2913 RCAR_GP_PIN(2, 11),
2914};
2915static const unsigned int msiof2_sync_c_mux[] = {
2916 MSIOF2_SYNC_C_MARK,
2917};
2918static const unsigned int msiof2_ss1_c_pins[] = {
2919 /* SS1 */
2920 RCAR_GP_PIN(2, 10),
2921};
2922static const unsigned int msiof2_ss1_c_mux[] = {
2923 MSIOF2_SS1_C_MARK,
2924};
2925static const unsigned int msiof2_ss2_c_pins[] = {
2926 /* SS2 */
2927 RCAR_GP_PIN(2, 9),
2928};
2929static const unsigned int msiof2_ss2_c_mux[] = {
2930 MSIOF2_SS2_C_MARK,
2931};
2932static const unsigned int msiof2_txd_c_pins[] = {
2933 /* TXD */
2934 RCAR_GP_PIN(2, 14),
2935};
2936static const unsigned int msiof2_txd_c_mux[] = {
2937 MSIOF2_TXD_C_MARK,
2938};
2939static const unsigned int msiof2_rxd_c_pins[] = {
2940 /* RXD */
2941 RCAR_GP_PIN(2, 13),
2942};
2943static const unsigned int msiof2_rxd_c_mux[] = {
2944 MSIOF2_RXD_C_MARK,
2945};
2946static const unsigned int msiof2_clk_d_pins[] = {
2947 /* SCK */
2948 RCAR_GP_PIN(0, 8),
2949};
2950static const unsigned int msiof2_clk_d_mux[] = {
2951 MSIOF2_SCK_D_MARK,
2952};
2953static const unsigned int msiof2_sync_d_pins[] = {
2954 /* SYNC */
2955 RCAR_GP_PIN(0, 9),
2956};
2957static const unsigned int msiof2_sync_d_mux[] = {
2958 MSIOF2_SYNC_D_MARK,
2959};
2960static const unsigned int msiof2_ss1_d_pins[] = {
2961 /* SS1 */
2962 RCAR_GP_PIN(0, 12),
2963};
2964static const unsigned int msiof2_ss1_d_mux[] = {
2965 MSIOF2_SS1_D_MARK,
2966};
2967static const unsigned int msiof2_ss2_d_pins[] = {
2968 /* SS2 */
2969 RCAR_GP_PIN(0, 13),
2970};
2971static const unsigned int msiof2_ss2_d_mux[] = {
2972 MSIOF2_SS2_D_MARK,
2973};
2974static const unsigned int msiof2_txd_d_pins[] = {
2975 /* TXD */
2976 RCAR_GP_PIN(0, 11),
2977};
2978static const unsigned int msiof2_txd_d_mux[] = {
2979 MSIOF2_TXD_D_MARK,
2980};
2981static const unsigned int msiof2_rxd_d_pins[] = {
2982 /* RXD */
2983 RCAR_GP_PIN(0, 10),
2984};
2985static const unsigned int msiof2_rxd_d_mux[] = {
2986 MSIOF2_RXD_D_MARK,
2987};
2988/* - MSIOF3 ----------------------------------------------------------------- */
2989static const unsigned int msiof3_clk_a_pins[] = {
2990 /* SCK */
2991 RCAR_GP_PIN(0, 0),
2992};
2993static const unsigned int msiof3_clk_a_mux[] = {
2994 MSIOF3_SCK_A_MARK,
2995};
2996static const unsigned int msiof3_sync_a_pins[] = {
2997 /* SYNC */
2998 RCAR_GP_PIN(0, 1),
2999};
3000static const unsigned int msiof3_sync_a_mux[] = {
3001 MSIOF3_SYNC_A_MARK,
3002};
3003static const unsigned int msiof3_ss1_a_pins[] = {
3004 /* SS1 */
3005 RCAR_GP_PIN(0, 14),
3006};
3007static const unsigned int msiof3_ss1_a_mux[] = {
3008 MSIOF3_SS1_A_MARK,
3009};
3010static const unsigned int msiof3_ss2_a_pins[] = {
3011 /* SS2 */
3012 RCAR_GP_PIN(0, 15),
3013};
3014static const unsigned int msiof3_ss2_a_mux[] = {
3015 MSIOF3_SS2_A_MARK,
3016};
3017static const unsigned int msiof3_txd_a_pins[] = {
3018 /* TXD */
3019 RCAR_GP_PIN(0, 3),
3020};
3021static const unsigned int msiof3_txd_a_mux[] = {
3022 MSIOF3_TXD_A_MARK,
3023};
3024static const unsigned int msiof3_rxd_a_pins[] = {
3025 /* RXD */
3026 RCAR_GP_PIN(0, 2),
3027};
3028static const unsigned int msiof3_rxd_a_mux[] = {
3029 MSIOF3_RXD_A_MARK,
3030};
3031static const unsigned int msiof3_clk_b_pins[] = {
3032 /* SCK */
3033 RCAR_GP_PIN(1, 2),
3034};
3035static const unsigned int msiof3_clk_b_mux[] = {
3036 MSIOF3_SCK_B_MARK,
3037};
3038static const unsigned int msiof3_sync_b_pins[] = {
3039 /* SYNC */
3040 RCAR_GP_PIN(1, 0),
3041};
3042static const unsigned int msiof3_sync_b_mux[] = {
3043 MSIOF3_SYNC_B_MARK,
3044};
3045static const unsigned int msiof3_ss1_b_pins[] = {
3046 /* SS1 */
3047 RCAR_GP_PIN(1, 4),
3048};
3049static const unsigned int msiof3_ss1_b_mux[] = {
3050 MSIOF3_SS1_B_MARK,
3051};
3052static const unsigned int msiof3_ss2_b_pins[] = {
3053 /* SS2 */
3054 RCAR_GP_PIN(1, 5),
3055};
3056static const unsigned int msiof3_ss2_b_mux[] = {
3057 MSIOF3_SS2_B_MARK,
3058};
3059static const unsigned int msiof3_txd_b_pins[] = {
3060 /* TXD */
3061 RCAR_GP_PIN(1, 1),
3062};
3063static const unsigned int msiof3_txd_b_mux[] = {
3064 MSIOF3_TXD_B_MARK,
3065};
3066static const unsigned int msiof3_rxd_b_pins[] = {
3067 /* RXD */
3068 RCAR_GP_PIN(1, 3),
3069};
3070static const unsigned int msiof3_rxd_b_mux[] = {
3071 MSIOF3_RXD_B_MARK,
3072};
3073static const unsigned int msiof3_clk_c_pins[] = {
3074 /* SCK */
3075 RCAR_GP_PIN(1, 12),
3076};
3077static const unsigned int msiof3_clk_c_mux[] = {
3078 MSIOF3_SCK_C_MARK,
3079};
3080static const unsigned int msiof3_sync_c_pins[] = {
3081 /* SYNC */
3082 RCAR_GP_PIN(1, 13),
3083};
3084static const unsigned int msiof3_sync_c_mux[] = {
3085 MSIOF3_SYNC_C_MARK,
3086};
3087static const unsigned int msiof3_txd_c_pins[] = {
3088 /* TXD */
3089 RCAR_GP_PIN(1, 15),
3090};
3091static const unsigned int msiof3_txd_c_mux[] = {
3092 MSIOF3_TXD_C_MARK,
3093};
3094static const unsigned int msiof3_rxd_c_pins[] = {
3095 /* RXD */
3096 RCAR_GP_PIN(1, 14),
3097};
3098static const unsigned int msiof3_rxd_c_mux[] = {
3099 MSIOF3_RXD_C_MARK,
3100};
3101static const unsigned int msiof3_clk_d_pins[] = {
3102 /* SCK */
3103 RCAR_GP_PIN(1, 22),
3104};
3105static const unsigned int msiof3_clk_d_mux[] = {
3106 MSIOF3_SCK_D_MARK,
3107};
3108static const unsigned int msiof3_sync_d_pins[] = {
3109 /* SYNC */
3110 RCAR_GP_PIN(1, 23),
3111};
3112static const unsigned int msiof3_sync_d_mux[] = {
3113 MSIOF3_SYNC_D_MARK,
3114};
3115static const unsigned int msiof3_ss1_d_pins[] = {
3116 /* SS1 */
3117 RCAR_GP_PIN(1, 26),
3118};
3119static const unsigned int msiof3_ss1_d_mux[] = {
3120 MSIOF3_SS1_D_MARK,
3121};
3122static const unsigned int msiof3_txd_d_pins[] = {
3123 /* TXD */
3124 RCAR_GP_PIN(1, 25),
3125};
3126static const unsigned int msiof3_txd_d_mux[] = {
3127 MSIOF3_TXD_D_MARK,
3128};
3129static const unsigned int msiof3_rxd_d_pins[] = {
3130 /* RXD */
3131 RCAR_GP_PIN(1, 24),
3132};
3133static const unsigned int msiof3_rxd_d_mux[] = {
3134 MSIOF3_RXD_D_MARK,
3135};
3136
3137static const unsigned int msiof3_clk_e_pins[] = {
3138 /* SCK */
3139 RCAR_GP_PIN(2, 3),
3140};
3141static const unsigned int msiof3_clk_e_mux[] = {
3142 MSIOF3_SCK_E_MARK,
3143};
3144static const unsigned int msiof3_sync_e_pins[] = {
3145 /* SYNC */
3146 RCAR_GP_PIN(2, 2),
3147};
3148static const unsigned int msiof3_sync_e_mux[] = {
3149 MSIOF3_SYNC_E_MARK,
3150};
3151static const unsigned int msiof3_ss1_e_pins[] = {
3152 /* SS1 */
3153 RCAR_GP_PIN(2, 1),
3154};
3155static const unsigned int msiof3_ss1_e_mux[] = {
3156 MSIOF3_SS1_E_MARK,
3157};
3158static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3159 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3160 RCAR_GP_PIN(2, 0),
3161};
3162static const unsigned int msiof3_ss2_e_mux[] = {
3163 MSIOF3_SS2_E_MARK,
3164};
3165static const unsigned int msiof3_txd_e_pins[] = {
3166 /* TXD */
3167 RCAR_GP_PIN(2, 5),
3168};
3169static const unsigned int msiof3_txd_e_mux[] = {
3170 MSIOF3_TXD_E_MARK,
3171};
3172static const unsigned int msiof3_rxd_e_pins[] = {
3173 /* RXD */
3174 RCAR_GP_PIN(2, 4),
3175};
3176static const unsigned int msiof3_rxd_e_mux[] = {
3177 MSIOF3_RXD_E_MARK,
3178};
3179
3180/* - PWM0 --------------------------------------------------------------------*/
3181static const unsigned int pwm0_pins[] = {
3182 /* PWM */
3183 RCAR_GP_PIN(2, 6),
3184};
3185static const unsigned int pwm0_mux[] = {
3186 PWM0_MARK,
3187};
3188/* - PWM1 --------------------------------------------------------------------*/
3189static const unsigned int pwm1_a_pins[] = {
3190 /* PWM */
3191 RCAR_GP_PIN(2, 7),
3192};
3193static const unsigned int pwm1_a_mux[] = {
3194 PWM1_A_MARK,
3195};
3196static const unsigned int pwm1_b_pins[] = {
3197 /* PWM */
3198 RCAR_GP_PIN(1, 8),
3199};
3200static const unsigned int pwm1_b_mux[] = {
3201 PWM1_B_MARK,
3202};
3203/* - PWM2 --------------------------------------------------------------------*/
3204static const unsigned int pwm2_a_pins[] = {
3205 /* PWM */
3206 RCAR_GP_PIN(2, 8),
3207};
3208static const unsigned int pwm2_a_mux[] = {
3209 PWM2_A_MARK,
3210};
3211static const unsigned int pwm2_b_pins[] = {
3212 /* PWM */
3213 RCAR_GP_PIN(1, 11),
3214};
3215static const unsigned int pwm2_b_mux[] = {
3216 PWM2_B_MARK,
3217};
3218/* - PWM3 --------------------------------------------------------------------*/
3219static const unsigned int pwm3_a_pins[] = {
3220 /* PWM */
3221 RCAR_GP_PIN(1, 0),
3222};
3223static const unsigned int pwm3_a_mux[] = {
3224 PWM3_A_MARK,
3225};
3226static const unsigned int pwm3_b_pins[] = {
3227 /* PWM */
3228 RCAR_GP_PIN(2, 2),
3229};
3230static const unsigned int pwm3_b_mux[] = {
3231 PWM3_B_MARK,
3232};
3233/* - PWM4 --------------------------------------------------------------------*/
3234static const unsigned int pwm4_a_pins[] = {
3235 /* PWM */
3236 RCAR_GP_PIN(1, 1),
3237};
3238static const unsigned int pwm4_a_mux[] = {
3239 PWM4_A_MARK,
3240};
3241static const unsigned int pwm4_b_pins[] = {
3242 /* PWM */
3243 RCAR_GP_PIN(2, 3),
3244};
3245static const unsigned int pwm4_b_mux[] = {
3246 PWM4_B_MARK,
3247};
3248/* - PWM5 --------------------------------------------------------------------*/
3249static const unsigned int pwm5_a_pins[] = {
3250 /* PWM */
3251 RCAR_GP_PIN(1, 2),
3252};
3253static const unsigned int pwm5_a_mux[] = {
3254 PWM5_A_MARK,
3255};
3256static const unsigned int pwm5_b_pins[] = {
3257 /* PWM */
3258 RCAR_GP_PIN(2, 4),
3259};
3260static const unsigned int pwm5_b_mux[] = {
3261 PWM5_B_MARK,
3262};
3263/* - PWM6 --------------------------------------------------------------------*/
3264static const unsigned int pwm6_a_pins[] = {
3265 /* PWM */
3266 RCAR_GP_PIN(1, 3),
3267};
3268static const unsigned int pwm6_a_mux[] = {
3269 PWM6_A_MARK,
3270};
3271static const unsigned int pwm6_b_pins[] = {
3272 /* PWM */
3273 RCAR_GP_PIN(2, 5),
3274};
3275static const unsigned int pwm6_b_mux[] = {
3276 PWM6_B_MARK,
3277};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]3278#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3279
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3280/* - QSPI0 ------------------------------------------------------------------ */
3281static const unsigned int qspi0_ctrl_pins[] = {
3282 /* QSPI0_SPCLK, QSPI0_SSL */
3283 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3284};
3285static const unsigned int qspi0_ctrl_mux[] = {
3286 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3287};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3288static const unsigned int qspi0_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3289 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3290 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3291 /* QSPI0_IO2, QSPI0_IO3 */
3292 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3293};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3294static const unsigned int qspi0_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3295 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3296 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3297};
3298/* - QSPI1 ------------------------------------------------------------------ */
3299static const unsigned int qspi1_ctrl_pins[] = {
3300 /* QSPI1_SPCLK, QSPI1_SSL */
3301 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3302};
3303static const unsigned int qspi1_ctrl_mux[] = {
3304 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3305};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3306static const unsigned int qspi1_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3307 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3308 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3309 /* QSPI1_IO2, QSPI1_IO3 */
3310 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3311};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3312static const unsigned int qspi1_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3313 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3314 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3315};
3316
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3317/* - SCIF0 ------------------------------------------------------------------ */
3318static const unsigned int scif0_data_pins[] = {
3319 /* RX, TX */
3320 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3321};
3322static const unsigned int scif0_data_mux[] = {
3323 RX0_MARK, TX0_MARK,
3324};
3325static const unsigned int scif0_clk_pins[] = {
3326 /* SCK */
3327 RCAR_GP_PIN(5, 0),
3328};
3329static const unsigned int scif0_clk_mux[] = {
3330 SCK0_MARK,
3331};
3332static const unsigned int scif0_ctrl_pins[] = {
3333 /* RTS, CTS */
3334 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3335};
3336static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3337 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3338};
3339/* - SCIF1 ------------------------------------------------------------------ */
3340static const unsigned int scif1_data_a_pins[] = {
3341 /* RX, TX */
3342 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3343};
3344static const unsigned int scif1_data_a_mux[] = {
3345 RX1_A_MARK, TX1_A_MARK,
3346};
3347static const unsigned int scif1_clk_pins[] = {
3348 /* SCK */
3349 RCAR_GP_PIN(6, 21),
3350};
3351static const unsigned int scif1_clk_mux[] = {
3352 SCK1_MARK,
3353};
3354static const unsigned int scif1_ctrl_pins[] = {
3355 /* RTS, CTS */
3356 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3357};
3358static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3359 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3360};
3361
3362static const unsigned int scif1_data_b_pins[] = {
3363 /* RX, TX */
3364 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3365};
3366static const unsigned int scif1_data_b_mux[] = {
3367 RX1_B_MARK, TX1_B_MARK,
3368};
3369/* - SCIF2 ------------------------------------------------------------------ */
3370static const unsigned int scif2_data_a_pins[] = {
3371 /* RX, TX */
3372 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3373};
3374static const unsigned int scif2_data_a_mux[] = {
3375 RX2_A_MARK, TX2_A_MARK,
3376};
3377static const unsigned int scif2_clk_pins[] = {
3378 /* SCK */
3379 RCAR_GP_PIN(5, 9),
3380};
3381static const unsigned int scif2_clk_mux[] = {
3382 SCK2_MARK,
3383};
3384static const unsigned int scif2_data_b_pins[] = {
3385 /* RX, TX */
3386 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3387};
3388static const unsigned int scif2_data_b_mux[] = {
3389 RX2_B_MARK, TX2_B_MARK,
3390};
3391/* - SCIF3 ------------------------------------------------------------------ */
3392static const unsigned int scif3_data_a_pins[] = {
3393 /* RX, TX */
3394 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3395};
3396static const unsigned int scif3_data_a_mux[] = {
3397 RX3_A_MARK, TX3_A_MARK,
3398};
3399static const unsigned int scif3_clk_pins[] = {
3400 /* SCK */
3401 RCAR_GP_PIN(1, 22),
3402};
3403static const unsigned int scif3_clk_mux[] = {
3404 SCK3_MARK,
3405};
3406static const unsigned int scif3_ctrl_pins[] = {
3407 /* RTS, CTS */
3408 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3409};
3410static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3411 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3412};
3413static const unsigned int scif3_data_b_pins[] = {
3414 /* RX, TX */
3415 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3416};
3417static const unsigned int scif3_data_b_mux[] = {
3418 RX3_B_MARK, TX3_B_MARK,
3419};
3420/* - SCIF4 ------------------------------------------------------------------ */
3421static const unsigned int scif4_data_a_pins[] = {
3422 /* RX, TX */
3423 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3424};
3425static const unsigned int scif4_data_a_mux[] = {
3426 RX4_A_MARK, TX4_A_MARK,
3427};
3428static const unsigned int scif4_clk_a_pins[] = {
3429 /* SCK */
3430 RCAR_GP_PIN(2, 10),
3431};
3432static const unsigned int scif4_clk_a_mux[] = {
3433 SCK4_A_MARK,
3434};
3435static const unsigned int scif4_ctrl_a_pins[] = {
3436 /* RTS, CTS */
3437 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3438};
3439static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3440 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3441};
3442static const unsigned int scif4_data_b_pins[] = {
3443 /* RX, TX */
3444 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3445};
3446static const unsigned int scif4_data_b_mux[] = {
3447 RX4_B_MARK, TX4_B_MARK,
3448};
3449static const unsigned int scif4_clk_b_pins[] = {
3450 /* SCK */
3451 RCAR_GP_PIN(1, 5),
3452};
3453static const unsigned int scif4_clk_b_mux[] = {
3454 SCK4_B_MARK,
3455};
3456static const unsigned int scif4_ctrl_b_pins[] = {
3457 /* RTS, CTS */
3458 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3459};
3460static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3461 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3462};
3463static const unsigned int scif4_data_c_pins[] = {
3464 /* RX, TX */
3465 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3466};
3467static const unsigned int scif4_data_c_mux[] = {
3468 RX4_C_MARK, TX4_C_MARK,
3469};
3470static const unsigned int scif4_clk_c_pins[] = {
3471 /* SCK */
3472 RCAR_GP_PIN(0, 8),
3473};
3474static const unsigned int scif4_clk_c_mux[] = {
3475 SCK4_C_MARK,
3476};
3477static const unsigned int scif4_ctrl_c_pins[] = {
3478 /* RTS, CTS */
3479 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3480};
3481static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3482 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3483};
3484/* - SCIF5 ------------------------------------------------------------------ */
3485static const unsigned int scif5_data_a_pins[] = {
3486 /* RX, TX */
3487 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3488};
3489static const unsigned int scif5_data_a_mux[] = {
3490 RX5_A_MARK, TX5_A_MARK,
3491};
3492static const unsigned int scif5_clk_a_pins[] = {
3493 /* SCK */
3494 RCAR_GP_PIN(6, 21),
3495};
3496static const unsigned int scif5_clk_a_mux[] = {
3497 SCK5_A_MARK,
3498};
3499
3500static const unsigned int scif5_data_b_pins[] = {
3501 /* RX, TX */
3502 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3503};
3504static const unsigned int scif5_data_b_mux[] = {
3505 RX5_B_MARK, TX5_B_MARK,
3506};
3507static const unsigned int scif5_clk_b_pins[] = {
3508 /* SCK */
3509 RCAR_GP_PIN(5, 0),
3510};
3511static const unsigned int scif5_clk_b_mux[] = {
3512 SCK5_B_MARK,
3513};
3514
3515/* - SCIF Clock ------------------------------------------------------------- */
3516static const unsigned int scif_clk_a_pins[] = {
3517 /* SCIF_CLK */
3518 RCAR_GP_PIN(6, 23),
3519};
3520static const unsigned int scif_clk_a_mux[] = {
3521 SCIF_CLK_A_MARK,
3522};
3523static const unsigned int scif_clk_b_pins[] = {
3524 /* SCIF_CLK */
3525 RCAR_GP_PIN(5, 9),
3526};
3527static const unsigned int scif_clk_b_mux[] = {
3528 SCIF_CLK_B_MARK,
3529};
3530
3531/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3532static const unsigned int sdhi0_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3533 /* D[0:3] */
3534 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3535 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3536};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3537static const unsigned int sdhi0_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3538 SD0_DAT0_MARK, SD0_DAT1_MARK,
3539 SD0_DAT2_MARK, SD0_DAT3_MARK,
3540};
3541static const unsigned int sdhi0_ctrl_pins[] = {
3542 /* CLK, CMD */
3543 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3544};
3545static const unsigned int sdhi0_ctrl_mux[] = {
3546 SD0_CLK_MARK, SD0_CMD_MARK,
3547};
3548static const unsigned int sdhi0_cd_pins[] = {
3549 /* CD */
3550 RCAR_GP_PIN(3, 12),
3551};
3552static const unsigned int sdhi0_cd_mux[] = {
3553 SD0_CD_MARK,
3554};
3555static const unsigned int sdhi0_wp_pins[] = {
3556 /* WP */
3557 RCAR_GP_PIN(3, 13),
3558};
3559static const unsigned int sdhi0_wp_mux[] = {
3560 SD0_WP_MARK,
3561};
3562/* - SDHI1 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3563static const unsigned int sdhi1_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3564 /* D[0:3] */
3565 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3566 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3567};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3568static const unsigned int sdhi1_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3569 SD1_DAT0_MARK, SD1_DAT1_MARK,
3570 SD1_DAT2_MARK, SD1_DAT3_MARK,
3571};
3572static const unsigned int sdhi1_ctrl_pins[] = {
3573 /* CLK, CMD */
3574 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3575};
3576static const unsigned int sdhi1_ctrl_mux[] = {
3577 SD1_CLK_MARK, SD1_CMD_MARK,
3578};
3579static const unsigned int sdhi1_cd_pins[] = {
3580 /* CD */
3581 RCAR_GP_PIN(3, 14),
3582};
3583static const unsigned int sdhi1_cd_mux[] = {
3584 SD1_CD_MARK,
3585};
3586static const unsigned int sdhi1_wp_pins[] = {
3587 /* WP */
3588 RCAR_GP_PIN(3, 15),
3589};
3590static const unsigned int sdhi1_wp_mux[] = {
3591 SD1_WP_MARK,
3592};
3593/* - SDHI2 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3594static const unsigned int sdhi2_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3595 /* D[0:7] */
3596 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3597 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3598 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3599 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3600};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3601static const unsigned int sdhi2_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3602 SD2_DAT0_MARK, SD2_DAT1_MARK,
3603 SD2_DAT2_MARK, SD2_DAT3_MARK,
3604 SD2_DAT4_MARK, SD2_DAT5_MARK,
3605 SD2_DAT6_MARK, SD2_DAT7_MARK,
3606};
3607static const unsigned int sdhi2_ctrl_pins[] = {
3608 /* CLK, CMD */
3609 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3610};
3611static const unsigned int sdhi2_ctrl_mux[] = {
3612 SD2_CLK_MARK, SD2_CMD_MARK,
3613};
3614static const unsigned int sdhi2_cd_a_pins[] = {
3615 /* CD */
3616 RCAR_GP_PIN(4, 13),
3617};
3618static const unsigned int sdhi2_cd_a_mux[] = {
3619 SD2_CD_A_MARK,
3620};
3621static const unsigned int sdhi2_cd_b_pins[] = {
3622 /* CD */
3623 RCAR_GP_PIN(5, 10),
3624};
3625static const unsigned int sdhi2_cd_b_mux[] = {
3626 SD2_CD_B_MARK,
3627};
3628static const unsigned int sdhi2_wp_a_pins[] = {
3629 /* WP */
3630 RCAR_GP_PIN(4, 14),
3631};
3632static const unsigned int sdhi2_wp_a_mux[] = {
3633 SD2_WP_A_MARK,
3634};
3635static const unsigned int sdhi2_wp_b_pins[] = {
3636 /* WP */
3637 RCAR_GP_PIN(5, 11),
3638};
3639static const unsigned int sdhi2_wp_b_mux[] = {
3640 SD2_WP_B_MARK,
3641};
3642static const unsigned int sdhi2_ds_pins[] = {
3643 /* DS */
3644 RCAR_GP_PIN(4, 6),
3645};
3646static const unsigned int sdhi2_ds_mux[] = {
3647 SD2_DS_MARK,
3648};
3649/* - SDHI3 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3650static const unsigned int sdhi3_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3651 /* D[0:7] */
3652 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3653 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3654 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3655 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3656};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3657static const unsigned int sdhi3_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3658 SD3_DAT0_MARK, SD3_DAT1_MARK,
3659 SD3_DAT2_MARK, SD3_DAT3_MARK,
3660 SD3_DAT4_MARK, SD3_DAT5_MARK,
3661 SD3_DAT6_MARK, SD3_DAT7_MARK,
3662};
3663static const unsigned int sdhi3_ctrl_pins[] = {
3664 /* CLK, CMD */
3665 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3666};
3667static const unsigned int sdhi3_ctrl_mux[] = {
3668 SD3_CLK_MARK, SD3_CMD_MARK,
3669};
3670static const unsigned int sdhi3_cd_pins[] = {
3671 /* CD */
3672 RCAR_GP_PIN(4, 15),
3673};
3674static const unsigned int sdhi3_cd_mux[] = {
3675 SD3_CD_MARK,
3676};
3677static const unsigned int sdhi3_wp_pins[] = {
3678 /* WP */
3679 RCAR_GP_PIN(4, 16),
3680};
3681static const unsigned int sdhi3_wp_mux[] = {
3682 SD3_WP_MARK,
3683};
3684static const unsigned int sdhi3_ds_pins[] = {
3685 /* DS */
3686 RCAR_GP_PIN(4, 17),
3687};
3688static const unsigned int sdhi3_ds_mux[] = {
3689 SD3_DS_MARK,
3690};
3691
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]3692#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3693/* - SSI -------------------------------------------------------------------- */
3694static const unsigned int ssi0_data_pins[] = {
3695 /* SDATA */
3696 RCAR_GP_PIN(6, 2),
3697};
3698static const unsigned int ssi0_data_mux[] = {
3699 SSI_SDATA0_MARK,
3700};
3701static const unsigned int ssi01239_ctrl_pins[] = {
3702 /* SCK, WS */
3703 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3704};
3705static const unsigned int ssi01239_ctrl_mux[] = {
3706 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3707};
3708static const unsigned int ssi1_data_a_pins[] = {
3709 /* SDATA */
3710 RCAR_GP_PIN(6, 3),
3711};
3712static const unsigned int ssi1_data_a_mux[] = {
3713 SSI_SDATA1_A_MARK,
3714};
3715static const unsigned int ssi1_data_b_pins[] = {
3716 /* SDATA */
3717 RCAR_GP_PIN(5, 12),
3718};
3719static const unsigned int ssi1_data_b_mux[] = {
3720 SSI_SDATA1_B_MARK,
3721};
3722static const unsigned int ssi1_ctrl_a_pins[] = {
3723 /* SCK, WS */
3724 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3725};
3726static const unsigned int ssi1_ctrl_a_mux[] = {
3727 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3728};
3729static const unsigned int ssi1_ctrl_b_pins[] = {
3730 /* SCK, WS */
3731 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3732};
3733static const unsigned int ssi1_ctrl_b_mux[] = {
3734 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3735};
3736static const unsigned int ssi2_data_a_pins[] = {
3737 /* SDATA */
3738 RCAR_GP_PIN(6, 4),
3739};
3740static const unsigned int ssi2_data_a_mux[] = {
3741 SSI_SDATA2_A_MARK,
3742};
3743static const unsigned int ssi2_data_b_pins[] = {
3744 /* SDATA */
3745 RCAR_GP_PIN(5, 13),
3746};
3747static const unsigned int ssi2_data_b_mux[] = {
3748 SSI_SDATA2_B_MARK,
3749};
3750static const unsigned int ssi2_ctrl_a_pins[] = {
3751 /* SCK, WS */
3752 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3753};
3754static const unsigned int ssi2_ctrl_a_mux[] = {
3755 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3756};
3757static const unsigned int ssi2_ctrl_b_pins[] = {
3758 /* SCK, WS */
3759 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3760};
3761static const unsigned int ssi2_ctrl_b_mux[] = {
3762 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3763};
3764static const unsigned int ssi3_data_pins[] = {
3765 /* SDATA */
3766 RCAR_GP_PIN(6, 7),
3767};
3768static const unsigned int ssi3_data_mux[] = {
3769 SSI_SDATA3_MARK,
3770};
3771static const unsigned int ssi349_ctrl_pins[] = {
3772 /* SCK, WS */
3773 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3774};
3775static const unsigned int ssi349_ctrl_mux[] = {
3776 SSI_SCK349_MARK, SSI_WS349_MARK,
3777};
3778static const unsigned int ssi4_data_pins[] = {
3779 /* SDATA */
3780 RCAR_GP_PIN(6, 10),
3781};
3782static const unsigned int ssi4_data_mux[] = {
3783 SSI_SDATA4_MARK,
3784};
3785static const unsigned int ssi4_ctrl_pins[] = {
3786 /* SCK, WS */
3787 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3788};
3789static const unsigned int ssi4_ctrl_mux[] = {
3790 SSI_SCK4_MARK, SSI_WS4_MARK,
3791};
3792static const unsigned int ssi5_data_pins[] = {
3793 /* SDATA */
3794 RCAR_GP_PIN(6, 13),
3795};
3796static const unsigned int ssi5_data_mux[] = {
3797 SSI_SDATA5_MARK,
3798};
3799static const unsigned int ssi5_ctrl_pins[] = {
3800 /* SCK, WS */
3801 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3802};
3803static const unsigned int ssi5_ctrl_mux[] = {
3804 SSI_SCK5_MARK, SSI_WS5_MARK,
3805};
3806static const unsigned int ssi6_data_pins[] = {
3807 /* SDATA */
3808 RCAR_GP_PIN(6, 16),
3809};
3810static const unsigned int ssi6_data_mux[] = {
3811 SSI_SDATA6_MARK,
3812};
3813static const unsigned int ssi6_ctrl_pins[] = {
3814 /* SCK, WS */
3815 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3816};
3817static const unsigned int ssi6_ctrl_mux[] = {
3818 SSI_SCK6_MARK, SSI_WS6_MARK,
3819};
3820static const unsigned int ssi7_data_pins[] = {
3821 /* SDATA */
3822 RCAR_GP_PIN(6, 19),
3823};
3824static const unsigned int ssi7_data_mux[] = {
3825 SSI_SDATA7_MARK,
3826};
3827static const unsigned int ssi78_ctrl_pins[] = {
3828 /* SCK, WS */
3829 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3830};
3831static const unsigned int ssi78_ctrl_mux[] = {
3832 SSI_SCK78_MARK, SSI_WS78_MARK,
3833};
3834static const unsigned int ssi8_data_pins[] = {
3835 /* SDATA */
3836 RCAR_GP_PIN(6, 20),
3837};
3838static const unsigned int ssi8_data_mux[] = {
3839 SSI_SDATA8_MARK,
3840};
3841static const unsigned int ssi9_data_a_pins[] = {
3842 /* SDATA */
3843 RCAR_GP_PIN(6, 21),
3844};
3845static const unsigned int ssi9_data_a_mux[] = {
3846 SSI_SDATA9_A_MARK,
3847};
3848static const unsigned int ssi9_data_b_pins[] = {
3849 /* SDATA */
3850 RCAR_GP_PIN(5, 14),
3851};
3852static const unsigned int ssi9_data_b_mux[] = {
3853 SSI_SDATA9_B_MARK,
3854};
3855static const unsigned int ssi9_ctrl_a_pins[] = {
3856 /* SCK, WS */
3857 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3858};
3859static const unsigned int ssi9_ctrl_a_mux[] = {
3860 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3861};
3862static const unsigned int ssi9_ctrl_b_pins[] = {
3863 /* SCK, WS */
3864 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3865};
3866static const unsigned int ssi9_ctrl_b_mux[] = {
3867 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3868};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]3869#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3870
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3871/* - TMU -------------------------------------------------------------------- */
3872static const unsigned int tmu_tclk1_a_pins[] = {
3873 /* TCLK */
3874 RCAR_GP_PIN(6, 23),
3875};
3876static const unsigned int tmu_tclk1_a_mux[] = {
3877 TCLK1_A_MARK,
3878};
3879static const unsigned int tmu_tclk1_b_pins[] = {
3880 /* TCLK */
3881 RCAR_GP_PIN(5, 19),
3882};
3883static const unsigned int tmu_tclk1_b_mux[] = {
3884 TCLK1_B_MARK,
3885};
3886static const unsigned int tmu_tclk2_a_pins[] = {
3887 /* TCLK */
3888 RCAR_GP_PIN(6, 19),
3889};
3890static const unsigned int tmu_tclk2_a_mux[] = {
3891 TCLK2_A_MARK,
3892};
3893static const unsigned int tmu_tclk2_b_pins[] = {
3894 /* TCLK */
3895 RCAR_GP_PIN(6, 28),
3896};
3897static const unsigned int tmu_tclk2_b_mux[] = {
3898 TCLK2_B_MARK,
3899};
3900
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3901/* - TPU ------------------------------------------------------------------- */
3902static const unsigned int tpu_to0_pins[] = {
3903 /* TPU0TO0 */
3904 RCAR_GP_PIN(6, 28),
3905};
3906static const unsigned int tpu_to0_mux[] = {
3907 TPU0TO0_MARK,
3908};
3909static const unsigned int tpu_to1_pins[] = {
3910 /* TPU0TO1 */
3911 RCAR_GP_PIN(6, 29),
3912};
3913static const unsigned int tpu_to1_mux[] = {
3914 TPU0TO1_MARK,
3915};
3916static const unsigned int tpu_to2_pins[] = {
3917 /* TPU0TO2 */
3918 RCAR_GP_PIN(6, 30),
3919};
3920static const unsigned int tpu_to2_mux[] = {
3921 TPU0TO2_MARK,
3922};
3923static const unsigned int tpu_to3_pins[] = {
3924 /* TPU0TO3 */
3925 RCAR_GP_PIN(6, 31),
3926};
3927static const unsigned int tpu_to3_mux[] = {
3928 TPU0TO3_MARK,
3929};
3930
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3931/* - USB0 ------------------------------------------------------------------- */
3932static const unsigned int usb0_pins[] = {
3933 /* PWEN, OVC */
3934 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3935};
3936static const unsigned int usb0_mux[] = {
3937 USB0_PWEN_MARK, USB0_OVC_MARK,
3938};
3939/* - USB1 ------------------------------------------------------------------- */
3940static const unsigned int usb1_pins[] = {
3941 /* PWEN, OVC */
3942 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3943};
3944static const unsigned int usb1_mux[] = {
3945 USB1_PWEN_MARK, USB1_OVC_MARK,
3946};
3947
3948/* - USB30 ------------------------------------------------------------------ */
3949static const unsigned int usb30_pins[] = {
3950 /* PWEN, OVC */
3951 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3952};
3953static const unsigned int usb30_mux[] = {
3954 USB30_PWEN_MARK, USB30_OVC_MARK,
3955};
3956
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]3957#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3958/* - VIN4 ------------------------------------------------------------------- */
3959static const unsigned int vin4_data18_a_pins[] = {
3960 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3961 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3962 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3963 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3964 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3965 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3966 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3967 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3968 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3969};
3970static const unsigned int vin4_data18_a_mux[] = {
3971 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3972 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3973 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3974 VI4_DATA10_MARK, VI4_DATA11_MARK,
3975 VI4_DATA12_MARK, VI4_DATA13_MARK,
3976 VI4_DATA14_MARK, VI4_DATA15_MARK,
3977 VI4_DATA18_MARK, VI4_DATA19_MARK,
3978 VI4_DATA20_MARK, VI4_DATA21_MARK,
3979 VI4_DATA22_MARK, VI4_DATA23_MARK,
3980};
3981static const unsigned int vin4_data18_b_pins[] = {
3982 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3983 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3984 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3985 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3986 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3987 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3988 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3989 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3990 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3991};
3992static const unsigned int vin4_data18_b_mux[] = {
3993 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3994 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3995 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3996 VI4_DATA10_MARK, VI4_DATA11_MARK,
3997 VI4_DATA12_MARK, VI4_DATA13_MARK,
3998 VI4_DATA14_MARK, VI4_DATA15_MARK,
3999 VI4_DATA18_MARK, VI4_DATA19_MARK,
4000 VI4_DATA20_MARK, VI4_DATA21_MARK,
4001 VI4_DATA22_MARK, VI4_DATA23_MARK,
4002};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4003static const unsigned int vin4_data_a_pins[] = {
4004 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4005 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4006 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4007 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4008 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4009 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4010 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4011 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4012 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4013 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4014 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4015 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4016};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4017static const unsigned int vin4_data_a_mux[] = {
4018 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4019 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4020 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4021 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4022 VI4_DATA8_MARK, VI4_DATA9_MARK,
4023 VI4_DATA10_MARK, VI4_DATA11_MARK,
4024 VI4_DATA12_MARK, VI4_DATA13_MARK,
4025 VI4_DATA14_MARK, VI4_DATA15_MARK,
4026 VI4_DATA16_MARK, VI4_DATA17_MARK,
4027 VI4_DATA18_MARK, VI4_DATA19_MARK,
4028 VI4_DATA20_MARK, VI4_DATA21_MARK,
4029 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4030};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4031static const unsigned int vin4_data_b_pins[] = {
4032 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4033 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4034 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4035 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4036 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4037 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4038 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4039 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4040 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4041 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4042 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4043 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4044};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4045static const unsigned int vin4_data_b_mux[] = {
4046 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4047 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4048 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4049 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4050 VI4_DATA8_MARK, VI4_DATA9_MARK,
4051 VI4_DATA10_MARK, VI4_DATA11_MARK,
4052 VI4_DATA12_MARK, VI4_DATA13_MARK,
4053 VI4_DATA14_MARK, VI4_DATA15_MARK,
4054 VI4_DATA16_MARK, VI4_DATA17_MARK,
4055 VI4_DATA18_MARK, VI4_DATA19_MARK,
4056 VI4_DATA20_MARK, VI4_DATA21_MARK,
4057 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4058};
4059static const unsigned int vin4_sync_pins[] = {
4060 /* HSYNC#, VSYNC# */
4061 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4062};
4063static const unsigned int vin4_sync_mux[] = {
4064 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4065};
4066static const unsigned int vin4_field_pins[] = {
4067 /* FIELD */
4068 RCAR_GP_PIN(1, 16),
4069};
4070static const unsigned int vin4_field_mux[] = {
4071 VI4_FIELD_MARK,
4072};
4073static const unsigned int vin4_clkenb_pins[] = {
4074 /* CLKENB */
4075 RCAR_GP_PIN(1, 19),
4076};
4077static const unsigned int vin4_clkenb_mux[] = {
4078 VI4_CLKENB_MARK,
4079};
4080static const unsigned int vin4_clk_pins[] = {
4081 /* CLK */
4082 RCAR_GP_PIN(1, 27),
4083};
4084static const unsigned int vin4_clk_mux[] = {
4085 VI4_CLK_MARK,
4086};
4087
4088/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4089static const unsigned int vin5_data_pins[] = {
4090 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4091 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4092 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4093 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4094 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4095 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4096 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4097 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4098};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4099static const unsigned int vin5_data_mux[] = {
4100 VI5_DATA0_MARK, VI5_DATA1_MARK,
4101 VI5_DATA2_MARK, VI5_DATA3_MARK,
4102 VI5_DATA4_MARK, VI5_DATA5_MARK,
4103 VI5_DATA6_MARK, VI5_DATA7_MARK,
4104 VI5_DATA8_MARK, VI5_DATA9_MARK,
4105 VI5_DATA10_MARK, VI5_DATA11_MARK,
4106 VI5_DATA12_MARK, VI5_DATA13_MARK,
4107 VI5_DATA14_MARK, VI5_DATA15_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4108};
4109static const unsigned int vin5_sync_pins[] = {
4110 /* HSYNC#, VSYNC# */
4111 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4112};
4113static const unsigned int vin5_sync_mux[] = {
4114 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4115};
4116static const unsigned int vin5_field_pins[] = {
4117 RCAR_GP_PIN(1, 11),
4118};
4119static const unsigned int vin5_field_mux[] = {
4120 /* FIELD */
4121 VI5_FIELD_MARK,
4122};
4123static const unsigned int vin5_clkenb_pins[] = {
4124 RCAR_GP_PIN(1, 20),
4125};
4126static const unsigned int vin5_clkenb_mux[] = {
4127 /* CLKENB */
4128 VI5_CLKENB_MARK,
4129};
4130static const unsigned int vin5_clk_pins[] = {
4131 RCAR_GP_PIN(1, 21),
4132};
4133static const unsigned int vin5_clk_mux[] = {
4134 /* CLK */
4135 VI5_CLK_MARK,
4136};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4137#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4138
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4139static const struct {
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4140 struct sh_pfc_pin_group common[324];
4141#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4142 struct sh_pfc_pin_group automotive[31];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4143#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4144} pinmux_groups = {
4145 .common = {
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4146#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4147 SH_PFC_PIN_GROUP(audio_clk_a_a),
4148 SH_PFC_PIN_GROUP(audio_clk_a_b),
4149 SH_PFC_PIN_GROUP(audio_clk_a_c),
4150 SH_PFC_PIN_GROUP(audio_clk_b_a),
4151 SH_PFC_PIN_GROUP(audio_clk_b_b),
4152 SH_PFC_PIN_GROUP(audio_clk_c_a),
4153 SH_PFC_PIN_GROUP(audio_clk_c_b),
4154 SH_PFC_PIN_GROUP(audio_clkout_a),
4155 SH_PFC_PIN_GROUP(audio_clkout_b),
4156 SH_PFC_PIN_GROUP(audio_clkout_c),
4157 SH_PFC_PIN_GROUP(audio_clkout_d),
4158 SH_PFC_PIN_GROUP(audio_clkout1_a),
4159 SH_PFC_PIN_GROUP(audio_clkout1_b),
4160 SH_PFC_PIN_GROUP(audio_clkout2_a),
4161 SH_PFC_PIN_GROUP(audio_clkout2_b),
4162 SH_PFC_PIN_GROUP(audio_clkout3_a),
4163 SH_PFC_PIN_GROUP(audio_clkout3_b),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4164#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4165 SH_PFC_PIN_GROUP(avb_link),
4166 SH_PFC_PIN_GROUP(avb_magic),
4167 SH_PFC_PIN_GROUP(avb_phy_int),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4168 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4169 SH_PFC_PIN_GROUP(avb_mdio),
4170 SH_PFC_PIN_GROUP(avb_mii),
4171 SH_PFC_PIN_GROUP(avb_avtp_pps),
4172 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4173 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4174 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4175 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4176#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4177 SH_PFC_PIN_GROUP(can0_data_a),
4178 SH_PFC_PIN_GROUP(can0_data_b),
4179 SH_PFC_PIN_GROUP(can1_data),
4180 SH_PFC_PIN_GROUP(can_clk),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4181 SH_PFC_PIN_GROUP(canfd0_data_a),
4182 SH_PFC_PIN_GROUP(canfd0_data_b),
4183 SH_PFC_PIN_GROUP(canfd1_data),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4184 SH_PFC_PIN_GROUP(du_rgb666),
4185 SH_PFC_PIN_GROUP(du_rgb888),
4186 SH_PFC_PIN_GROUP(du_clk_out_0),
4187 SH_PFC_PIN_GROUP(du_clk_out_1),
4188 SH_PFC_PIN_GROUP(du_sync),
4189 SH_PFC_PIN_GROUP(du_oddf),
4190 SH_PFC_PIN_GROUP(du_cde),
4191 SH_PFC_PIN_GROUP(du_disp),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4192#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4193 SH_PFC_PIN_GROUP(hscif0_data),
4194 SH_PFC_PIN_GROUP(hscif0_clk),
4195 SH_PFC_PIN_GROUP(hscif0_ctrl),
4196 SH_PFC_PIN_GROUP(hscif1_data_a),
4197 SH_PFC_PIN_GROUP(hscif1_clk_a),
4198 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4199 SH_PFC_PIN_GROUP(hscif1_data_b),
4200 SH_PFC_PIN_GROUP(hscif1_clk_b),
4201 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4202 SH_PFC_PIN_GROUP(hscif2_data_a),
4203 SH_PFC_PIN_GROUP(hscif2_clk_a),
4204 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4205 SH_PFC_PIN_GROUP(hscif2_data_b),
4206 SH_PFC_PIN_GROUP(hscif2_clk_b),
4207 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4208 SH_PFC_PIN_GROUP(hscif2_data_c),
4209 SH_PFC_PIN_GROUP(hscif2_clk_c),
4210 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4211 SH_PFC_PIN_GROUP(hscif3_data_a),
4212 SH_PFC_PIN_GROUP(hscif3_clk),
4213 SH_PFC_PIN_GROUP(hscif3_ctrl),
4214 SH_PFC_PIN_GROUP(hscif3_data_b),
4215 SH_PFC_PIN_GROUP(hscif3_data_c),
4216 SH_PFC_PIN_GROUP(hscif3_data_d),
4217 SH_PFC_PIN_GROUP(hscif4_data_a),
4218 SH_PFC_PIN_GROUP(hscif4_clk),
4219 SH_PFC_PIN_GROUP(hscif4_ctrl),
4220 SH_PFC_PIN_GROUP(hscif4_data_b),
4221 SH_PFC_PIN_GROUP(i2c0),
4222 SH_PFC_PIN_GROUP(i2c1_a),
4223 SH_PFC_PIN_GROUP(i2c1_b),
4224 SH_PFC_PIN_GROUP(i2c2_a),
4225 SH_PFC_PIN_GROUP(i2c2_b),
4226 SH_PFC_PIN_GROUP(i2c3),
4227 SH_PFC_PIN_GROUP(i2c5),
4228 SH_PFC_PIN_GROUP(i2c6_a),
4229 SH_PFC_PIN_GROUP(i2c6_b),
4230 SH_PFC_PIN_GROUP(i2c6_c),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4231#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4232 SH_PFC_PIN_GROUP(intc_ex_irq0),
4233 SH_PFC_PIN_GROUP(intc_ex_irq1),
4234 SH_PFC_PIN_GROUP(intc_ex_irq2),
4235 SH_PFC_PIN_GROUP(intc_ex_irq3),
4236 SH_PFC_PIN_GROUP(intc_ex_irq4),
4237 SH_PFC_PIN_GROUP(intc_ex_irq5),
4238 SH_PFC_PIN_GROUP(msiof0_clk),
4239 SH_PFC_PIN_GROUP(msiof0_sync),
4240 SH_PFC_PIN_GROUP(msiof0_ss1),
4241 SH_PFC_PIN_GROUP(msiof0_ss2),
4242 SH_PFC_PIN_GROUP(msiof0_txd),
4243 SH_PFC_PIN_GROUP(msiof0_rxd),
4244 SH_PFC_PIN_GROUP(msiof1_clk_a),
4245 SH_PFC_PIN_GROUP(msiof1_sync_a),
4246 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4247 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4248 SH_PFC_PIN_GROUP(msiof1_txd_a),
4249 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4250 SH_PFC_PIN_GROUP(msiof1_clk_b),
4251 SH_PFC_PIN_GROUP(msiof1_sync_b),
4252 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4253 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4254 SH_PFC_PIN_GROUP(msiof1_txd_b),
4255 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4256 SH_PFC_PIN_GROUP(msiof1_clk_c),
4257 SH_PFC_PIN_GROUP(msiof1_sync_c),
4258 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4259 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4260 SH_PFC_PIN_GROUP(msiof1_txd_c),
4261 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4262 SH_PFC_PIN_GROUP(msiof1_clk_d),
4263 SH_PFC_PIN_GROUP(msiof1_sync_d),
4264 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4265 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4266 SH_PFC_PIN_GROUP(msiof1_txd_d),
4267 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4268 SH_PFC_PIN_GROUP(msiof1_clk_e),
4269 SH_PFC_PIN_GROUP(msiof1_sync_e),
4270 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4271 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4272 SH_PFC_PIN_GROUP(msiof1_txd_e),
4273 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4274 SH_PFC_PIN_GROUP(msiof1_clk_f),
4275 SH_PFC_PIN_GROUP(msiof1_sync_f),
4276 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4277 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4278 SH_PFC_PIN_GROUP(msiof1_txd_f),
4279 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4280 SH_PFC_PIN_GROUP(msiof1_clk_g),
4281 SH_PFC_PIN_GROUP(msiof1_sync_g),
4282 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4283 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4284 SH_PFC_PIN_GROUP(msiof1_txd_g),
4285 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4286 SH_PFC_PIN_GROUP(msiof2_clk_a),
4287 SH_PFC_PIN_GROUP(msiof2_sync_a),
4288 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4289 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4290 SH_PFC_PIN_GROUP(msiof2_txd_a),
4291 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4292 SH_PFC_PIN_GROUP(msiof2_clk_b),
4293 SH_PFC_PIN_GROUP(msiof2_sync_b),
4294 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4295 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4296 SH_PFC_PIN_GROUP(msiof2_txd_b),
4297 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4298 SH_PFC_PIN_GROUP(msiof2_clk_c),
4299 SH_PFC_PIN_GROUP(msiof2_sync_c),
4300 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4301 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4302 SH_PFC_PIN_GROUP(msiof2_txd_c),
4303 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4304 SH_PFC_PIN_GROUP(msiof2_clk_d),
4305 SH_PFC_PIN_GROUP(msiof2_sync_d),
4306 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4307 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4308 SH_PFC_PIN_GROUP(msiof2_txd_d),
4309 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4310 SH_PFC_PIN_GROUP(msiof3_clk_a),
4311 SH_PFC_PIN_GROUP(msiof3_sync_a),
4312 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4313 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4314 SH_PFC_PIN_GROUP(msiof3_txd_a),
4315 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4316 SH_PFC_PIN_GROUP(msiof3_clk_b),
4317 SH_PFC_PIN_GROUP(msiof3_sync_b),
4318 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4319 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4320 SH_PFC_PIN_GROUP(msiof3_txd_b),
4321 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4322 SH_PFC_PIN_GROUP(msiof3_clk_c),
4323 SH_PFC_PIN_GROUP(msiof3_sync_c),
4324 SH_PFC_PIN_GROUP(msiof3_txd_c),
4325 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4326 SH_PFC_PIN_GROUP(msiof3_clk_d),
4327 SH_PFC_PIN_GROUP(msiof3_sync_d),
4328 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4329 SH_PFC_PIN_GROUP(msiof3_txd_d),
4330 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4331 SH_PFC_PIN_GROUP(msiof3_clk_e),
4332 SH_PFC_PIN_GROUP(msiof3_sync_e),
4333 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4334 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4335 SH_PFC_PIN_GROUP(msiof3_txd_e),
4336 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4337 SH_PFC_PIN_GROUP(pwm0),
4338 SH_PFC_PIN_GROUP(pwm1_a),
4339 SH_PFC_PIN_GROUP(pwm1_b),
4340 SH_PFC_PIN_GROUP(pwm2_a),
4341 SH_PFC_PIN_GROUP(pwm2_b),
4342 SH_PFC_PIN_GROUP(pwm3_a),
4343 SH_PFC_PIN_GROUP(pwm3_b),
4344 SH_PFC_PIN_GROUP(pwm4_a),
4345 SH_PFC_PIN_GROUP(pwm4_b),
4346 SH_PFC_PIN_GROUP(pwm5_a),
4347 SH_PFC_PIN_GROUP(pwm5_b),
4348 SH_PFC_PIN_GROUP(pwm6_a),
4349 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4350#endif
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4351 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4352 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4353 BUS_DATA_PIN_GROUP(qspi0_data, 4),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4354 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4355 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4356 BUS_DATA_PIN_GROUP(qspi1_data, 4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4357 SH_PFC_PIN_GROUP(scif0_data),
4358 SH_PFC_PIN_GROUP(scif0_clk),
4359 SH_PFC_PIN_GROUP(scif0_ctrl),
4360 SH_PFC_PIN_GROUP(scif1_data_a),
4361 SH_PFC_PIN_GROUP(scif1_clk),
4362 SH_PFC_PIN_GROUP(scif1_ctrl),
4363 SH_PFC_PIN_GROUP(scif1_data_b),
4364 SH_PFC_PIN_GROUP(scif2_data_a),
4365 SH_PFC_PIN_GROUP(scif2_clk),
4366 SH_PFC_PIN_GROUP(scif2_data_b),
4367 SH_PFC_PIN_GROUP(scif3_data_a),
4368 SH_PFC_PIN_GROUP(scif3_clk),
4369 SH_PFC_PIN_GROUP(scif3_ctrl),
4370 SH_PFC_PIN_GROUP(scif3_data_b),
4371 SH_PFC_PIN_GROUP(scif4_data_a),
4372 SH_PFC_PIN_GROUP(scif4_clk_a),
4373 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4374 SH_PFC_PIN_GROUP(scif4_data_b),
4375 SH_PFC_PIN_GROUP(scif4_clk_b),
4376 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4377 SH_PFC_PIN_GROUP(scif4_data_c),
4378 SH_PFC_PIN_GROUP(scif4_clk_c),
4379 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4380 SH_PFC_PIN_GROUP(scif5_data_a),
4381 SH_PFC_PIN_GROUP(scif5_clk_a),
4382 SH_PFC_PIN_GROUP(scif5_data_b),
4383 SH_PFC_PIN_GROUP(scif5_clk_b),
4384 SH_PFC_PIN_GROUP(scif_clk_a),
4385 SH_PFC_PIN_GROUP(scif_clk_b),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4386 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4387 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4388 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4389 SH_PFC_PIN_GROUP(sdhi0_cd),
4390 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4391 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4392 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4393 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4394 SH_PFC_PIN_GROUP(sdhi1_cd),
4395 SH_PFC_PIN_GROUP(sdhi1_wp),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4396 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4397 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4398 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4399 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4400 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4401 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4402 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4403 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4404 SH_PFC_PIN_GROUP(sdhi2_ds),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4405 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4406 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4407 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4408 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4409 SH_PFC_PIN_GROUP(sdhi3_cd),
4410 SH_PFC_PIN_GROUP(sdhi3_wp),
4411 SH_PFC_PIN_GROUP(sdhi3_ds),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4412#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4413 SH_PFC_PIN_GROUP(ssi0_data),
4414 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4415 SH_PFC_PIN_GROUP(ssi1_data_a),
4416 SH_PFC_PIN_GROUP(ssi1_data_b),
4417 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4418 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4419 SH_PFC_PIN_GROUP(ssi2_data_a),
4420 SH_PFC_PIN_GROUP(ssi2_data_b),
4421 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4422 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4423 SH_PFC_PIN_GROUP(ssi3_data),
4424 SH_PFC_PIN_GROUP(ssi349_ctrl),
4425 SH_PFC_PIN_GROUP(ssi4_data),
4426 SH_PFC_PIN_GROUP(ssi4_ctrl),
4427 SH_PFC_PIN_GROUP(ssi5_data),
4428 SH_PFC_PIN_GROUP(ssi5_ctrl),
4429 SH_PFC_PIN_GROUP(ssi6_data),
4430 SH_PFC_PIN_GROUP(ssi6_ctrl),
4431 SH_PFC_PIN_GROUP(ssi7_data),
4432 SH_PFC_PIN_GROUP(ssi78_ctrl),
4433 SH_PFC_PIN_GROUP(ssi8_data),
4434 SH_PFC_PIN_GROUP(ssi9_data_a),
4435 SH_PFC_PIN_GROUP(ssi9_data_b),
4436 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4437 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4438#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4439 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4440 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4441 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4442 SH_PFC_PIN_GROUP(tmu_tclk2_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4443 SH_PFC_PIN_GROUP(tpu_to0),
4444 SH_PFC_PIN_GROUP(tpu_to1),
4445 SH_PFC_PIN_GROUP(tpu_to2),
4446 SH_PFC_PIN_GROUP(tpu_to3),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4447 SH_PFC_PIN_GROUP(usb0),
4448 SH_PFC_PIN_GROUP(usb1),
4449 SH_PFC_PIN_GROUP(usb30),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4450#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4451 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4452 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4453 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4454 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4455 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4456 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4457 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4458 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4459 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4460 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4461 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4462 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4463 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4464 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4465 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4466 SH_PFC_PIN_GROUP(vin4_sync),
4467 SH_PFC_PIN_GROUP(vin4_field),
4468 SH_PFC_PIN_GROUP(vin4_clkenb),
4469 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4470 BUS_DATA_PIN_GROUP(vin5_data, 8),
4471 BUS_DATA_PIN_GROUP(vin5_data, 10),
4472 BUS_DATA_PIN_GROUP(vin5_data, 12),
4473 BUS_DATA_PIN_GROUP(vin5_data, 16),
4474 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4475 SH_PFC_PIN_GROUP(vin5_sync),
4476 SH_PFC_PIN_GROUP(vin5_field),
4477 SH_PFC_PIN_GROUP(vin5_clkenb),
4478 SH_PFC_PIN_GROUP(vin5_clk),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4479#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4480 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4481#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4482 .automotive = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4483 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4484 SH_PFC_PIN_GROUP(drif0_data0_a),
4485 SH_PFC_PIN_GROUP(drif0_data1_a),
4486 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4487 SH_PFC_PIN_GROUP(drif0_data0_b),
4488 SH_PFC_PIN_GROUP(drif0_data1_b),
4489 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4490 SH_PFC_PIN_GROUP(drif0_data0_c),
4491 SH_PFC_PIN_GROUP(drif0_data1_c),
4492 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4493 SH_PFC_PIN_GROUP(drif1_data0_a),
4494 SH_PFC_PIN_GROUP(drif1_data1_a),
4495 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4496 SH_PFC_PIN_GROUP(drif1_data0_b),
4497 SH_PFC_PIN_GROUP(drif1_data1_b),
4498 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4499 SH_PFC_PIN_GROUP(drif1_data0_c),
4500 SH_PFC_PIN_GROUP(drif1_data1_c),
4501 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4502 SH_PFC_PIN_GROUP(drif2_data0_a),
4503 SH_PFC_PIN_GROUP(drif2_data1_a),
4504 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4505 SH_PFC_PIN_GROUP(drif2_data0_b),
4506 SH_PFC_PIN_GROUP(drif2_data1_b),
4507 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4508 SH_PFC_PIN_GROUP(drif3_data0_a),
4509 SH_PFC_PIN_GROUP(drif3_data1_a),
4510 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4511 SH_PFC_PIN_GROUP(drif3_data0_b),
4512 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4513 SH_PFC_PIN_GROUP(mlb_3pin),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4514 }
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4515#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4516};
4517
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4518#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4519static const char * const audio_clk_groups[] = {
4520 "audio_clk_a_a",
4521 "audio_clk_a_b",
4522 "audio_clk_a_c",
4523 "audio_clk_b_a",
4524 "audio_clk_b_b",
4525 "audio_clk_c_a",
4526 "audio_clk_c_b",
4527 "audio_clkout_a",
4528 "audio_clkout_b",
4529 "audio_clkout_c",
4530 "audio_clkout_d",
4531 "audio_clkout1_a",
4532 "audio_clkout1_b",
4533 "audio_clkout2_a",
4534 "audio_clkout2_b",
4535 "audio_clkout3_a",
4536 "audio_clkout3_b",
4537};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4538#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4539
4540static const char * const avb_groups[] = {
4541 "avb_link",
4542 "avb_magic",
4543 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4544 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4545 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4546 "avb_mii",
4547 "avb_avtp_pps",
4548 "avb_avtp_match_a",
4549 "avb_avtp_capture_a",
4550 "avb_avtp_match_b",
4551 "avb_avtp_capture_b",
4552};
4553
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4554#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4555static const char * const can0_groups[] = {
4556 "can0_data_a",
4557 "can0_data_b",
4558};
4559
4560static const char * const can1_groups[] = {
4561 "can1_data",
4562};
4563
4564static const char * const can_clk_groups[] = {
4565 "can_clk",
4566};
4567
4568static const char * const canfd0_groups[] = {
4569 "canfd0_data_a",
4570 "canfd0_data_b",
4571};
4572
4573static const char * const canfd1_groups[] = {
4574 "canfd1_data",
4575};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4576#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4577
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4578#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4579static const char * const drif0_groups[] = {
4580 "drif0_ctrl_a",
4581 "drif0_data0_a",
4582 "drif0_data1_a",
4583 "drif0_ctrl_b",
4584 "drif0_data0_b",
4585 "drif0_data1_b",
4586 "drif0_ctrl_c",
4587 "drif0_data0_c",
4588 "drif0_data1_c",
4589};
4590
4591static const char * const drif1_groups[] = {
4592 "drif1_ctrl_a",
4593 "drif1_data0_a",
4594 "drif1_data1_a",
4595 "drif1_ctrl_b",
4596 "drif1_data0_b",
4597 "drif1_data1_b",
4598 "drif1_ctrl_c",
4599 "drif1_data0_c",
4600 "drif1_data1_c",
4601};
4602
4603static const char * const drif2_groups[] = {
4604 "drif2_ctrl_a",
4605 "drif2_data0_a",
4606 "drif2_data1_a",
4607 "drif2_ctrl_b",
4608 "drif2_data0_b",
4609 "drif2_data1_b",
4610};
4611
4612static const char * const drif3_groups[] = {
4613 "drif3_ctrl_a",
4614 "drif3_data0_a",
4615 "drif3_data1_a",
4616 "drif3_ctrl_b",
4617 "drif3_data0_b",
4618 "drif3_data1_b",
4619};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4620#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4621
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4622#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4623static const char * const du_groups[] = {
4624 "du_rgb666",
4625 "du_rgb888",
4626 "du_clk_out_0",
4627 "du_clk_out_1",
4628 "du_sync",
4629 "du_oddf",
4630 "du_cde",
4631 "du_disp",
4632};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4633#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4634
4635static const char * const hscif0_groups[] = {
4636 "hscif0_data",
4637 "hscif0_clk",
4638 "hscif0_ctrl",
4639};
4640
4641static const char * const hscif1_groups[] = {
4642 "hscif1_data_a",
4643 "hscif1_clk_a",
4644 "hscif1_ctrl_a",
4645 "hscif1_data_b",
4646 "hscif1_clk_b",
4647 "hscif1_ctrl_b",
4648};
4649
4650static const char * const hscif2_groups[] = {
4651 "hscif2_data_a",
4652 "hscif2_clk_a",
4653 "hscif2_ctrl_a",
4654 "hscif2_data_b",
4655 "hscif2_clk_b",
4656 "hscif2_ctrl_b",
4657 "hscif2_data_c",
4658 "hscif2_clk_c",
4659 "hscif2_ctrl_c",
4660};
4661
4662static const char * const hscif3_groups[] = {
4663 "hscif3_data_a",
4664 "hscif3_clk",
4665 "hscif3_ctrl",
4666 "hscif3_data_b",
4667 "hscif3_data_c",
4668 "hscif3_data_d",
4669};
4670
4671static const char * const hscif4_groups[] = {
4672 "hscif4_data_a",
4673 "hscif4_clk",
4674 "hscif4_ctrl",
4675 "hscif4_data_b",
4676};
4677
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4678static const char * const i2c0_groups[] = {
4679 "i2c0",
4680};
4681
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4682static const char * const i2c1_groups[] = {
4683 "i2c1_a",
4684 "i2c1_b",
4685};
4686
4687static const char * const i2c2_groups[] = {
4688 "i2c2_a",
4689 "i2c2_b",
4690};
4691
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4692static const char * const i2c3_groups[] = {
4693 "i2c3",
4694};
4695
4696static const char * const i2c5_groups[] = {
4697 "i2c5",
4698};
4699
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4700static const char * const i2c6_groups[] = {
4701 "i2c6_a",
4702 "i2c6_b",
4703 "i2c6_c",
4704};
4705
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4706#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4707static const char * const intc_ex_groups[] = {
4708 "intc_ex_irq0",
4709 "intc_ex_irq1",
4710 "intc_ex_irq2",
4711 "intc_ex_irq3",
4712 "intc_ex_irq4",
4713 "intc_ex_irq5",
4714};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4715#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4716
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4717#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4718static const char * const mlb_3pin_groups[] = {
4719 "mlb_3pin",
4720};
4721#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4722
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4723#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4724static const char * const msiof0_groups[] = {
4725 "msiof0_clk",
4726 "msiof0_sync",
4727 "msiof0_ss1",
4728 "msiof0_ss2",
4729 "msiof0_txd",
4730 "msiof0_rxd",
4731};
4732
4733static const char * const msiof1_groups[] = {
4734 "msiof1_clk_a",
4735 "msiof1_sync_a",
4736 "msiof1_ss1_a",
4737 "msiof1_ss2_a",
4738 "msiof1_txd_a",
4739 "msiof1_rxd_a",
4740 "msiof1_clk_b",
4741 "msiof1_sync_b",
4742 "msiof1_ss1_b",
4743 "msiof1_ss2_b",
4744 "msiof1_txd_b",
4745 "msiof1_rxd_b",
4746 "msiof1_clk_c",
4747 "msiof1_sync_c",
4748 "msiof1_ss1_c",
4749 "msiof1_ss2_c",
4750 "msiof1_txd_c",
4751 "msiof1_rxd_c",
4752 "msiof1_clk_d",
4753 "msiof1_sync_d",
4754 "msiof1_ss1_d",
4755 "msiof1_ss2_d",
4756 "msiof1_txd_d",
4757 "msiof1_rxd_d",
4758 "msiof1_clk_e",
4759 "msiof1_sync_e",
4760 "msiof1_ss1_e",
4761 "msiof1_ss2_e",
4762 "msiof1_txd_e",
4763 "msiof1_rxd_e",
4764 "msiof1_clk_f",
4765 "msiof1_sync_f",
4766 "msiof1_ss1_f",
4767 "msiof1_ss2_f",
4768 "msiof1_txd_f",
4769 "msiof1_rxd_f",
4770 "msiof1_clk_g",
4771 "msiof1_sync_g",
4772 "msiof1_ss1_g",
4773 "msiof1_ss2_g",
4774 "msiof1_txd_g",
4775 "msiof1_rxd_g",
4776};
4777
4778static const char * const msiof2_groups[] = {
4779 "msiof2_clk_a",
4780 "msiof2_sync_a",
4781 "msiof2_ss1_a",
4782 "msiof2_ss2_a",
4783 "msiof2_txd_a",
4784 "msiof2_rxd_a",
4785 "msiof2_clk_b",
4786 "msiof2_sync_b",
4787 "msiof2_ss1_b",
4788 "msiof2_ss2_b",
4789 "msiof2_txd_b",
4790 "msiof2_rxd_b",
4791 "msiof2_clk_c",
4792 "msiof2_sync_c",
4793 "msiof2_ss1_c",
4794 "msiof2_ss2_c",
4795 "msiof2_txd_c",
4796 "msiof2_rxd_c",
4797 "msiof2_clk_d",
4798 "msiof2_sync_d",
4799 "msiof2_ss1_d",
4800 "msiof2_ss2_d",
4801 "msiof2_txd_d",
4802 "msiof2_rxd_d",
4803};
4804
4805static const char * const msiof3_groups[] = {
4806 "msiof3_clk_a",
4807 "msiof3_sync_a",
4808 "msiof3_ss1_a",
4809 "msiof3_ss2_a",
4810 "msiof3_txd_a",
4811 "msiof3_rxd_a",
4812 "msiof3_clk_b",
4813 "msiof3_sync_b",
4814 "msiof3_ss1_b",
4815 "msiof3_ss2_b",
4816 "msiof3_txd_b",
4817 "msiof3_rxd_b",
4818 "msiof3_clk_c",
4819 "msiof3_sync_c",
4820 "msiof3_txd_c",
4821 "msiof3_rxd_c",
4822 "msiof3_clk_d",
4823 "msiof3_sync_d",
4824 "msiof3_ss1_d",
4825 "msiof3_txd_d",
4826 "msiof3_rxd_d",
4827 "msiof3_clk_e",
4828 "msiof3_sync_e",
4829 "msiof3_ss1_e",
4830 "msiof3_ss2_e",
4831 "msiof3_txd_e",
4832 "msiof3_rxd_e",
4833};
4834
4835static const char * const pwm0_groups[] = {
4836 "pwm0",
4837};
4838
4839static const char * const pwm1_groups[] = {
4840 "pwm1_a",
4841 "pwm1_b",
4842};
4843
4844static const char * const pwm2_groups[] = {
4845 "pwm2_a",
4846 "pwm2_b",
4847};
4848
4849static const char * const pwm3_groups[] = {
4850 "pwm3_a",
4851 "pwm3_b",
4852};
4853
4854static const char * const pwm4_groups[] = {
4855 "pwm4_a",
4856 "pwm4_b",
4857};
4858
4859static const char * const pwm5_groups[] = {
4860 "pwm5_a",
4861 "pwm5_b",
4862};
4863
4864static const char * const pwm6_groups[] = {
4865 "pwm6_a",
4866 "pwm6_b",
4867};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4868#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4869
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4870static const char * const qspi0_groups[] = {
4871 "qspi0_ctrl",
4872 "qspi0_data2",
4873 "qspi0_data4",
4874};
4875
4876static const char * const qspi1_groups[] = {
4877 "qspi1_ctrl",
4878 "qspi1_data2",
4879 "qspi1_data4",
4880};
4881
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4882static const char * const scif0_groups[] = {
4883 "scif0_data",
4884 "scif0_clk",
4885 "scif0_ctrl",
4886};
4887
4888static const char * const scif1_groups[] = {
4889 "scif1_data_a",
4890 "scif1_clk",
4891 "scif1_ctrl",
4892 "scif1_data_b",
4893};
4894
4895static const char * const scif2_groups[] = {
4896 "scif2_data_a",
4897 "scif2_clk",
4898 "scif2_data_b",
4899};
4900
4901static const char * const scif3_groups[] = {
4902 "scif3_data_a",
4903 "scif3_clk",
4904 "scif3_ctrl",
4905 "scif3_data_b",
4906};
4907
4908static const char * const scif4_groups[] = {
4909 "scif4_data_a",
4910 "scif4_clk_a",
4911 "scif4_ctrl_a",
4912 "scif4_data_b",
4913 "scif4_clk_b",
4914 "scif4_ctrl_b",
4915 "scif4_data_c",
4916 "scif4_clk_c",
4917 "scif4_ctrl_c",
4918};
4919
4920static const char * const scif5_groups[] = {
4921 "scif5_data_a",
4922 "scif5_clk_a",
4923 "scif5_data_b",
4924 "scif5_clk_b",
4925};
4926
4927static const char * const scif_clk_groups[] = {
4928 "scif_clk_a",
4929 "scif_clk_b",
4930};
4931
4932static const char * const sdhi0_groups[] = {
4933 "sdhi0_data1",
4934 "sdhi0_data4",
4935 "sdhi0_ctrl",
4936 "sdhi0_cd",
4937 "sdhi0_wp",
4938};
4939
4940static const char * const sdhi1_groups[] = {
4941 "sdhi1_data1",
4942 "sdhi1_data4",
4943 "sdhi1_ctrl",
4944 "sdhi1_cd",
4945 "sdhi1_wp",
4946};
4947
4948static const char * const sdhi2_groups[] = {
4949 "sdhi2_data1",
4950 "sdhi2_data4",
4951 "sdhi2_data8",
4952 "sdhi2_ctrl",
4953 "sdhi2_cd_a",
4954 "sdhi2_wp_a",
4955 "sdhi2_cd_b",
4956 "sdhi2_wp_b",
4957 "sdhi2_ds",
4958};
4959
4960static const char * const sdhi3_groups[] = {
4961 "sdhi3_data1",
4962 "sdhi3_data4",
4963 "sdhi3_data8",
4964 "sdhi3_ctrl",
4965 "sdhi3_cd",
4966 "sdhi3_wp",
4967 "sdhi3_ds",
4968};
4969
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4970#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4971static const char * const ssi_groups[] = {
4972 "ssi0_data",
4973 "ssi01239_ctrl",
4974 "ssi1_data_a",
4975 "ssi1_data_b",
4976 "ssi1_ctrl_a",
4977 "ssi1_ctrl_b",
4978 "ssi2_data_a",
4979 "ssi2_data_b",
4980 "ssi2_ctrl_a",
4981 "ssi2_ctrl_b",
4982 "ssi3_data",
4983 "ssi349_ctrl",
4984 "ssi4_data",
4985 "ssi4_ctrl",
4986 "ssi5_data",
4987 "ssi5_ctrl",
4988 "ssi6_data",
4989 "ssi6_ctrl",
4990 "ssi7_data",
4991 "ssi78_ctrl",
4992 "ssi8_data",
4993 "ssi9_data_a",
4994 "ssi9_data_b",
4995 "ssi9_ctrl_a",
4996 "ssi9_ctrl_b",
4997};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]4998#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4999
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5000static const char * const tmu_groups[] = {
5001 "tmu_tclk1_a",
5002 "tmu_tclk1_b",
5003 "tmu_tclk2_a",
5004 "tmu_tclk2_b",
5005};
5006
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5007static const char * const tpu_groups[] = {
5008 "tpu_to0",
5009 "tpu_to1",
5010 "tpu_to2",
5011 "tpu_to3",
5012};
5013
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5014static const char * const usb0_groups[] = {
5015 "usb0",
5016};
5017
5018static const char * const usb1_groups[] = {
5019 "usb1",
5020};
5021
5022static const char * const usb30_groups[] = {
5023 "usb30",
5024};
5025
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5026#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5027static const char * const vin4_groups[] = {
5028 "vin4_data8_a",
5029 "vin4_data10_a",
5030 "vin4_data12_a",
5031 "vin4_data16_a",
5032 "vin4_data18_a",
5033 "vin4_data20_a",
5034 "vin4_data24_a",
5035 "vin4_data8_b",
5036 "vin4_data10_b",
5037 "vin4_data12_b",
5038 "vin4_data16_b",
5039 "vin4_data18_b",
5040 "vin4_data20_b",
5041 "vin4_data24_b",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5042 "vin4_g8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5043 "vin4_sync",
5044 "vin4_field",
5045 "vin4_clkenb",
5046 "vin4_clk",
5047};
5048
5049static const char * const vin5_groups[] = {
5050 "vin5_data8",
5051 "vin5_data10",
5052 "vin5_data12",
5053 "vin5_data16",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5054 "vin5_high8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5055 "vin5_sync",
5056 "vin5_field",
5057 "vin5_clkenb",
5058 "vin5_clk",
5059};
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5060#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5061
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5062static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5063 struct sh_pfc_function common[52];
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5064#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5065 struct sh_pfc_function automotive[5];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]5066#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5067} pinmux_functions = {
5068 .common = {
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5069#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5070 SH_PFC_FUNCTION(audio_clk),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5071#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5072 SH_PFC_FUNCTION(avb),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5073#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5074 SH_PFC_FUNCTION(can0),
5075 SH_PFC_FUNCTION(can1),
5076 SH_PFC_FUNCTION(can_clk),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5077 SH_PFC_FUNCTION(canfd0),
5078 SH_PFC_FUNCTION(canfd1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5079 SH_PFC_FUNCTION(du),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5080#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5081 SH_PFC_FUNCTION(hscif0),
5082 SH_PFC_FUNCTION(hscif1),
5083 SH_PFC_FUNCTION(hscif2),
5084 SH_PFC_FUNCTION(hscif3),
5085 SH_PFC_FUNCTION(hscif4),
5086 SH_PFC_FUNCTION(i2c0),
5087 SH_PFC_FUNCTION(i2c1),
5088 SH_PFC_FUNCTION(i2c2),
5089 SH_PFC_FUNCTION(i2c3),
5090 SH_PFC_FUNCTION(i2c5),
5091 SH_PFC_FUNCTION(i2c6),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5092#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5093 SH_PFC_FUNCTION(intc_ex),
5094 SH_PFC_FUNCTION(msiof0),
5095 SH_PFC_FUNCTION(msiof1),
5096 SH_PFC_FUNCTION(msiof2),
5097 SH_PFC_FUNCTION(msiof3),
5098 SH_PFC_FUNCTION(pwm0),
5099 SH_PFC_FUNCTION(pwm1),
5100 SH_PFC_FUNCTION(pwm2),
5101 SH_PFC_FUNCTION(pwm3),
5102 SH_PFC_FUNCTION(pwm4),
5103 SH_PFC_FUNCTION(pwm5),
5104 SH_PFC_FUNCTION(pwm6),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5105#endif
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5106 SH_PFC_FUNCTION(qspi0),
5107 SH_PFC_FUNCTION(qspi1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5108 SH_PFC_FUNCTION(scif0),
5109 SH_PFC_FUNCTION(scif1),
5110 SH_PFC_FUNCTION(scif2),
5111 SH_PFC_FUNCTION(scif3),
5112 SH_PFC_FUNCTION(scif4),
5113 SH_PFC_FUNCTION(scif5),
5114 SH_PFC_FUNCTION(scif_clk),
5115 SH_PFC_FUNCTION(sdhi0),
5116 SH_PFC_FUNCTION(sdhi1),
5117 SH_PFC_FUNCTION(sdhi2),
5118 SH_PFC_FUNCTION(sdhi3),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5119#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5120 SH_PFC_FUNCTION(ssi),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5121#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5122 SH_PFC_FUNCTION(tmu),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5123 SH_PFC_FUNCTION(tpu),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5124 SH_PFC_FUNCTION(usb0),
5125 SH_PFC_FUNCTION(usb1),
5126 SH_PFC_FUNCTION(usb30),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5127#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5128 SH_PFC_FUNCTION(vin4),
5129 SH_PFC_FUNCTION(vin5),
Marek Vasut05876e22024-12-23 14:34:11 +0100[diff] [blame]5130#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5131 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5132#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5133 .automotive = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5134 SH_PFC_FUNCTION(drif0),
5135 SH_PFC_FUNCTION(drif1),
5136 SH_PFC_FUNCTION(drif2),
5137 SH_PFC_FUNCTION(drif3),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5138 SH_PFC_FUNCTION(mlb_3pin),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5139 }
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5140#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5141};
5142
5143static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5144#define F_(x, y) FN_##y
5145#define FM(x) FN_##x
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5146 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5147 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5148 1, 1, 1, 1, 1),
5149 GROUP(
5150 /* GP0_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5151 GP_0_15_FN, GPSR0_15,
5152 GP_0_14_FN, GPSR0_14,
5153 GP_0_13_FN, GPSR0_13,
5154 GP_0_12_FN, GPSR0_12,
5155 GP_0_11_FN, GPSR0_11,
5156 GP_0_10_FN, GPSR0_10,
5157 GP_0_9_FN, GPSR0_9,
5158 GP_0_8_FN, GPSR0_8,
5159 GP_0_7_FN, GPSR0_7,
5160 GP_0_6_FN, GPSR0_6,
5161 GP_0_5_FN, GPSR0_5,
5162 GP_0_4_FN, GPSR0_4,
5163 GP_0_3_FN, GPSR0_3,
5164 GP_0_2_FN, GPSR0_2,
5165 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5166 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5167 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5168 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5169 0, 0,
5170 0, 0,
5171 0, 0,
5172 GP_1_28_FN, GPSR1_28,
5173 GP_1_27_FN, GPSR1_27,
5174 GP_1_26_FN, GPSR1_26,
5175 GP_1_25_FN, GPSR1_25,
5176 GP_1_24_FN, GPSR1_24,
5177 GP_1_23_FN, GPSR1_23,
5178 GP_1_22_FN, GPSR1_22,
5179 GP_1_21_FN, GPSR1_21,
5180 GP_1_20_FN, GPSR1_20,
5181 GP_1_19_FN, GPSR1_19,
5182 GP_1_18_FN, GPSR1_18,
5183 GP_1_17_FN, GPSR1_17,
5184 GP_1_16_FN, GPSR1_16,
5185 GP_1_15_FN, GPSR1_15,
5186 GP_1_14_FN, GPSR1_14,
5187 GP_1_13_FN, GPSR1_13,
5188 GP_1_12_FN, GPSR1_12,
5189 GP_1_11_FN, GPSR1_11,
5190 GP_1_10_FN, GPSR1_10,
5191 GP_1_9_FN, GPSR1_9,
5192 GP_1_8_FN, GPSR1_8,
5193 GP_1_7_FN, GPSR1_7,
5194 GP_1_6_FN, GPSR1_6,
5195 GP_1_5_FN, GPSR1_5,
5196 GP_1_4_FN, GPSR1_4,
5197 GP_1_3_FN, GPSR1_3,
5198 GP_1_2_FN, GPSR1_2,
5199 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5200 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5201 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5202 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5203 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5204 1, 1, 1, 1),
5205 GROUP(
5206 /* GP2_31_15 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5207 GP_2_14_FN, GPSR2_14,
5208 GP_2_13_FN, GPSR2_13,
5209 GP_2_12_FN, GPSR2_12,
5210 GP_2_11_FN, GPSR2_11,
5211 GP_2_10_FN, GPSR2_10,
5212 GP_2_9_FN, GPSR2_9,
5213 GP_2_8_FN, GPSR2_8,
5214 GP_2_7_FN, GPSR2_7,
5215 GP_2_6_FN, GPSR2_6,
5216 GP_2_5_FN, GPSR2_5,
5217 GP_2_4_FN, GPSR2_4,
5218 GP_2_3_FN, GPSR2_3,
5219 GP_2_2_FN, GPSR2_2,
5220 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5221 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5222 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5223 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5224 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5225 1, 1, 1, 1, 1),
5226 GROUP(
5227 /* GP3_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5228 GP_3_15_FN, GPSR3_15,
5229 GP_3_14_FN, GPSR3_14,
5230 GP_3_13_FN, GPSR3_13,
5231 GP_3_12_FN, GPSR3_12,
5232 GP_3_11_FN, GPSR3_11,
5233 GP_3_10_FN, GPSR3_10,
5234 GP_3_9_FN, GPSR3_9,
5235 GP_3_8_FN, GPSR3_8,
5236 GP_3_7_FN, GPSR3_7,
5237 GP_3_6_FN, GPSR3_6,
5238 GP_3_5_FN, GPSR3_5,
5239 GP_3_4_FN, GPSR3_4,
5240 GP_3_3_FN, GPSR3_3,
5241 GP_3_2_FN, GPSR3_2,
5242 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5243 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5244 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5245 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5246 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5247 1, 1, 1, 1, 1, 1, 1),
5248 GROUP(
5249 /* GP4_31_18 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5250 GP_4_17_FN, GPSR4_17,
5251 GP_4_16_FN, GPSR4_16,
5252 GP_4_15_FN, GPSR4_15,
5253 GP_4_14_FN, GPSR4_14,
5254 GP_4_13_FN, GPSR4_13,
5255 GP_4_12_FN, GPSR4_12,
5256 GP_4_11_FN, GPSR4_11,
5257 GP_4_10_FN, GPSR4_10,
5258 GP_4_9_FN, GPSR4_9,
5259 GP_4_8_FN, GPSR4_8,
5260 GP_4_7_FN, GPSR4_7,
5261 GP_4_6_FN, GPSR4_6,
5262 GP_4_5_FN, GPSR4_5,
5263 GP_4_4_FN, GPSR4_4,
5264 GP_4_3_FN, GPSR4_3,
5265 GP_4_2_FN, GPSR4_2,
5266 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5267 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5268 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5269 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5270 0, 0,
5271 0, 0,
5272 0, 0,
5273 0, 0,
5274 0, 0,
5275 0, 0,
5276 GP_5_25_FN, GPSR5_25,
5277 GP_5_24_FN, GPSR5_24,
5278 GP_5_23_FN, GPSR5_23,
5279 GP_5_22_FN, GPSR5_22,
5280 GP_5_21_FN, GPSR5_21,
5281 GP_5_20_FN, GPSR5_20,
5282 GP_5_19_FN, GPSR5_19,
5283 GP_5_18_FN, GPSR5_18,
5284 GP_5_17_FN, GPSR5_17,
5285 GP_5_16_FN, GPSR5_16,
5286 GP_5_15_FN, GPSR5_15,
5287 GP_5_14_FN, GPSR5_14,
5288 GP_5_13_FN, GPSR5_13,
5289 GP_5_12_FN, GPSR5_12,
5290 GP_5_11_FN, GPSR5_11,
5291 GP_5_10_FN, GPSR5_10,
5292 GP_5_9_FN, GPSR5_9,
5293 GP_5_8_FN, GPSR5_8,
5294 GP_5_7_FN, GPSR5_7,
5295 GP_5_6_FN, GPSR5_6,
5296 GP_5_5_FN, GPSR5_5,
5297 GP_5_4_FN, GPSR5_4,
5298 GP_5_3_FN, GPSR5_3,
5299 GP_5_2_FN, GPSR5_2,
5300 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5301 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5302 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5303 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5304 GP_6_31_FN, GPSR6_31,
5305 GP_6_30_FN, GPSR6_30,
5306 GP_6_29_FN, GPSR6_29,
5307 GP_6_28_FN, GPSR6_28,
5308 GP_6_27_FN, GPSR6_27,
5309 GP_6_26_FN, GPSR6_26,
5310 GP_6_25_FN, GPSR6_25,
5311 GP_6_24_FN, GPSR6_24,
5312 GP_6_23_FN, GPSR6_23,
5313 GP_6_22_FN, GPSR6_22,
5314 GP_6_21_FN, GPSR6_21,
5315 GP_6_20_FN, GPSR6_20,
5316 GP_6_19_FN, GPSR6_19,
5317 GP_6_18_FN, GPSR6_18,
5318 GP_6_17_FN, GPSR6_17,
5319 GP_6_16_FN, GPSR6_16,
5320 GP_6_15_FN, GPSR6_15,
5321 GP_6_14_FN, GPSR6_14,
5322 GP_6_13_FN, GPSR6_13,
5323 GP_6_12_FN, GPSR6_12,
5324 GP_6_11_FN, GPSR6_11,
5325 GP_6_10_FN, GPSR6_10,
5326 GP_6_9_FN, GPSR6_9,
5327 GP_6_8_FN, GPSR6_8,
5328 GP_6_7_FN, GPSR6_7,
5329 GP_6_6_FN, GPSR6_6,
5330 GP_6_5_FN, GPSR6_5,
5331 GP_6_4_FN, GPSR6_4,
5332 GP_6_3_FN, GPSR6_3,
5333 GP_6_2_FN, GPSR6_2,
5334 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5335 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5336 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5337 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5338 GROUP(-28, 1, 1, 1, 1),
5339 GROUP(
5340 /* GP7_31_4 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5341 GP_7_3_FN, GPSR7_3,
5342 GP_7_2_FN, GPSR7_2,
5343 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5344 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5345 },
5346#undef F_
5347#undef FM
5348
5349#define F_(x, y) x,
5350#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5351 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5352 IP0_31_28
5353 IP0_27_24
5354 IP0_23_20
5355 IP0_19_16
5356 IP0_15_12
5357 IP0_11_8
5358 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5359 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5360 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5361 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5362 IP1_31_28
5363 IP1_27_24
5364 IP1_23_20
5365 IP1_19_16
5366 IP1_15_12
5367 IP1_11_8
5368 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5369 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5370 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5371 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5372 IP2_31_28
5373 IP2_27_24
5374 IP2_23_20
5375 IP2_19_16
5376 IP2_15_12
5377 IP2_11_8
5378 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5379 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5380 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5381 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5382 IP3_31_28
5383 IP3_27_24
5384 IP3_23_20
5385 IP3_19_16
5386 IP3_15_12
5387 IP3_11_8
5388 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5389 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5390 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5391 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5392 IP4_31_28
5393 IP4_27_24
5394 IP4_23_20
5395 IP4_19_16
5396 IP4_15_12
5397 IP4_11_8
5398 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5399 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5400 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5401 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5402 IP5_31_28
5403 IP5_27_24
5404 IP5_23_20
5405 IP5_19_16
5406 IP5_15_12
5407 IP5_11_8
5408 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5409 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5410 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5411 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5412 IP6_31_28
5413 IP6_27_24
5414 IP6_23_20
5415 IP6_19_16
5416 IP6_15_12
5417 IP6_11_8
5418 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5419 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5420 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5421 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5422 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5423 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5424 IP7_31_28
5425 IP7_27_24
5426 IP7_23_20
5427 IP7_19_16
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5428 /* IP7_15_12 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5429 IP7_11_8
5430 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5431 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5432 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5433 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5434 IP8_31_28
5435 IP8_27_24
5436 IP8_23_20
5437 IP8_19_16
5438 IP8_15_12
5439 IP8_11_8
5440 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5441 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5442 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5443 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5444 IP9_31_28
5445 IP9_27_24
5446 IP9_23_20
5447 IP9_19_16
5448 IP9_15_12
5449 IP9_11_8
5450 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5451 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5452 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5453 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5454 IP10_31_28
5455 IP10_27_24
5456 IP10_23_20
5457 IP10_19_16
5458 IP10_15_12
5459 IP10_11_8
5460 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5461 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5462 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5463 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5464 IP11_31_28
5465 IP11_27_24
5466 IP11_23_20
5467 IP11_19_16
5468 IP11_15_12
5469 IP11_11_8
5470 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5471 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5472 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5473 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5474 IP12_31_28
5475 IP12_27_24
5476 IP12_23_20
5477 IP12_19_16
5478 IP12_15_12
5479 IP12_11_8
5480 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5481 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5482 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5483 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5484 IP13_31_28
5485 IP13_27_24
5486 IP13_23_20
5487 IP13_19_16
5488 IP13_15_12
5489 IP13_11_8
5490 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5491 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5492 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5493 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5494 IP14_31_28
5495 IP14_27_24
5496 IP14_23_20
5497 IP14_19_16
5498 IP14_15_12
5499 IP14_11_8
5500 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5501 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5502 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5503 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5504 IP15_31_28
5505 IP15_27_24
5506 IP15_23_20
5507 IP15_19_16
5508 IP15_15_12
5509 IP15_11_8
5510 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5511 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5512 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5513 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5514 IP16_31_28
5515 IP16_27_24
5516 IP16_23_20
5517 IP16_19_16
5518 IP16_15_12
5519 IP16_11_8
5520 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5521 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5522 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5523 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5524 IP17_31_28
5525 IP17_27_24
5526 IP17_23_20
5527 IP17_19_16
5528 IP17_15_12
5529 IP17_11_8
5530 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5531 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5532 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5533 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5534 GROUP(-24, 4, 4),
5535 GROUP(
5536 /* IP18_31_8 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5537 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5538 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5539 },
5540#undef F_
5541#undef FM
5542
5543#define F_(x, y) x,
5544#define FM(x) FN_##x,
5545 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5546 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5547 1, 1, 1, 2, 2, 1, 2, -3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5548 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5549 MOD_SEL0_31_30_29
5550 MOD_SEL0_28_27
5551 MOD_SEL0_26_25_24
5552 MOD_SEL0_23
5553 MOD_SEL0_22
5554 MOD_SEL0_21
5555 MOD_SEL0_20
5556 MOD_SEL0_19
5557 MOD_SEL0_18_17
5558 MOD_SEL0_16
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5559 /* RESERVED 15 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5560 MOD_SEL0_14_13
5561 MOD_SEL0_12
5562 MOD_SEL0_11
5563 MOD_SEL0_10
5564 MOD_SEL0_9_8
5565 MOD_SEL0_7_6
5566 MOD_SEL0_5
5567 MOD_SEL0_4_3
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5568 /* RESERVED 2, 1, 0 */ ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5569 },
5570 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5571 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5572 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5573 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5574 MOD_SEL1_31_30
5575 MOD_SEL1_29_28_27
5576 MOD_SEL1_26
5577 MOD_SEL1_25_24
5578 MOD_SEL1_23_22_21
5579 MOD_SEL1_20
5580 MOD_SEL1_19
5581 MOD_SEL1_18_17
5582 MOD_SEL1_16
5583 MOD_SEL1_15_14
5584 MOD_SEL1_13
5585 MOD_SEL1_12
5586 MOD_SEL1_11
5587 MOD_SEL1_10
5588 MOD_SEL1_9
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5589 /* RESERVED 8, 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5590 MOD_SEL1_6
5591 MOD_SEL1_5
5592 MOD_SEL1_4
5593 MOD_SEL1_3
5594 MOD_SEL1_2
5595 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5596 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5597 },
5598 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5599 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5600 -16, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5601 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5602 MOD_SEL2_31
5603 MOD_SEL2_30
5604 MOD_SEL2_29
5605 MOD_SEL2_28_27
5606 MOD_SEL2_26
5607 MOD_SEL2_25_24_23
5608 MOD_SEL2_22
5609 MOD_SEL2_21
5610 MOD_SEL2_20
5611 MOD_SEL2_19
5612 MOD_SEL2_18
5613 MOD_SEL2_17
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5614 /* RESERVED 16-1 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5615 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5616 },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]5617 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5618};
5619
5620static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5621 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5622 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5623 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5624 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5625 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5626 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5627 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5628 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5629 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5630 } },
5631 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5632 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5633 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5634 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5635 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5636 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5637 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5638 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5639 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5640 } },
5641 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5642 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5643 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5644 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5645 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5646 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5647 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5648 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5649 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5650 } },
5651 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5652 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5653 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5654 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5655 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5656 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5657 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5658 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5659 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5660 } },
5661 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5662 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5663 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5664 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5665 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5666 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5667 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5668 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5669 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5670 } },
5671 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5672 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5673 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5674 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5675 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5676 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5677 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5678 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5679 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5680 } },
5681 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5682 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5683 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5684 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5685 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5686 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5687 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5688 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5689 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5690 } },
5691 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5692 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5693 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5694 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5695 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5696 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5697 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5698 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5699 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5700 } },
5701 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5702 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5703 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5704 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5705 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5706 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5707 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5708 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5709 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5710 } },
5711 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5712 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5713 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5714 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5715 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5716 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5717 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5718 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5719 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5720 } },
5721 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5722 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5723 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5724 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5725 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5726 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5727 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5728 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5729 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5730 } },
5731 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5732 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5733 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5734 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5735 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5736 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5737 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5738 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5739 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5740 } },
5741 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5742 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5743 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5744 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5745 } },
5746 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5747 { PIN_TDO, 28, 2 }, /* TDO */
5748 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5749 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5750 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5751 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5752 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5753 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5754 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5755 } },
5756 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5757 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5758 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5759 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5760 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5761 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5762 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5763 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5764 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5765 } },
5766 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5767 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5768 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5769 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5770 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5771 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5772 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5773 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5774 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5775 } },
5776 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5777 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5778 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5779 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5780 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5781 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5782 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5783 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5784 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5785 } },
5786 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5787 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5788 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5789 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5790 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5791 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5792 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5793 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5794 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5795 } },
5796 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5797 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5798 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5799 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5800 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5801 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5802 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5803 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5804 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5805 } },
5806 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5807 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5808 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5809 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5810 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5811 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5812 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5813 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5814 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5815 } },
5816 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5817 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5818 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5819 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5820 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5821 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5822 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5823 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5824 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5825 } },
5826 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5827 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5828 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5829 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5830 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5831 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5832 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5833 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5834 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5835 } },
5836 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5837 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5838 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5839 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5840 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5841 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5842 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5843 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5844 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5845 } },
5846 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5847 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5848 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5849 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5850 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5851 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5852 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5853 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5854 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5855 } },
5856 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5857 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5858 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5859 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5860 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5861 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5862 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5863 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5864 } },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]5865 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5866};
5867
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5868enum ioctrl_regs {
5869 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5870 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5871};
5872
5873static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5874 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5875 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]5876 { /* sentinel */ }
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5877};
5878
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5879static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5880{
5881 int bit = -EINVAL;
5882
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5883 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5884
5885 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5886 bit = pin & 0x1f;
5887
5888 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5889 bit = (pin & 0x1f) + 12;
5890
5891 return bit;
5892}
5893
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5894static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5895 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5896 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5897 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5898 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5899 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5900 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5901 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5902 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5903 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5904 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5905 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5906 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5907 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5908 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5909 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5910 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5911 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5912 [16] = PIN_AVB_RXC, /* AVB_RXC */
5913 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5914 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5915 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5916 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5917 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5918 [22] = PIN_AVB_TXC, /* AVB_TXC */
5919 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5920 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5921 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5922 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5923 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5924 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5925 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5926 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5927 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5928 } },
5929 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5930 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5931 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5932 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5933 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5934 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5935 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5936 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5937 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5938 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5939 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5940 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5941 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5942 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5943 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5944 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5945 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5946 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5947 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5948 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5949 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5950 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5951 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5952 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5953 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5954 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5955 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5956 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5957 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5958 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5959 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5960 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5961 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5962 } },
5963 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5964 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5965 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5966 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5967 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5968 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5969 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5970 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5971 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5972 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5973 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5974 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5975 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5976 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5977 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5978 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5979 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5980 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5981 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5982 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5983 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5984 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5985 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5986 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5987 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5988 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5989 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5990 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5991 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5992 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5993 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5994 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5995 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5996 } },
5997 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5998 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5999 [ 1] = SH_PFC_PIN_NONE,
6000 [ 2] = PIN_FSCLKST, /* FSCLKST */
6001 [ 3] = PIN_EXTALR, /* EXTALR*/
6002 [ 4] = PIN_TRST_N, /* TRST# */
6003 [ 5] = PIN_TCK, /* TCK */
6004 [ 6] = PIN_TMS, /* TMS */
6005 [ 7] = PIN_TDI, /* TDI */
6006 [ 8] = SH_PFC_PIN_NONE,
6007 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6008 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6009 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6010 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6011 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6012 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6013 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6014 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6015 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6016 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6017 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6018 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6019 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6020 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6021 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6022 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6023 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6024 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6025 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6026 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6027 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6028 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6029 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6030 } },
6031 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6032 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6033 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6034 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6035 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6036 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6037 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6038 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6039 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6040 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6041 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6042 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6043 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6044 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6045 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6046 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6047 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6048 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6049 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6050 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6051 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6052 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6053 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6054 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6055 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6056 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6057 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6058 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6059 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6060 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6061 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6062 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6063 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6064 } },
6065 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6066 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6067 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6068 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6069 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6070 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6071 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6072 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6073 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6074 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6075 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6076 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6077 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6078 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6079 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6080 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6081 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6082 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6083 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6084 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6085 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6086 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6087 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6088 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6089 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6090 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6091 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6092 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6093 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6094 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6095 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6096 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6097 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6098 } },
6099 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6100 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6101 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6102 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6103 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6104 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6105 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6106 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6107 [ 7] = PIN_PRESET_N, /* PRESET# */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6108 [ 8] = SH_PFC_PIN_NONE,
6109 [ 9] = SH_PFC_PIN_NONE,
6110 [10] = SH_PFC_PIN_NONE,
6111 [11] = SH_PFC_PIN_NONE,
6112 [12] = SH_PFC_PIN_NONE,
6113 [13] = SH_PFC_PIN_NONE,
6114 [14] = SH_PFC_PIN_NONE,
6115 [15] = SH_PFC_PIN_NONE,
6116 [16] = SH_PFC_PIN_NONE,
6117 [17] = SH_PFC_PIN_NONE,
6118 [18] = SH_PFC_PIN_NONE,
6119 [19] = SH_PFC_PIN_NONE,
6120 [20] = SH_PFC_PIN_NONE,
6121 [21] = SH_PFC_PIN_NONE,
6122 [22] = SH_PFC_PIN_NONE,
6123 [23] = SH_PFC_PIN_NONE,
6124 [24] = SH_PFC_PIN_NONE,
6125 [25] = SH_PFC_PIN_NONE,
6126 [26] = SH_PFC_PIN_NONE,
6127 [27] = SH_PFC_PIN_NONE,
6128 [28] = SH_PFC_PIN_NONE,
6129 [29] = SH_PFC_PIN_NONE,
6130 [30] = SH_PFC_PIN_NONE,
6131 [31] = SH_PFC_PIN_NONE,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6132 } },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]6133 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6134};
6135
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6136static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6137 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6138 .get_bias = rcar_pinmux_get_bias,
6139 .set_bias = rcar_pinmux_set_bias,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6140};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6141
6142#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6143const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6144 .name = "r8a774a1_pfc",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6145 .ops = &r8a7796_pfc_ops,
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6146 .unlock_reg = 0xe6060000, /* PMMR */
6147
6148 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6149
6150 .pins = pinmux_pins,
6151 .nr_pins = ARRAY_SIZE(pinmux_pins),
6152 .groups = pinmux_groups.common,
6153 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6154 .functions = pinmux_functions.common,
6155 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6156
6157 .cfg_regs = pinmux_config_regs,
6158 .drive_regs = pinmux_drive_regs,
6159 .bias_regs = pinmux_bias_regs,
6160 .ioctrl_regs = pinmux_ioctrl_regs,
6161
6162 .pinmux_data = pinmux_data,
6163 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6164};
6165#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6166
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6167#ifdef CONFIG_PINCTRL_PFC_R8A77960
6168const struct sh_pfc_soc_info r8a77960_pinmux_info = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6169 .name = "r8a77960_pfc",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6170 .ops = &r8a7796_pfc_ops,
6171 .unlock_reg = 0xe6060000, /* PMMR */
6172
6173 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6174
6175 .pins = pinmux_pins,
6176 .nr_pins = ARRAY_SIZE(pinmux_pins),
6177 .groups = pinmux_groups.common,
6178 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6179 ARRAY_SIZE(pinmux_groups.automotive),
6180 .functions = pinmux_functions.common,
6181 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6182 ARRAY_SIZE(pinmux_functions.automotive),
6183
6184 .cfg_regs = pinmux_config_regs,
6185 .drive_regs = pinmux_drive_regs,
6186 .bias_regs = pinmux_bias_regs,
6187 .ioctrl_regs = pinmux_ioctrl_regs,
6188
6189 .pinmux_data = pinmux_data,
6190 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6191};
6192#endif
6193
6194#ifdef CONFIG_PINCTRL_PFC_R8A77961
6195const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6196 .name = "r8a77961_pfc",
6197 .ops = &r8a7796_pfc_ops,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6198 .unlock_reg = 0xe6060000, /* PMMR */
6199
6200 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6201
6202 .pins = pinmux_pins,
6203 .nr_pins = ARRAY_SIZE(pinmux_pins),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6204 .groups = pinmux_groups.common,
6205 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6206 ARRAY_SIZE(pinmux_groups.automotive),
6207 .functions = pinmux_functions.common,
6208 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6209 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6210
6211 .cfg_regs = pinmux_config_regs,
6212 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6213 .bias_regs = pinmux_bias_regs,
6214 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6215
6216 .pinmux_data = pinmux_data,
6217 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6218};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6219#endif