blob: 18bd640a68b60a9ba8a87fcd1d5489140653c344 [file] [log] [blame]
Masahiro Yamada92b8c2f2016-01-12 16:36:38 +09001menu "Clock"
2
Simon Glass36ad2342015-06-23 15:39:15 -06003config CLK
4 bool "Enable clock driver support"
5 depends on DM
6 help
7 This allows drivers to be provided for clock generators, including
8 oscillators and PLLs. Devices can use a common clock API to request
9 a particular clock rate and check on available clocks. Clocks can
10 feed into other clocks in a tree structure, with multiplexers to
11 choose the source for each clock.
12
Masahiro Yamadab16de452015-08-12 07:31:46 +090013config SPL_CLK
Simon Glass36ad2342015-06-23 15:39:15 -060014 bool "Enable clock support in SPL"
Wenyou Yange4cf4132017-07-31 15:21:57 +080015 depends on CLK && SPL && SPL_DM
Simon Glass36ad2342015-06-23 15:39:15 -060016 help
17 The clock subsystem adds a small amount of overhead to the image.
18 If this is acceptable and you have a need to use clock drivers in
19 SPL, enable this option. It might provide a cleaner interface to
20 setting up clocks within SPL, and allows the same drivers to be
21 used as U-Boot proper.
Masahiro Yamada92b8c2f2016-01-12 16:36:38 +090022
Philipp Tomsich592c3db2017-06-29 01:45:01 +020023config TPL_CLK
24 bool "Enable clock support in TPL"
25 depends on CLK && TPL_DM
26 help
27 The clock subsystem adds a small amount of overhead to the image.
28 If this is acceptable and you have a need to use clock drivers in
29 SPL, enable this option. It might provide a cleaner interface to
30 setting up clocks within TPL, and allows the same drivers to be
31 used as U-Boot proper.
32
Simon Glasse7ca7da2022-04-30 00:56:53 -060033config VPL_CLK
34 bool "Enable clock support in VPL"
35 depends on CLK && VPL_DM
36 help
37 The clock subsystem adds a small amount of overhead to the image.
38 If this is acceptable and you have a need to use clock drivers in
39 SPL, enable this option. It might provide a cleaner interface to
40 setting up clocks within TPL, and allows the same drivers to be
41 used as U-Boot proper.
42
43config CLK_BCM6345
44 bool "Clock controller driver for BCM6345"
45 depends on CLK && ARCH_BMIPS
46 default y
47 help
48 This clock driver adds support for enabling and disabling peripheral
49 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
50
51config CLK_BOSTON
52 def_bool y if TARGET_BOSTON
53 depends on CLK
54 select REGMAP
55 select SYSCON
56 help
57 Enable this to support the clocks
58
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020059config SPL_CLK_CCF
Michal Simek293bbb52024-04-16 08:55:15 +020060 bool "SPL Common Clock Framework [CCF] support"
Adam Fordac4d80e2019-08-24 13:50:34 -050061 depends on SPL
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020062 help
63 Enable this option if you want to (re-)use the Linux kernel's Common
64 Clock Framework [CCF] code in U-Boot's SPL.
65
Peng Fan2d9bd932019-07-31 07:01:54 +000066config SPL_CLK_COMPOSITE_CCF
Michal Simek293bbb52024-04-16 08:55:15 +020067 bool "SPL Common Clock Framework [CCF] composite clk support"
Peng Fan2d9bd932019-07-31 07:01:54 +000068 depends on SPL_CLK_CCF
69 help
70 Enable this option if you want to (re-)use the Linux kernel's Common
71 Clock Framework [CCF] composite code in U-Boot's SPL.
72
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020073config CLK_CCF
Michal Simek293bbb52024-04-16 08:55:15 +020074 bool "Common Clock Framework [CCF] support"
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020075 help
76 Enable this option if you want to (re-)use the Linux kernel's Common
77 Clock Framework [CCF] code in U-Boot's clock driver.
78
Peng Fan2d9bd932019-07-31 07:01:54 +000079config CLK_COMPOSITE_CCF
Michal Simek293bbb52024-04-16 08:55:15 +020080 bool "Common Clock Framework [CCF] composite clk support"
Peng Fan2d9bd932019-07-31 07:01:54 +000081 depends on CLK_CCF
82 help
83 Enable this option if you want to (re-)use the Linux kernel's Common
84 Clock Framework [CCF] composite code in U-Boot's clock driver.
85
Marek Vasut59ee41c2023-08-14 01:51:27 +020086config CLK_GPIO
87 bool "GPIO-controlled clock gate driver"
88 depends on CLK
89 help
90 Enable this option to add GPIO-controlled clock gate driver.
91
92config SPL_CLK_GPIO
93 bool "GPIO-controlled clock gate driver in SPL"
94 depends on SPL_CLK
95 help
96 Enable this option to add GPIO-controlled clock gate driver
97 in U-Boot SPL.
98
Caleb Connollyd2e24c12025-02-10 16:27:25 +000099config CLK_STUB
100 bool "Stub clock driver"
101 depends on CLK
102 help
103 Enable this to provide a stub clock driver for non-essential clock
104 controllers.
105
Sean Andersond1f48b52021-12-15 11:36:19 -0500106config CLK_BCM6345
107 bool "Clock controller driver for BCM6345"
108 depends on CLK && ARCH_BMIPS
109 default y
110 help
111 This clock driver adds support for enabling and disabling peripheral
112 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
113
114config CLK_BOSTON
115 def_bool y if TARGET_BOSTON
116 depends on CLK
117 select REGMAP
118 select SYSCON
119 help
120 Enable this to support the clocks
121
122config CLK_CDCE9XX
123 bool "Enable CDCD9XX clock driver"
124 depends on CLK
125 help
126 Enable the clock synthesizer driver for CDCE913/925/937/949
127 series of chips.
128
Sean Anderson35b37542021-12-15 11:36:20 -0500129config CLK_ICS8N3QV01
Sean Andersond1f48b52021-12-15 11:36:19 -0500130 bool "Enable ICS8N3QV01 VCXO driver"
131 depends on CLK
132 help
133 Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
134 Crystal Oscillator). The output frequency can be programmed via an
135 I2C interface.
136
Simon Glass6eb4e3c2020-02-06 09:54:53 -0700137config CLK_INTEL
138 bool "Enable clock driver for Intel x86"
139 depends on CLK && X86
140 help
141 This provides very basic support for clocks on Intel SoCs. The driver
142 is barely used at present but could be expanded as needs arise.
143 Much clock configuration in U-Boot is either set up by the FSP, or
144 set up by U-Boot itself but only statically. Thus the driver does not
145 support changing clock rates, only querying them.
146
Sean Andersond1f48b52021-12-15 11:36:19 -0500147config CLK_K210
148 bool "Clock support for Kendryte K210"
149 depends on CLK
150 help
151 This enables support clock driver for Kendryte K210 platforms.
152
153config CLK_K210_SET_RATE
154 bool "Enable setting the Kendryte K210 PLL rate"
155 depends on CLK_K210
156 help
157 Add functionality to calculate new rates for K210 PLLs. Enabling this
158 feature adds around 1K to U-Boot's final size.
159
160config CLK_MPC83XX
161 bool "Enable MPC83xx clock driver"
162 depends on CLK
163 help
164 Support for the clock driver of the MPC83xx series of SoCs.
165
Stefan Roese560b07f2020-07-30 13:56:16 +0200166config CLK_OCTEON
167 bool "Clock controller driver for Marvell MIPS Octeon"
168 depends on CLK && ARCH_OCTEON
169 default y
170 help
171 Enable this to support the clocks on Octeon MIPS platforms.
172
Sean Andersond1f48b52021-12-15 11:36:19 -0500173config SANDBOX_CLK_CCF
Michal Simek293bbb52024-04-16 08:55:15 +0200174 bool "Sandbox Common Clock Framework [CCF] support"
Sean Andersond1f48b52021-12-15 11:36:19 -0500175 depends on SANDBOX
176 select CLK_CCF
177 help
178 Enable this option if you want to test the Linux kernel's Common
179 Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
180
181config CLK_SCMI
182 bool "Enable SCMI clock driver"
AKASHI Takahirof6a07382023-06-12 10:14:49 +0900183 depends on CLK
Sean Andersond1f48b52021-12-15 11:36:19 -0500184 depends on SCMI_FIRMWARE
185 help
186 Enable this option if you want to support clock devices exposed
187 by a SCMI agent based on SCMI clock protocol communication
188 with a SCMI server.
189
Jonas Karlman3cf87082023-04-17 19:07:18 +0000190config SPL_CLK_SCMI
191 bool "Enable SCMI clock driver in SPL"
192 depends on SCMI_FIRMWARE && SPL_FIRMWARE
193 help
194 Enable this option if you want to support clock devices exposed
195 by a SCMI agent based on SCMI clock protocol communication
196 with a SCMI server in SPL.
197
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300198config CLK_HSDK
Eugeniy Paltsev6bd63fc2020-05-07 22:20:10 +0300199 bool "Enable cgu clock driver for HSDK boards"
200 depends on CLK && TARGET_HSDK
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300201 help
Eugeniy Paltsev6bd63fc2020-05-07 22:20:10 +0300202 Enable this to support the cgu clocks on Synopsys ARC HSDK and
203 Synopsys ARC HSDK-4xD boards
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300204
Sean Andersond1f48b52021-12-15 11:36:19 -0500205config CLK_VERSACLOCK
206 tristate "Enable VersaClock 5/6 devices"
207 depends on CLK
208 depends on CLK_CCF
209 depends on OF_CONTROL
210 help
211 This driver supports the IDT VersaClock 5 and VersaClock 6
212 programmable clock generators.
213
Siva Durga Prasad Paladuguf7a71202019-06-23 12:24:57 +0530214config CLK_VERSAL
215 bool "Enable clock driver support for Versal"
Jay Buddhabhattid52796d2022-09-19 14:21:05 +0200216 depends on (ARCH_VERSAL || ARCH_VERSAL_NET)
Algapally Santosh Sagarbf34dd42023-02-01 02:55:53 -0700217 imply ZYNQMP_FIRMWARE
Siva Durga Prasad Paladuguf7a71202019-06-23 12:24:57 +0530218 help
219 This clock driver adds support for clock realted settings for
220 Versal platform.
221
Liviu Dudauba024e62018-09-17 17:50:00 +0100222config CLK_VEXPRESS_OSC
223 bool "Enable driver for Arm Versatile Express OSC clock generators"
224 depends on CLK && VEXPRESS_CONFIG
225 help
226 This clock driver adds support for clock generators present on
227 Arm Versatile Express platforms.
228
Zhengxun39df0532021-06-11 15:10:48 +0000229config CLK_XLNX_CLKWZRD
230 bool "Xilinx Clocking Wizard"
231 depends on CLK
232 help
233 Support for the Xilinx Clocking Wizard IP core clock generator.
234 The wizard support for dynamically reconfiguring the clocking
235 primitives for Multiply, Divide, Phase Shift/Offset, or Duty
236 Cycle. Limited by U-Boot clk uclass without set_phase API and
237 set_duty_cycle API, this driver only supports set_rate to modify
238 the frequency.
239
Sean Andersond1f48b52021-12-15 11:36:19 -0500240config CLK_ZYNQ
241 bool "Enable clock driver support for Zynq"
242 depends on CLK && ARCH_ZYNQ
243 default y
244 help
245 This clock driver adds support for clock related settings for
246 Zynq platform.
247
Siva Durga Prasad Paladugu468b55f2016-11-15 16:15:41 +0530248config CLK_ZYNQMP
249 bool "Enable clock driver support for ZynqMP"
250 depends on ARCH_ZYNQMP
Algapally Santosh Sagarbf34dd42023-02-01 02:55:53 -0700251 imply ZYNQMP_FIRMWARE
Siva Durga Prasad Paladugu468b55f2016-11-15 16:15:41 +0530252 help
253 This clock driver adds support for clock realted settings for
254 ZynqMP platform.
255
Tom Rinidec7ea02024-05-20 13:35:03 -0600256source "drivers/clk/adi/Kconfig"
Anup Patel00a156d2019-06-25 06:31:02 +0000257source "drivers/clk/analogbits/Kconfig"
Wenyou Yang8c772bd2016-07-20 17:55:12 +0800258source "drivers/clk/at91/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530259source "drivers/clk/exynos/Kconfig"
Peng Fan5e80d5a2018-10-18 14:28:30 +0200260source "drivers/clk/imx/Kconfig"
Jerome Brunet3da39a82019-02-10 14:54:30 +0100261source "drivers/clk/meson/Kconfig"
Padmarao Begari0c4ae802021-01-15 08:20:38 +0530262source "drivers/clk/microchip/Kconfig"
Marek BehĂșn61d74e82018-04-24 17:21:25 +0200263source "drivers/clk/mvebu/Kconfig"
Manivannan Sadhasivam91a85132018-06-14 23:38:35 +0530264source "drivers/clk/owl/Kconfig"
Caleb Connolly878b26a2023-11-07 12:40:59 +0000265source "drivers/clk/qcom/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530266source "drivers/clk/renesas/Kconfig"
Kongyang Liu80bf1f72024-06-11 17:41:14 +0800267source "drivers/clk/sophgo/Kconfig"
Jagan Teki1d150b42018-12-22 21:32:49 +0530268source "drivers/clk/sunxi/Kconfig"
Anup Patel42fdf082019-02-25 08:14:49 +0000269source "drivers/clk/sifive/Kconfig"
Yanhong Wang5a85d052023-03-29 11:42:13 +0800270source "drivers/clk/starfive/Kconfig"
Patrick Delaunay12427612022-05-19 17:56:45 +0200271source "drivers/clk/stm32/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530272source "drivers/clk/tegra/Kconfig"
Dario Binacchida3b0202020-12-30 00:06:32 +0100273source "drivers/clk/ti/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530274source "drivers/clk/uniphier/Kconfig"
Masahiro Yamadae4dfb052016-02-02 21:11:32 +0900275
Masahiro Yamada92b8c2f2016-01-12 16:36:38 +0900276endmenu