blob: 47606ede9d6d009426311cc2937ead288d131725 [file] [log] [blame]
Svyatoslav Ryhel7a25c382023-06-30 10:29:03 +03001// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "tegra30-asus-transformer.dtsi"
5
6/ {
7 model = "ASUS Transformer Infinity TF700T";
8 compatible = "asus,tf700t", "nvidia,tegra30";
9
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +030010 host1x@50000000 {
11 dc@54200000 {
12 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
13 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
14
15 rgb {
16 status = "okay";
17
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +020018 /delete-property/ nvidia,panel;
19
20 port {
21 dpi_output: endpoint {
22 remote-endpoint = <&bridge_input>;
23 bus-width = <24>;
24 };
25 };
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +030026 };
27 };
28 };
Svyatoslav Ryhel7a25c382023-06-30 10:29:03 +030029
Svyatoslav Ryhelf3947d42023-11-27 19:20:21 +020030 pinmux@70000868 {
31 state_default: pinmux {
32 lcd_pwr2_pc6 {
33 nvidia,pins = "lcd_pwr2_pc6",
34 "lcd_dc1_pd2";
35 nvidia,function = "displaya";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
39 };
40
41 pbb3 {
42 nvidia,pins = "pbb3";
43 nvidia,function = "vgp3";
44 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45 nvidia,tristate = <TEGRA_PIN_DISABLE>;
46 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
47 };
48
49 spi2_mosi_px0 {
50 nvidia,pins = "spi2_mosi_px0";
51 nvidia,function = "spi2";
52 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
53 nvidia,tristate = <TEGRA_PIN_DISABLE>;
54 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
55 };
56
57 pbb7 {
58 nvidia,pins = "pbb7";
59 nvidia,function = "i2s4";
60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61 nvidia,tristate = <TEGRA_PIN_DISABLE>;
62 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
63 };
64
65 kb_row7_pr7 {
66 nvidia,pins = "kb_row7_pr7";
67 nvidia,function = "kbc";
68 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
69 nvidia,tristate = <TEGRA_PIN_DISABLE>;
70 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
71 };
72
73 gmi_cs4_n_pk2 {
74 nvidia,pins = "gmi_cs4_n_pk2";
75 nvidia,function = "gmi";
76 nvidia,pull = <TEGRA_PIN_PULL_UP>;
77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
78 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
79 };
80 };
81 };
82
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +030083 tc358768_refclk: clock-tc358768 {
84 compatible = "fixed-clock";
85 clock-frequency = <23100000>;
86 clock-accuracy = <100>;
87 #clock-cells = <0>;
88 };
89
90 tc358768_osc: clock-tc358768-osc-gate {
91 compatible = "gpio-gate-clock";
92 enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>;
93 clocks = <&tc358768_refclk>;
94 #clock-cells = <0>;
95 };
96
97 i2c-mux {
98 compatible = "i2c-mux-gpio";
99
100 mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>;
101 i2c-parent = <&gen1_i2c>;
102 idle-state = <0x0>;
103
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 i2c@1 {
108 reg = <1>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 tc358768: dsi@7 {
113 compatible = "toshiba,tc358768";
114 reg = <0x7>;
115
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 clocks = <&tc358768_osc>;
120 clock-names = "refclk";
121
122 reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
123
124 vddc-supply = <&vdd_1v2_mipi>;
125 vddio-supply = <&vdd_1v8_vio>;
126 vddmipi-supply = <&vdd_1v2_mipi>;
127
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200128 /*
129 * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
130 * LCD SuperIPS+ Full HD panel.
131 */
132 panel@1 {
133 compatible = "panasonic,vvx10f004b00";
134 reg = <1>;
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300135
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200136 power-supply = <&vdd_pnl_reg>;
137 backlight = <&backlight>;
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300138
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200139 display-timings {
140 timing@0 {
141 /* 1920x1200@60Hz */
142 clock-frequency = <154000000>;
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300143
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200144 hactive = <1920>;
145 hfront-porch = <48>;
146 hback-porch = <80>;
147 hsync-len = <32>;
148 hsync-active = <1>;
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300149
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200150 vactive = <1200>;
151 vfront-porch = <3>;
152 vback-porch = <26>;
153 vsync-len = <6>;
154 vsync-active = <1>;
155 };
156 };
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300157
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200158 port {
159 panel_input: endpoint {
160 remote-endpoint = <&bridge_output>;
161 };
162 };
163 };
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300164
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200165 ports {
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 port@0 {
170 reg = <0>;
171
172 bridge_input: endpoint {
173 remote-endpoint = <&dpi_output>;
174 bus-width = <24>;
175 };
176 };
177
178 port@1 {
179 reg = <1>;
180
181 bridge_output: endpoint {
182 remote-endpoint = <&panel_input>;
183 };
184 };
185 };
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300186 };
187 };
188 };
189
Svyatoslav Ryhel337e7512025-03-04 20:08:55 +0200190 /delete-node/ panel;
191
Svyatoslav Ryhel62dcf422023-04-25 18:21:32 +0300192 vdd_1v2_mipi: regulator-mipi {
193 compatible = "regulator-fixed";
194 regulator-name = "tc358768_1v2_vdd";
195 regulator-min-microvolt = <1200000>;
196 regulator-max-microvolt = <1200000>;
197 regulator-enable-ramp-delay = <10000>;
198 regulator-boot-on;
199 gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>;
200 enable-active-high;
201 };
Svyatoslav Ryhel7a25c382023-06-30 10:29:03 +0300202};