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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / stm32h7-u-boot.dtsi
blob: 9148a1fcd4c419dbb93a7754f9a1d1d29c97045b [file] [log] [blame]
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2
3#include <dt-bindings/memory/stm32-sdram.h>
4
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]5/{
6 clocks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]7 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]8 };
9
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]10 aliases {
11 gpio0 = &gpioa;
12 gpio1 = &gpiob;
13 gpio2 = &gpioc;
14 gpio3 = &gpiod;
15 gpio4 = &gpioe;
16 gpio5 = &gpiof;
17 gpio6 = &gpiog;
18 gpio7 = &gpioh;
19 gpio8 = &gpioi;
20 gpio9 = &gpioj;
21 gpio10 = &gpiok;
22 mmc0 = &sdmmc1;
dillon min8423bfb2021-04-09 15:28:40 +0800[diff] [blame]23 pinctrl0 = &pinctrl;
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]24 };
25
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]26 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]28 pin-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]30 };
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]31
32 fmc: fmc@52004000 {
33 compatible = "st,stm32h7-fmc";
34 reg = <0x52004000 0x1000>;
35 clocks = <&rcc FMC_CK>;
36
37 pinctrl-0 = <&fmc_pins>;
38 pinctrl-names = "default";
39 status = "okay";
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]40 };
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]41 };
42};
43
44&clk_hse {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]46};
47
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]48&clk_i2s {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]50};
51
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]52&clk_lse {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]54};
55
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]56&fmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]58};
59
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]60&gpioa {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]62 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]63};
64
65&gpiob {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]67 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]68};
69
70&gpioc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]72 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]73};
74
75&gpiod {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]77 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]78};
79
80&gpioe {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]82 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]83};
84
85&gpiof {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]87 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]88};
89
90&gpiog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]92 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]93};
94
95&gpioh {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]97 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]98};
99
100&gpioi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]102 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]103};
104
105&gpioj {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]107 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]108};
109
110&gpiok {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]112 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]113};
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]114
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]115&pwrcfg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-all;
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]117};
118
119&rcc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-all;
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]121};
Patrick Delaunayc5c90692019-11-06 16:16:32 +0100[diff] [blame]122
123&sdmmc1 {
124 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
125};
Patrice Chotard82270812020-11-06 08:11:59 +0100[diff] [blame]126
127&timer5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-all;
Patrice Chotard82270812020-11-06 08:11:59 +0100[diff] [blame]129};
dillon min8423bfb2021-04-09 15:28:40 +0800[diff] [blame]130
131&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-all;
dillon min8423bfb2021-04-09 15:28:40 +0800[diff] [blame]133};