ARM: dts: stm32: DT alignment with kernel v5.3
Device tree and binding alignment with kernel v5.3
and converted to SPDX.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 99fa0e6..361c8e5 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -61,17 +61,6 @@
st,sdram-refcount = <1539>;
};
};
-
- sdmmc1: sdmmc@52007000 {
- compatible = "st,stm32-sdmmc2";
- reg = <0x52007000 0x1000>;
- interrupts = <49>;
- clocks = <&rcc SDMMC1_CK>;
- resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
- st,idma = <1>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- };
};
};
@@ -213,35 +202,9 @@
<STM32_PINMUX('I', 9, AF12)>,
<STM32_PINMUX('I',10, AF12)>;
- slew-rate = <3>;
- };
- };
-
- pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
- pins {
- pinmux = <STM32_PINMUX('B', 8, AF7)>,
- <STM32_PINMUX('B', 9, AF7)>,
- <STM32_PINMUX('C', 6, AF8)>,
- <STM32_PINMUX('C', 7, AF8)>;
- drive-push-pull;
slew-rate = <3>;
};
};
-
- sdmmc1_pins: sdmmc@0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>,
- <STM32_PINMUX('C', 9, AF12)>,
- <STM32_PINMUX('C',10, AF12)>,
- <STM32_PINMUX('C',11, AF12)>,
- <STM32_PINMUX('C',12, AF12)>,
- <STM32_PINMUX('D', 2, AF12)>;
-
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
};
&pwrcfg {
@@ -251,3 +214,7 @@
&rcc {
u-boot,dm-pre-reloc;
};
+
+&sdmmc1 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+};