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git01.mediatek.com / filogic / uboot / 5e3dfbeb29f2caf4079e1d72cfc0ffcb6b1ed346 / . / include / configs / theadorable.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]2/*
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]4 */
5
6#ifndef _CONFIG_THEADORABLE_H
7#define _CONFIG_THEADORABLE_H
8
Tom Rini51556652021-08-21 13:50:14 -0400[diff] [blame]9#include <linux/sizes.h>
10
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]11/*
12 * High Level Configuration Options (easy to change)
13 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]14
15/*
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
18 * U-Boot into it.
19 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]20
21/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]22 * The debugging version enables USB support via defconfig.
23 * This version should also enable all other non-production
24 * interfaces / features.
25 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]26
27/* I2C */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]28#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese07b5e042016-04-08 15:58:29 +0200[diff] [blame]29#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]30
31/* USB/EHCI configuration */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]32#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
33
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]34/* Environment in SPI NOR flash */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]35
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]36#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
37
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]38/* Keep device tree and initrd in lower memory so the kernel can access them */
39#define CONFIG_EXTRA_ENV_SETTINGS \
40 "fdt_high=0x10000000\0" \
41 "initrd_high=0x10000000\0"
42
43/* SATA support */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]44#define CONFIG_LBA48
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]45
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]46/* FPGA programming support */
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]47#define CONFIG_FPGA_STRATIX_V
48
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]49/*
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]50 * Bootcounter
51 */
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]52/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
53#define BOOTCOUNT_ADDR 0x1000
54
55/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]56 * mv-common.h should be defined after CMD configs since it used them
57 * to enable certain macros
58 */
59#include "mv-common.h"
60
61/*
62 * Memory layout while starting into the bin_hdr via the
63 * BootROM:
64 *
65 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
66 * 0x4000.4030 bin_hdr start address
67 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
68 * 0x4007.fffc BootROM stack top
69 *
70 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
71 * L2 cache thus cannot be used.
72 */
73
74/* SPL */
75/* Defines for SPL */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]76
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]77/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Tom Rini51556652021-08-21 13:50:14 -0400[diff] [blame]78#define CONFIG_SYS_SDRAM_SIZE SZ_2G
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]79
80#endif /* _CONFIG_THEADORABLE_H */