Blame - include/configs/theadorable.h - filogic/uboot

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Tom Rini	10e4779	2018-05-06 17:58:06 -0400	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	2	/*
				3	* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	4	*/
				5
				6	#ifndef _CONFIG_THEADORABLE_H
				7	#define _CONFIG_THEADORABLE_H
				8
Tom Rini	5155665	2021-08-21 13:50:14 -0400	[diff] [blame^]	9	#include <linux/sizes.h>
				10
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	11	/*
				12	* High Level Configuration Options (easy to change)
				13	*/
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	14
				15	/*
				16	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
				17	* for DDR ECC byte filling in the SPL before loading the main
				18	* U-Boot into it.
				19	*/
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	20
				21	/*
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	22	* The debugging version enables USB support via defconfig.
				23	* This version should also enable all other non-production
				24	* interfaces / features.
				25	*/
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	26
				27	/* I2C */
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	28	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese	07b5e04	2016-04-08 15:58:29 +0200	[diff] [blame]	29	#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	30
				31	/* USB/EHCI configuration */
				32	#define CONFIG_EHCI_IS_TDI
				33	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
				34
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	35	/* Environment in SPI NOR flash */
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	36
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	37	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
				38
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	39	/* Keep device tree and initrd in lower memory so the kernel can access them */
				40	#define CONFIG_EXTRA_ENV_SETTINGS \
				41	"fdt_high=0x10000000\0" \
				42	"initrd_high=0x10000000\0"
				43
				44	/* SATA support */
				45	#define CONFIG_SYS_SATA_MAX_DEVICE 1
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	46	#define CONFIG_LBA48
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	47
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	48	/* Enable LCD and reserve 512KB from top of memory*/
				49	#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
				50
Stefan Roese	f054758	2016-02-12 14:24:07 +0100	[diff] [blame]	51	/* FPGA programming support */
Stefan Roese	f054758	2016-02-12 14:24:07 +0100	[diff] [blame]	52	#define CONFIG_FPGA_STRATIX_V
				53
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	54	/*
Stefan Roese	1a4e980	2016-04-07 10:48:14 +0200	[diff] [blame]	55	* Bootcounter
				56	*/
Stefan Roese	1a4e980	2016-04-07 10:48:14 +0200	[diff] [blame]	57	/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
				58	#define BOOTCOUNT_ADDR 0x1000
				59
				60	/*
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	61	* mv-common.h should be defined after CMD configs since it used them
				62	* to enable certain macros
				63	*/
				64	#include "mv-common.h"
				65
				66	/*
				67	* Memory layout while starting into the bin_hdr via the
				68	* BootROM:
				69	*
				70	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
				71	* 0x4000.4030 bin_hdr start address
				72	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
				73	* 0x4007.fffc BootROM stack top
				74	*
				75	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
				76	* L2 cache thus cannot be used.
				77	*/
				78
				79	/* SPL */
				80	/* Defines for SPL */
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	81	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
				82
				83	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
				84	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
				85
				86	#ifdef CONFIG_SPL_BUILD
				87	#define CONFIG_SYS_MALLOC_SIMPLE
				88	#endif
				89
				90	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
				91	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
				92
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	93	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Tom Rini	5155665	2021-08-21 13:50:14 -0400	[diff] [blame^]	94	#define CONFIG_SYS_SDRAM_SIZE SZ_2G
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	95
				96	#endif /* _CONFIG_THEADORABLE_H */