blob: 859fc47030fd32efff8940037a0ae9e4e11e13aa [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Philipp Tomsichd21a4d82017-06-23 00:12:05 +02002/*
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
Philipp Tomsichd21a4d82017-06-23 00:12:05 +02004 */
5
6#include <common.h>
7#include <clk.h>
8#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Philipp Tomsichd21a4d82017-06-23 00:12:05 +020011#include <dt-bindings/memory/rk3368-dmc.h>
12#include <dt-structs.h>
13#include <ram.h>
14#include <regmap.h>
15#include <syscon.h>
16#include <asm/io.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080017#include <asm/arch-rockchip/clock.h>
18#include <asm/arch-rockchip/cru_rk3368.h>
19#include <asm/arch-rockchip/grf_rk3368.h>
Quentin Schulz5e38edb2024-03-11 13:01:56 +010020#include <asm/arch-rockchip/hardware.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080021#include <asm/arch-rockchip/ddr_rk3368.h>
Kever Yange47db832019-11-15 11:04:33 +080022#include <asm/arch-rockchip/sdram.h>
Kever Yangcdbb38a2019-11-15 11:04:32 +080023#include <asm/arch-rockchip/sdram_rk3288.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060024#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060025#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070026#include <linux/err.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060027#include <linux/printk.h>
Philipp Tomsichd21a4d82017-06-23 00:12:05 +020028
Philipp Tomsichd21a4d82017-06-23 00:12:05 +020029struct dram_info {
30 struct ram_info info;
31 struct clk ddr_clk;
32 struct rk3368_cru *cru;
33 struct rk3368_grf *grf;
34 struct rk3368_ddr_pctl *pctl;
35 struct rk3368_ddrphy *phy;
36 struct rk3368_pmu_grf *pmugrf;
37 struct rk3368_msch *msch;
38};
39
40struct rk3368_sdram_params {
41#if CONFIG_IS_ENABLED(OF_PLATDATA)
42 struct dtd_rockchip_rk3368_dmc of_plat;
43#endif
44 struct rk3288_sdram_pctl_timing pctl_timing;
45 u32 trefi_mem_ddr3;
46 struct rk3288_sdram_channel chan;
47 struct regmap *map;
48 u32 ddr_freq;
49 u32 memory_schedule;
50 u32 ddr_speed_bin;
51 u32 tfaw_mult;
52};
53
54/* PTCL bits */
55enum {
56 /* PCTL_DFISTCFG0 */
57 DFI_INIT_START = BIT(0),
58 DFI_DATA_BYTE_DISABLE_EN = BIT(2),
59
60 /* PCTL_DFISTCFG1 */
61 DFI_DRAM_CLK_SR_EN = BIT(0),
62 DFI_DRAM_CLK_DPD_EN = BIT(1),
63 ODT_LEN_BL8_W_SHIFT = 16,
64
65 /* PCTL_DFISTCFG2 */
66 DFI_PARITY_INTR_EN = BIT(0),
67 DFI_PARITY_EN = BIT(1),
68
69 /* PCTL_DFILPCFG0 */
70 TLP_RESP_TIME_SHIFT = 16,
71 LP_SR_EN = BIT(8),
72 LP_PD_EN = BIT(0),
73
74 /* PCTL_DFIODTCFG */
75 RANK0_ODT_WRITE_SEL = BIT(3),
76 RANK1_ODT_WRITE_SEL = BIT(11),
77
78 /* PCTL_SCFG */
79 HW_LOW_POWER_EN = BIT(0),
80
81 /* PCTL_MCMD */
82 START_CMD = BIT(31),
83 MCMD_RANK0 = BIT(20),
84 MCMD_RANK1 = BIT(21),
85 DESELECT_CMD = 0,
86 PREA_CMD,
87 REF_CMD,
88 MRS_CMD,
89 ZQCS_CMD,
90 ZQCL_CMD,
91 RSTL_CMD,
92 MRR_CMD = 8,
93 DPDE_CMD,
94
95 /* PCTL_POWCTL */
96 POWER_UP_START = BIT(0),
97
98 /* PCTL_POWSTAT */
99 POWER_UP_DONE = BIT(0),
100
101 /* PCTL_SCTL */
102 INIT_STATE = 0,
103 CFG_STATE,
104 GO_STATE,
105 SLEEP_STATE,
106 WAKEUP_STATE,
107
108 /* PCTL_STAT */
109 LP_TRIG_SHIFT = 4,
110 LP_TRIG_MASK = 7,
111 PCTL_STAT_MSK = 7,
112 INIT_MEM = 0,
113 CONFIG,
Tom Rini364d0022023-01-10 11:19:45 -0500114 CFG_REQ,
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200115 ACCESS,
116 ACCESS_REQ,
117 LOW_POWER,
118 LOW_POWER_ENTRY_REQ,
119 LOW_POWER_EXIT_REQ,
120
121 /* PCTL_MCFG */
122 DDR2_DDR3_BL_8 = BIT(0),
123 DDR3_EN = BIT(5),
124 TFAW_TRRD_MULT4 = (0 << 18),
125 TFAW_TRRD_MULT5 = (1 << 18),
126 TFAW_TRRD_MULT6 = (2 << 18),
127};
128
129#define DDR3_MR0_WR(n) \
130 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
131#define DDR3_MR0_CL(n) \
132 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
133#define DDR3_MR0_BL8 \
134 (0 << 0)
135#define DDR3_MR0_DLL_RESET \
136 (1 << 8)
137#define DDR3_MR1_RTT120OHM \
138 ((0 << 9) | (1 << 6) | (0 << 2))
139#define DDR3_MR2_TWL(n) \
140 (((n - 5) & 0x7) << 3)
141
142
143#ifdef CONFIG_TPL_BUILD
144
145static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
146{
147 if (enable)
148 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
149 else
150 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
151}
152
153static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
154{
155 if (ddr3_mode)
156 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
157 else
158 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
159}
160
161static void ddrphy_config(struct rk3368_ddrphy *phy,
162 u32 tcl, u32 tal, u32 tcwl)
163{
164 int i;
165
166 /* Set to DDR3 mode */
167 clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
168
169 /* DDRPHY_REGB: CL, AL */
170 clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
171 /* DDRPHY_REGC: CWL */
172 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
173
174 /* Update drive-strength */
175 writel(0xcc, &phy->reg[0x11]);
176 writel(0xaa, &phy->reg[0x16]);
177 /*
178 * Update NRCOMP/PRCOMP for all 4 channels (for details of all
179 * affected registers refer to the documentation of DDRPHY_REG20
180 * and DDRPHY_REG21 in the RK3368 TRM.
181 */
182 for (i = 0; i < 4; ++i) {
183 writel(0xcc, &phy->reg[0x20 + i * 0x10]);
184 writel(0x44, &phy->reg[0x21 + i * 0x10]);
185 }
186
187 /* Enable write-leveling calibration bypass */
188 setbits_le32(&phy->reg[2], BIT(3));
189}
190
191static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
192{
193 int i;
194
195 for (i = 0; i < n / sizeof(u32); i++)
196 writel(*src++, dest++);
197}
198
199static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
200{
201 u32 mcmd = START_CMD | cmd | rank;
202
203 debug("%s: writing %x to MCMD\n", __func__, mcmd);
204 writel(mcmd, &pctl->mcmd);
205 while (readl(&pctl->mcmd) & START_CMD)
206 /* spin */;
207}
208
209static void send_mrs(struct rk3368_ddr_pctl *pctl,
210 u32 rank, u32 mr_num, u32 mr_data)
211{
212 u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
213
214 debug("%s: writing %x to MCMD\n", __func__, mcmd);
215 writel(mcmd, &pctl->mcmd);
216 while (readl(&pctl->mcmd) & START_CMD)
217 /* spin */;
218}
219
220static int memory_init(struct rk3368_ddr_pctl *pctl,
221 struct rk3368_sdram_params *params)
222{
223 u32 mr[4];
224 const ulong timeout_ms = 500;
225 ulong tmp;
226
227 /*
228 * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
229 * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
230 * of PCTL.
231 */
232 writel(POWER_UP_START, &pctl->powctl);
233
234 tmp = get_timer(0);
235 do {
236 if (get_timer(tmp) > timeout_ms) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900237 pr_err("%s: POWER_UP_START did not complete in %ld ms\n",
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200238 __func__, timeout_ms);
239 return -ETIME;
240 }
241 } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
242
243 /* Configure MR0 through MR3 */
244 mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
245 DDR3_MR0_CL(params->pctl_timing.tcl) |
246 DDR3_MR0_DLL_RESET;
247 mr[1] = DDR3_MR1_RTT120OHM;
248 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
249 mr[3] = 0;
250
251 /*
252 * Also see RK3368 Technical Reference Manual:
253 * "16.6.2 Initialization (DDR3 Initialization Sequence)"
254 */
255 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
256 udelay(1);
257 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
258 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
259 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
260 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
261 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
262 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
263
264 return 0;
265}
266
267static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
268{
269 /*
270 * Also see RK3368 Technical Reference Manual:
271 * "16.6.1 State transition of PCTL (Moving to Config State)"
272 */
273 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
274
275 switch (state) {
276 case LOW_POWER:
277 writel(WAKEUP_STATE, &pctl->sctl);
278 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
279 /* spin */;
280
281 /* fall-through */
282 case ACCESS:
283 case INIT_MEM:
284 writel(CFG_STATE, &pctl->sctl);
285 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
286 /* spin */;
287 break;
288
289 case CONFIG:
290 return;
291
292 default:
293 break;
294 }
295}
296
297static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
298{
299 /*
300 * Also see RK3368 Technical Reference Manual:
301 * "16.6.1 State transition of PCTL (Moving to Access State)"
302 */
303 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
304
305 switch (state) {
306 case LOW_POWER:
307 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
308 LP_TRIG_MASK) == 1)
309 return;
310
311 writel(WAKEUP_STATE, &pctl->sctl);
312 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
313 /* spin */;
314
315 /* fall-through */
316 case INIT_MEM:
317 writel(CFG_STATE, &pctl->sctl);
318 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
319 /* spin */;
320
321 /* fall-through */
322 case CONFIG:
323 writel(GO_STATE, &pctl->sctl);
324 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
325 /* spin */;
326 break;
327
328 case ACCESS:
329 return;
330
331 default:
332 break;
333 }
334}
335
336static void ddrctl_reset(struct rk3368_cru *cru)
337{
338 const u32 ctl_reset = BIT(3) | BIT(2);
339 const u32 phy_reset = BIT(1) | BIT(0);
340
341 /*
342 * The PHY reset should be released before the PCTL reset.
343 *
344 * Note that the following sequence (including the number of
345 * us to delay between releasing the PHY and PCTL reset) has
346 * been adapted per feedback received from Rockchips, so do
347 * not try to optimise.
348 */
349 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
350 udelay(1);
351 rk_clrreg(&cru->softrst_con[10], phy_reset);
352 udelay(5);
353 rk_clrreg(&cru->softrst_con[10], ctl_reset);
354}
355
356static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
357{
358 /*
359 * The analog part of the PHY should be release at least 1000
360 * DRAM cycles before the digital part of the PHY (waiting for
361 * 5us will ensure this for a DRAM clock as low as 200MHz).
362 */
363 clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
364 udelay(1);
365 setbits_le32(&ddrphy->reg[0], BIT(2));
366 udelay(5);
367 setbits_le32(&ddrphy->reg[0], BIT(3));
368}
369
370static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
371{
372 u32 dqs_dll_delay;
373
374 setbits_le32(&ddrphy->reg[0x13], BIT(4));
375 clrbits_le32(&ddrphy->reg[0x14], BIT(3));
376
377 setbits_le32(&ddrphy->reg[0x26], BIT(4));
378 clrbits_le32(&ddrphy->reg[0x27], BIT(3));
379
380 setbits_le32(&ddrphy->reg[0x36], BIT(4));
381 clrbits_le32(&ddrphy->reg[0x37], BIT(3));
382
383 setbits_le32(&ddrphy->reg[0x46], BIT(4));
384 clrbits_le32(&ddrphy->reg[0x47], BIT(3));
385
386 setbits_le32(&ddrphy->reg[0x56], BIT(4));
387 clrbits_le32(&ddrphy->reg[0x57], BIT(3));
388
389 if (freq <= 400000000)
390 setbits_le32(&ddrphy->reg[0xa4], 0x1f);
391 else
392 clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
393
394 if (freq < 681000000)
395 dqs_dll_delay = 3; /* 67.5 degree delay */
396 else
397 dqs_dll_delay = 2; /* 45 degree delay */
398
399 writel(dqs_dll_delay, &ddrphy->reg[0x28]);
400 writel(dqs_dll_delay, &ddrphy->reg[0x38]);
401 writel(dqs_dll_delay, &ddrphy->reg[0x48]);
402 writel(dqs_dll_delay, &ddrphy->reg[0x58]);
403}
404
405static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
406{
407 const ulong timeout_ms = 200;
408 ulong tmp;
409
410 writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
411
412 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
413 &pctl->dfistcfg1);
414 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
415 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
416 &pctl->dfilpcfg0);
417
418 writel(1, &pctl->dfitphyupdtype0);
419
420 writel(0x1f, &pctl->dfitphyrdlat);
421 writel(0, &pctl->dfitphywrdata);
422 writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
423
424 setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
425
426 tmp = get_timer(0);
427 do {
428 if (get_timer(tmp) > timeout_ms) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900429 pr_err("%s: DFI init did not complete within %ld ms\n",
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200430 __func__, timeout_ms);
431 return -ETIME;
432 }
433 } while ((readl(&pctl->dfiststat0) & 1) == 0);
434
435 return 0;
436}
437
438static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
439{
440 const ulong MHz = 1000000;
441 return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
442}
443
444static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
445{
446 return ps_to_tCK(ns * 1000, freq);
447}
448
449static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
450{
451 const ulong MHz = 1000000;
452 return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
453}
454
455static int pctl_calc_timings(struct rk3368_sdram_params *params,
456 ulong freq)
457{
458 struct rk3288_sdram_pctl_timing *pctl_timing = &params->pctl_timing;
459 const ulong MHz = 1000000;
460 u32 tccd;
461 u32 tfaw_as_ps;
462
463 if (params->ddr_speed_bin != DDR3_1600K) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900464 pr_err("%s: unimplemented DDR3 speed bin %d\n",
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200465 __func__, params->ddr_speed_bin);
466 return -1;
467 }
468
469 /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
470 pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
471 pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
472
473 pctl_timing->tinit = 200; /* 200 usec */
474 pctl_timing->trsth = 500; /* 500 usec */
475 pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
476 params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
477
478 if (freq <= (400 * MHz)) {
479 pctl_timing->tcl = 6;
480 pctl_timing->tcwl = 10;
481 } else if (freq <= (533 * MHz)) {
482 pctl_timing->tcl = 8;
483 pctl_timing->tcwl = 6;
484 } else if (freq <= (666 * MHz)) {
485 pctl_timing->tcl = 10;
486 pctl_timing->tcwl = 7;
487 } else {
488 pctl_timing->tcl = 11;
489 pctl_timing->tcwl = 8;
490 }
491
492 pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
493 pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
494 pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
495 /*
496 * JESD-79:
497 * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
498 */
499 tccd = 4;
500 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
501 pctl_timing->tal = 0;
502 pctl_timing->tras = ps_to_tCK(35000, freq);
503 pctl_timing->trc = ps_to_tCK(48750, freq);
504 pctl_timing->trcd = ps_to_tCK(13750, freq);
505 pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
506 pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
507 pctl_timing->twr = ps_to_tCK(15000, freq);
508 /* The DDR3 mode-register does only support even values for tWR > 8. */
509 if (pctl_timing->twr > 8)
510 pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
511 pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
512 pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
513 pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
514 pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
515 pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
516 pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
517 pctl_timing->tdqs = 1; /* fixed for DDR3 */
518 pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
519 pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
520 pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
521 pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
522 pctl_timing->trstl = ns_to_tCK(100, freq);
523 pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
524 pctl_timing->tmrr = 0;
525 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
526 pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
527
528
529 /*
530 * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
531 * We want to use the smallest multiplier that satisfies the tFAW
532 * requirements of the given speed-bin. If necessary, we stretch out
533 * tRRD to allow us to operate on a 6x multiplier for tFAW.
534 */
535 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
536 if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
537 /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
538 pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
539 params->tfaw_mult = TFAW_TRRD_MULT6;
540 } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
541 params->tfaw_mult = TFAW_TRRD_MULT6;
542 } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
543 params->tfaw_mult = TFAW_TRRD_MULT5;
544 } else {
545 params->tfaw_mult = TFAW_TRRD_MULT4;
546 }
547
548 return 0;
549}
550
551static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
552 struct rk3368_sdram_params *params,
553 struct rk3368_grf *grf)
554{
555 /* Configure PCTL timing registers */
556 params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
557 copy_to_reg(&pctl->togcnt1u, &params->pctl_timing.togcnt1u,
558 sizeof(params->pctl_timing));
559 writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
560
561 /* Set up ODT write selector and ODT write length */
562 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
563 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
564
565 /* Set up the CL/CWL-dependent timings of DFI */
566 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
567 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
568
569 /* DDR3 */
570 writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
571 writel(0x001c0004, &grf->ddrc0_con0);
572
573 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
574}
575
576static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
577 struct rk3368_ddrphy *ddrphy)
578{
579 const u32 trefi = readl(&pctl->trefi);
580 const ulong timeout_ms = 500;
581 ulong tmp;
582
583 /* disable auto-refresh */
584 writel(0 | BIT(31), &pctl->trefi);
585
586 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
587 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
588
589 tmp = get_timer(0);
590 do {
591 if (get_timer(tmp) > timeout_ms) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900592 pr_err("%s: did not complete within %ld ms\n",
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200593 __func__, timeout_ms);
594 return -ETIME;
595 }
596 } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
597
598 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
599 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
600 /* resume auto-refresh */
601 writel(trefi | BIT(31), &pctl->trefi);
602
603 return 0;
604}
605
606static int sdram_col_row_detect(struct udevice *dev)
607{
608 struct dram_info *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700609 struct rk3368_sdram_params *params = dev_get_plat(dev);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200610 struct rk3368_ddr_pctl *pctl = priv->pctl;
611 struct rk3368_msch *msch = priv->msch;
612 const u32 test_pattern = 0x5aa5f00f;
613 int row, col;
614 uintptr_t addr;
615
616 move_to_config_state(pctl);
617 writel(6, &msch->ddrconf);
618 move_to_access_state(pctl);
619
620 /* Detect col */
621 for (col = 11; col >= 9; col--) {
Tom Rinibb4dd962022-11-16 13:10:37 -0500622 writel(0, CFG_SYS_SDRAM_BASE);
623 addr = CFG_SYS_SDRAM_BASE +
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200624 (1 << (col + params->chan.bw - 1));
625 writel(test_pattern, addr);
626 if ((readl(addr) == test_pattern) &&
Tom Rinibb4dd962022-11-16 13:10:37 -0500627 (readl(CFG_SYS_SDRAM_BASE) == 0))
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200628 break;
629 }
630
631 if (col == 8) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900632 pr_err("%s: col detect error\n", __func__);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200633 return -EINVAL;
634 }
635
636 move_to_config_state(pctl);
637 writel(15, &msch->ddrconf);
638 move_to_access_state(pctl);
639
640 /* Detect row*/
641 for (row = 16; row >= 12; row--) {
Tom Rinibb4dd962022-11-16 13:10:37 -0500642 writel(0, CFG_SYS_SDRAM_BASE);
643 addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200644 writel(test_pattern, addr);
645 if ((readl(addr) == test_pattern) &&
Tom Rinibb4dd962022-11-16 13:10:37 -0500646 (readl(CFG_SYS_SDRAM_BASE) == 0))
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200647 break;
648 }
649
650 if (row == 11) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900651 pr_err("%s: row detect error\n", __func__);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200652 return -EINVAL;
653 }
654
655 /* Record results */
656 debug("%s: col %d, row %d\n", __func__, col, row);
657 params->chan.col = col;
658 params->chan.cs0_row = row;
659 params->chan.cs1_row = row;
660 params->chan.row_3_4 = 0;
661
662 return 0;
663}
664
665static int msch_niu_config(struct rk3368_msch *msch,
666 struct rk3368_sdram_params *params)
667{
668 int i;
669 const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
670 const u8 rows = params->chan.cs0_row;
671
672 /*
673 * The DDR address-translation table always assumes a 32bit
674 * bus and the comparison below takes care of adjusting for
675 * a 16bit bus (i.e. one column-address is consumed).
676 */
677 const struct {
678 u8 rows;
679 u8 columns;
680 u8 type;
681 } ddrconf_table[] = {
682 /*
683 * C-B-R-D patterns are first. For these we require an
684 * exact match for the columns and rows (as there's
685 * one entry per possible configuration).
686 */
687 [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
688 [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
689 [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
690 [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
691 [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
692 [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
693 [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
694 [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
695 [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
696 [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
697 [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
698 /*
699 * 11 through 13 are C-R-B-D patterns. These are
700 * matched for an exact number of columns and to
701 * ensure that the hardware uses at least as many rows
702 * as the pattern requires (i.e. we make sure that
703 * there's no gaps up until we hit the device/chip-select;
704 * however, these patterns can accept up to 16 rows,
705 * as the row-address continues right after the CS
706 * switching)
707 */
708 [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
709 [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
710 [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
711 /*
712 * 14 and 15 are catch-all variants using a C-B-D-R
713 * scheme (i.e. alternating the chip-select every time
714 * C-B overflows) and stuffing the remaining C-bits
715 * into the top. Matching needs to make sure that the
716 * number of columns is either an exact match (i.e. we
717 * can use less the the maximum number of rows) -or-
718 * that the columns exceed what is given in this table
719 * and the rows are an exact match (in which case the
720 * remaining C-bits will be stuffed onto the top after
721 * the device/chip-select switches).
722 */
723 [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
724 [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
725 };
726
727 /*
728 * For C-B-R-D, we need an exact match (i.e. both for the number of
729 * columns and rows), while for C-B-D-R, only the the number of
730 * columns needs to match.
731 */
732 for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
733 bool match = false;
734
735 /* If this entry if for a different matcher, then skip it */
736 if (ddrconf_table[i].type != params->memory_schedule)
737 continue;
738
739 /*
740 * Match according to the rules (exact/inexact/at-least)
741 * documented in the ddrconf_table above.
742 */
743 switch (params->memory_schedule) {
744 case DMC_MSCH_CBRD:
745 match = (ddrconf_table[i].columns == cols) &&
746 (ddrconf_table[i].rows == rows);
747 break;
748
749 case DMC_MSCH_CRBD:
750 match = (ddrconf_table[i].columns == cols) &&
751 (ddrconf_table[i].rows <= rows);
752 break;
753
754 case DMC_MSCH_CBDR:
755 match = (ddrconf_table[i].columns == cols) ||
756 ((ddrconf_table[i].columns <= cols) &&
757 (ddrconf_table[i].rows == rows));
758 break;
759
760 default:
761 break;
762 }
763
764 if (match) {
765 debug("%s: setting ddrconf 0x%x\n", __func__, i);
766 writel(i, &msch->ddrconf);
767 return 0;
768 }
769 }
770
Masahiro Yamada81e10422017-09-16 14:10:41 +0900771 pr_err("%s: ddrconf (NIU config) not found\n", __func__);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200772 return -EINVAL;
773}
774
775static void dram_all_config(struct udevice *dev)
776{
777 struct dram_info *priv = dev_get_priv(dev);
778 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
Simon Glassfa20e932020-12-03 16:55:20 -0700779 struct rk3368_sdram_params *params = dev_get_plat(dev);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200780 const struct rk3288_sdram_channel *info = &params->chan;
781 u32 sys_reg = 0;
782 const int chan = 0;
783
784 sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
785 sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
786
787 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
788 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
789 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
790 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
791 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
792 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
793 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
794 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
795 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
796
797 writel(sys_reg, &pmugrf->os_reg[2]);
798}
799
800static int setup_sdram(struct udevice *dev)
801{
802 struct dram_info *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700803 struct rk3368_sdram_params *params = dev_get_plat(dev);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200804
805 struct rk3368_ddr_pctl *pctl = priv->pctl;
806 struct rk3368_ddrphy *ddrphy = priv->phy;
807 struct rk3368_cru *cru = priv->cru;
808 struct rk3368_grf *grf = priv->grf;
809 struct rk3368_msch *msch = priv->msch;
810
811 int ret;
812
813 /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
814 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
815 if (ret < 0) {
816 debug("%s: could not set DDR clock: %d\n", __func__, ret);
817 return ret;
818 }
819
820 /* Update the read-latency for the RK3368 */
821 writel(0x32, &msch->readlatency);
822
823 /* Initialise the DDR PCTL and DDR PHY */
824 ddrctl_reset(cru);
825 ddrphy_reset(ddrphy);
826 ddrphy_config_delays(ddrphy, params->ddr_freq);
827 dfi_cfg(pctl);
828 /* Configure relative system information of grf_ddrc0_con0 register */
829 ddr_set_ddr3_mode(grf, true);
830 ddr_set_noc_spr_err_stall(grf, true);
831 /* Calculate timings */
832 pctl_calc_timings(params, params->ddr_freq);
833 /* Initialise the device timings in protocol controller */
834 pctl_cfg(pctl, params, grf);
835 /* Configure AL, CL ... information of PHY registers */
836 ddrphy_config(ddrphy,
837 params->pctl_timing.tcl,
838 params->pctl_timing.tal,
839 params->pctl_timing.tcwl);
840
841 /* Initialize DRAM and configure with mode-register values */
842 ret = memory_init(pctl, params);
843 if (ret)
844 goto error;
845
846 move_to_config_state(pctl);
847 /* Perform data-training */
848 ddrphy_data_training(pctl, ddrphy);
849 move_to_access_state(pctl);
850
851 /* TODO(prt): could detect rank in training... */
Kever Yang24b65002019-03-29 22:48:29 +0800852#ifdef CONFIG_TARGET_EVB_PX5
853 params->chan.rank = 1;
854#else
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200855 params->chan.rank = 2;
Kever Yang24b65002019-03-29 22:48:29 +0800856#endif
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200857 /* TODO(prt): bus width is not auto-detected (yet)... */
858 params->chan.bw = 2; /* 32bit wide bus */
859 params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
860
861 /* DDR3 is always 8 bank */
862 params->chan.bk = 3;
863 /* Detect col and row number */
864 ret = sdram_col_row_detect(dev);
865 if (ret)
866 goto error;
867
868 /* Configure NIU DDR configuration */
869 ret = msch_niu_config(msch, params);
870 if (ret)
871 goto error;
872
873 /* set up OS_REG to communicate w/ next stage and OS */
874 dram_all_config(dev);
875
876 return 0;
877
878error:
879 printf("DRAM init failed!\n");
880 hang();
881}
882#endif
883
Simon Glassaad29ae2020-12-03 16:55:21 -0700884static int rk3368_dmc_of_to_plat(struct udevice *dev)
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200885{
886 int ret = 0;
887
Simon Glass6d70ba02021-08-07 07:24:06 -0600888 if (CONFIG_IS_ENABLED(OF_REAL)) {
889 struct rk3368_sdram_params *plat = dev_get_plat(dev);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200890
Simon Glass6d70ba02021-08-07 07:24:06 -0600891 ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
892 if (ret)
893 return ret;
894 }
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200895
896 return ret;
897}
898
899#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glassb75b15b2020-12-03 16:55:23 -0700900static int conv_of_plat(struct udevice *dev)
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200901{
Simon Glassfa20e932020-12-03 16:55:20 -0700902 struct rk3368_sdram_params *plat = dev_get_plat(dev);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200903 struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200904
905 plat->ddr_freq = of_plat->rockchip_ddr_frequency;
906 plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
907 plat->memory_schedule = of_plat->rockchip_memory_schedule;
908
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200909 return 0;
910}
911#endif
912
913static int rk3368_dmc_probe(struct udevice *dev)
914{
915#ifdef CONFIG_TPL_BUILD
Simon Glassfa20e932020-12-03 16:55:20 -0700916 struct rk3368_sdram_params *plat = dev_get_plat(dev);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200917 struct rk3368_ddr_pctl *pctl;
918 struct rk3368_ddrphy *ddrphy;
919 struct rk3368_cru *cru;
920 struct rk3368_grf *grf;
921 struct rk3368_msch *msch;
922 int ret;
923 struct udevice *dev_clk;
924#endif
925 struct dram_info *priv = dev_get_priv(dev);
926
927#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glassb75b15b2020-12-03 16:55:23 -0700928 ret = conv_of_plat(dev);
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200929 if (ret)
930 return ret;
931#endif
932
933 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
934 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
935
936#ifdef CONFIG_TPL_BUILD
Philipp Tomsich4e2fe8f2017-08-14 19:05:32 +0200937 pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0];
938 ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2];
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200939 msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
940 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
941
942 priv->pctl = pctl;
943 priv->phy = ddrphy;
944 priv->msch = msch;
945 priv->grf = grf;
946
947 ret = rockchip_get_clk(&dev_clk);
948 if (ret)
949 return ret;
950 priv->ddr_clk.id = CLK_DDR;
951 ret = clk_request(dev_clk, &priv->ddr_clk);
952 if (ret)
953 return ret;
954
955 cru = rockchip_get_cru();
956 priv->cru = cru;
957 if (IS_ERR(priv->cru))
958 return PTR_ERR(priv->cru);
959
960 ret = setup_sdram(dev);
961 if (ret)
962 return ret;
963#endif
964
965 priv->info.base = 0;
966 priv->info.size =
967 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
968
969 /*
970 * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
971 * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
972 * inaccessible for some IP controller.
973 */
974 priv->info.size = min(priv->info.size, (size_t)0xfe000000);
975
976 return 0;
977}
978
979static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
980{
981 struct dram_info *priv = dev_get_priv(dev);
982
983 *info = priv->info;
984 return 0;
985}
986
987static struct ram_ops rk3368_dmc_ops = {
988 .get_info = rk3368_dmc_get_info,
989};
990
991
992static const struct udevice_id rk3368_dmc_ids[] = {
993 { .compatible = "rockchip,rk3368-dmc" },
994 { }
995};
996
Walter Lozano2901ac62020-06-25 01:10:04 -0300997U_BOOT_DRIVER(rockchip_rk3368_dmc) = {
Philipp Tomsichd21a4d82017-06-23 00:12:05 +0200998 .name = "rockchip_rk3368_dmc",
999 .id = UCLASS_RAM,
1000 .of_match = rk3368_dmc_ids,
1001 .ops = &rk3368_dmc_ops,
1002 .probe = rk3368_dmc_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001003 .priv_auto = sizeof(struct dram_info),
Simon Glassaad29ae2020-12-03 16:55:21 -07001004 .of_to_plat = rk3368_dmc_of_to_plat,
Philipp Tomsichd21a4d82017-06-23 00:12:05 +02001005 .probe = rk3368_dmc_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001006 .priv_auto = sizeof(struct dram_info),
Simon Glass71fa5b42020-12-03 16:55:18 -07001007 .plat_auto = sizeof(struct rk3368_sdram_params),
Philipp Tomsichd21a4d82017-06-23 00:12:05 +02001008};