blob: 37bb79e25a11c955aa8db9110f7415beae44f3f2 [file] [log] [blame]
Masahiro Yamadac04368f2015-02-27 02:26:51 +09001/*
2 * Copyright (C) 2011-2015 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
Masahiro Yamada4b9c6f22015-02-27 02:26:52 +09008#include <common.h>
9#include <spl.h>
Masahiro Yamadac04368f2015-02-27 02:26:51 +090010#include <asm/io.h>
11#include <mach/sc-regs.h>
12
13void early_clkrst_init(void)
14{
15 u32 tmp;
16
17 /* deassert reset */
18 tmp = readl(SC_RSTCTRL);
Masahiro Yamada4b9c6f22015-02-27 02:26:52 +090019
Masahiro Yamadac04368f2015-02-27 02:26:51 +090020 tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
Masahiro Yamada4b9c6f22015-02-27 02:26:52 +090021 if (spl_boot_device() != BOOT_DEVICE_NAND)
22 tmp &= ~SC_RSTCTRL_NRST_NAND;
Masahiro Yamadac04368f2015-02-27 02:26:51 +090023 writel(tmp, SC_RSTCTRL);
24 readl(SC_RSTCTRL); /* dummy read */
25
26 /* privide clocks */
27 tmp = readl(SC_CLKCTRL);
28 tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
29 writel(tmp, SC_CLKCTRL);
30 readl(SC_CLKCTRL); /* dummy read */
31}