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git01.mediatek.com / filogic / uboot / 5d62dacb663bb8cf17a12c09d752685483b7dbdc / . / arch / arm / mach-stm32mp / stm32mp2 / stm32mp25x.c
blob: 12b43ea5cdf117221857c3819fccb3633854c777 [file] [log] [blame]
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
4 */
5
6#define LOG_CATEGORY LOGC_ARCH
7
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]8#include <log.h>
9#include <syscon.h>
10#include <asm/io.h>
11#include <asm/arch/stm32.h>
12#include <asm/arch/sys_proto.h>
13
14/* SYSCFG register */
15#define SYSCFG_DEVICEID_OFFSET 0x6400
16#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
17#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
Patrick Delaunayf296fd22024-03-19 20:14:27 +0100[diff] [blame]18
19/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
20#define REVID_SHIFT 0
21#define REVID_MASK GENMASK(5, 0)
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]22
23/* Device Part Number (RPN) = OTP9 */
24#define RPN_SHIFT 0
25#define RPN_MASK GENMASK(31, 0)
26
27/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
28 * - 000: Custom package
Patrice Chotarde9acbc32024-07-04 15:54:35 +0200[diff] [blame]29 * - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm
30 * - 011: VFBGA424 => AK = 14x14, 424 balls pith 0.5mm
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]31 * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
32 * - others: Reserved
33 */
34#define PKG_SHIFT 0
35#define PKG_MASK GENMASK(2, 0)
36
37static u32 read_deviceid(void)
38{
39 void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
40
41 return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
42}
43
44u32 get_cpu_dev(void)
45{
46 return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
47}
48
49u32 get_cpu_rev(void)
50{
Patrick Delaunayf296fd22024-03-19 20:14:27 +0100[diff] [blame]51 return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]52}
53
54/* Get Device Part Number (RPN) from OTP */
55u32 get_cpu_type(void)
56{
57 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
58}
59
60/* Get Package options from OTP */
61u32 get_cpu_package(void)
62{
63 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
64}
65
66int get_eth_nb(void)
67{
68 int nb_eth;
69
70 switch (get_cpu_type()) {
71 case CPU_STM32MP257Fxx:
72 fallthrough;
73 case CPU_STM32MP257Dxx:
74 fallthrough;
75 case CPU_STM32MP257Cxx:
76 fallthrough;
77 case CPU_STM32MP257Axx:
78 nb_eth = 5; /* dual ETH with TSN support */
79 break;
80 case CPU_STM32MP253Fxx:
81 fallthrough;
82 case CPU_STM32MP253Dxx:
83 fallthrough;
84 case CPU_STM32MP253Cxx:
85 fallthrough;
86 case CPU_STM32MP253Axx:
87 nb_eth = 2; /* dual ETH */
88 break;
89 case CPU_STM32MP251Fxx:
90 fallthrough;
91 case CPU_STM32MP251Dxx:
92 fallthrough;
93 case CPU_STM32MP251Cxx:
94 fallthrough;
95 case CPU_STM32MP251Axx:
96 nb_eth = 1; /* single ETH */
97 break;
98 default:
99 nb_eth = 0;
100 break;
101 }
102
103 return nb_eth;
104}
105
106void get_soc_name(char name[SOC_NAME_SIZE])
107{
108 char *cpu_s, *cpu_r, *package;
109
110 cpu_s = "????";
111 cpu_r = "?";
112 package = "??";
113 if (get_cpu_dev() == CPU_DEV_STM32MP25) {
114 switch (get_cpu_type()) {
115 case CPU_STM32MP257Fxx:
116 cpu_s = "257F";
117 break;
118 case CPU_STM32MP257Dxx:
119 cpu_s = "257D";
120 break;
121 case CPU_STM32MP257Cxx:
122 cpu_s = "257C";
123 break;
124 case CPU_STM32MP257Axx:
125 cpu_s = "257A";
126 break;
127 case CPU_STM32MP255Fxx:
128 cpu_s = "255F";
129 break;
130 case CPU_STM32MP255Dxx:
131 cpu_s = "255D";
132 break;
133 case CPU_STM32MP255Cxx:
134 cpu_s = "255C";
135 break;
136 case CPU_STM32MP255Axx:
137 cpu_s = "255A";
138 break;
139 case CPU_STM32MP253Fxx:
140 cpu_s = "253F";
141 break;
142 case CPU_STM32MP253Dxx:
143 cpu_s = "253D";
144 break;
145 case CPU_STM32MP253Cxx:
146 cpu_s = "253C";
147 break;
148 case CPU_STM32MP253Axx:
149 cpu_s = "253A";
150 break;
151 case CPU_STM32MP251Fxx:
152 cpu_s = "251F";
153 break;
154 case CPU_STM32MP251Dxx:
155 cpu_s = "251D";
156 break;
157 case CPU_STM32MP251Cxx:
158 cpu_s = "251C";
159 break;
160 case CPU_STM32MP251Axx:
161 cpu_s = "251A";
162 break;
163 default:
164 cpu_s = "25??";
165 break;
166 }
167 /* REVISION */
168 switch (get_cpu_rev()) {
Patrick Delaunayf296fd22024-03-19 20:14:27 +0100[diff] [blame]169 case OTP_REVID_1:
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]170 cpu_r = "A";
171 break;
Patrick Delaunayf296fd22024-03-19 20:14:27 +0100[diff] [blame]172 case OTP_REVID_1_1:
173 cpu_r = "Z";
174 break;
175 case OTP_REVID_2:
Yann Gautierbb5502a2024-01-15 15:05:45 +0100[diff] [blame]176 cpu_r = "B";
177 break;
Patrick Delaunayf296fd22024-03-19 20:14:27 +0100[diff] [blame]178 case OTP_REVID_2_1:
179 cpu_r = "Y";
180 break;
181 case OTP_REVID_2_2:
182 cpu_r = "X";
183 break;
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]184 default:
185 break;
186 }
187 /* PACKAGE */
188 switch (get_cpu_package()) {
189 case STM32MP25_PKG_CUSTOM:
190 package = "XX";
191 break;
Patrice Chotarde9acbc32024-07-04 15:54:35 +0200[diff] [blame]192 case STM32MP25_PKG_AL_VFBGA361:
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]193 package = "AL";
194 break;
Patrice Chotarde9acbc32024-07-04 15:54:35 +0200[diff] [blame]195 case STM32MP25_PKG_AK_VFBGA424:
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]196 package = "AK";
197 break;
Patrice Chotarde9acbc32024-07-04 15:54:35 +0200[diff] [blame]198 case STM32MP25_PKG_AI_TFBGA436:
Patrice Chotardd29531c2023-10-27 16:43:04 +0200[diff] [blame]199 package = "AI";
200 break;
201 default:
202 break;
203 }
204 }
205
206 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
207}