blob: f7a254359c9be7180e86ee9af5513d5c63d442aa [file] [log] [blame]
Ilko Iliev2b4ed302021-04-23 09:45:52 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __IMX8M_CM_H
7#define __IMX8M_CM_H
8
9#include <linux/sizes.h>
10#include <linux/stringify.h>
11#include <asm/arch/imx-regs.h>
12
13#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
14
Ilko Iliev2b4ed302021-04-23 09:45:52 +020015#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Ilko Iliev2b4ed302021-04-23 09:45:52 +020016
17#ifdef CONFIG_SPL_BUILD
Ilko Iliev2b4ed302021-04-23 09:45:52 +020018#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
19
20/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
21#define CONFIG_MALLOC_F_ADDR 0x182000
22/* For RAW image gives a error info not panic */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020023
24#endif
25
Ilko Iliev2b4ed302021-04-23 09:45:52 +020026/* ENET Config */
27/* ENET1 */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020028
Ilko Iliev2b4ed302021-04-23 09:45:52 +020029#define BOOT_TARGET_DEVICES(func) \
30 func(MMC, mmc, 0) \
31 func(MMC, mmc, 1) \
32 func(DHCP, dhcp, na)
33
34#include <config_distro_bootcmd.h>
Ilko Iliev2b4ed302021-04-23 09:45:52 +020035
36/* Initial environment variables */
37#define CONFIG_EXTRA_ENV_SETTINGS \
38 BOOTENV \
39 "scriptaddr=0x43500000\0" \
40 "kernel_addr_r=0x40880000\0" \
41 "image=Image\0" \
42 "console=ttymxc0,115200\0" \
43 "fdt_addr=0x43000000\0" \
44 "boot_fdt=try\0" \
45 "fdt_file=imx8mq-cm.dtb\0" \
46 "initrd_addr=0x43800000\0" \
47 "bootm_size=0x10000000\0" \
Tom Rinib113bca2021-12-11 14:55:52 -050048 "mmcpart=1\0" \
Peng Fanbb4bb582022-04-15 12:23:41 +080049 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
Ilko Iliev2b4ed302021-04-23 09:45:52 +020050
51/* Link Definitions */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020052
53#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
54#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
Ilko Iliev2b4ed302021-04-23 09:45:52 +020055
Ilko Iliev2b4ed302021-04-23 09:45:52 +020056
Ilko Iliev2b4ed302021-04-23 09:45:52 +020057#define CONFIG_SYS_SDRAM_BASE 0x40000000
58#define PHYS_SDRAM 0x40000000
59#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
60
Marek Vasut86a27482022-04-24 23:44:03 +020061#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
Ilko Iliev2b4ed302021-04-23 09:45:52 +020062
Ilko Iliev2b4ed302021-04-23 09:45:52 +020063#define CONFIG_SYS_FSL_USDHC_NUM 2
64#define CONFIG_SYS_FSL_ESDHC_ADDR 0
65
Ilko Iliev2b4ed302021-04-23 09:45:52 +020066#endif