blob: 6eecfc813a4337433410731e9b3a73e536e20c6f [file] [log] [blame]
Ilko Iliev2b4ed302021-04-23 09:45:52 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __IMX8M_CM_H
7#define __IMX8M_CM_H
8
9#include <linux/sizes.h>
10#include <linux/stringify.h>
11#include <asm/arch/imx-regs.h>
12
13#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
14
15#define CONFIG_SPL_MAX_SIZE (124 * 1024)
16#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Ilko Iliev2b4ed302021-04-23 09:45:52 +020017
18#ifdef CONFIG_SPL_BUILD
19#define CONFIG_SPL_STACK 0x187FF0
20#define CONFIG_SPL_BSS_START_ADDR 0x00180000
21#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
22#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
23#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
24#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
25
26/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
27#define CONFIG_MALLOC_F_ADDR 0x182000
28/* For RAW image gives a error info not panic */
29#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
30
31#endif
32
Ilko Iliev2b4ed302021-04-23 09:45:52 +020033/* ENET Config */
34/* ENET1 */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020035
36#ifndef CONFIG_SPL_BUILD
37#define BOOT_TARGET_DEVICES(func) \
38 func(MMC, mmc, 0) \
39 func(MMC, mmc, 1) \
40 func(DHCP, dhcp, na)
41
42#include <config_distro_bootcmd.h>
43#endif
44
45/* Initial environment variables */
46#define CONFIG_EXTRA_ENV_SETTINGS \
47 BOOTENV \
48 "scriptaddr=0x43500000\0" \
49 "kernel_addr_r=0x40880000\0" \
50 "image=Image\0" \
51 "console=ttymxc0,115200\0" \
52 "fdt_addr=0x43000000\0" \
53 "boot_fdt=try\0" \
54 "fdt_file=imx8mq-cm.dtb\0" \
55 "initrd_addr=0x43800000\0" \
56 "bootm_size=0x10000000\0" \
Tom Rinib113bca2021-12-11 14:55:52 -050057 "mmcpart=1\0" \
Peng Fanbb4bb582022-04-15 12:23:41 +080058 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
Ilko Iliev2b4ed302021-04-23 09:45:52 +020059
60/* Link Definitions */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020061
62#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
63#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
64#define CONFIG_SYS_INIT_SP_OFFSET \
65 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
66#define CONFIG_SYS_INIT_SP_ADDR \
67 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
68
Ilko Iliev2b4ed302021-04-23 09:45:52 +020069
Ilko Iliev2b4ed302021-04-23 09:45:52 +020070#define CONFIG_SYS_SDRAM_BASE 0x40000000
71#define PHYS_SDRAM 0x40000000
72#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
73
Marek Vasut86a27482022-04-24 23:44:03 +020074#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
Ilko Iliev2b4ed302021-04-23 09:45:52 +020075
76/* Monitor Command Prompt */
77#define CONFIG_SYS_CBSIZE 1024
78#define CONFIG_SYS_MAXARGS 64
79#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
80#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
81 sizeof(CONFIG_SYS_PROMPT) + 16)
82
Ilko Iliev2b4ed302021-04-23 09:45:52 +020083#define CONFIG_SYS_FSL_USDHC_NUM 2
84#define CONFIG_SYS_FSL_ESDHC_ADDR 0
85
Ilko Iliev2b4ed302021-04-23 09:45:52 +020086#endif