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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Galae1c09492010-07-15 16:49:03 -05002/*
ramneek mehresh3d339632012-04-18 19:39:53 +00003 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Kumar Galae1c09492010-07-15 16:49:03 -05004 */
5
6/*
7 * Corenet DS style board configuration file
8 */
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include "../board/freescale/common/ics307_clk.h"
13
Shaohui Xie25a2b392011-03-16 10:10:32 +080014#ifdef CONFIG_RAMBOOT_PBL
Udit Agarwald2dd2f72019-11-07 16:11:39 +000015#ifdef CONFIG_NXP_ESBC
Shaohui Xie25a2b392011-03-16 10:10:32 +080016#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
17#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Miquel Raynald0935362019-10-03 19:50:03 +020018#ifdef CONFIG_MTD_RAW_NAND
Aneesh Bansale0f50152015-06-16 10:36:00 +053019#define CONFIG_RAMBOOT_NAND
20#endif
Aneesh Bansalb69061d2015-06-16 10:36:43 +053021#define CONFIG_BOOTSCRIPT_COPY_RAM
Aneesh Bansale0f50152015-06-16 10:36:00 +053022#else
23#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090025#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
York Sun80d89912016-11-18 11:22:17 -080026#if defined(CONFIG_TARGET_P3041DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090027#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
York Sund1bb6022016-11-18 11:26:09 -080028#elif defined(CONFIG_TARGET_P4080DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090029#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
York Sun14bd0742016-11-18 11:32:46 -080030#elif defined(CONFIG_TARGET_P5020DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090031#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
York Suncc85e252016-11-18 11:40:51 -080032#elif defined(CONFIG_TARGET_P5040DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090033#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
Shaohui Xieea65fd82012-08-10 02:49:35 +000034#endif
Shaohui Xie25a2b392011-03-16 10:10:32 +080035#endif
Aneesh Bansale0f50152015-06-16 10:36:00 +053036#endif
Shaohui Xie25a2b392011-03-16 10:10:32 +080037
Liu Gangb4611ee2012-08-09 05:10:03 +000038#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
Liu Gang1e084582012-03-08 00:33:18 +000039/* Set 1M boot space */
Liu Gangb4611ee2012-08-09 05:10:03 +000040#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
41#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +000043#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Liu Gang1e084582012-03-08 00:33:18 +000044#endif
45
Kumar Galae1c09492010-07-15 16:49:03 -050046/* High Level Configuration Options */
Kumar Galae1c09492010-07-15 16:49:03 -050047#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Kumar Galae1c09492010-07-15 16:49:03 -050048
Kumar Galae727a362011-01-12 02:48:53 -060049#ifndef CONFIG_RESET_VECTOR_ADDRESS
50#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
51#endif
52
Kumar Galae1c09492010-07-15 16:49:03 -050053#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sunfe845072016-12-28 08:43:45 -080054#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Robert P. J. Daya8099812016-05-03 19:52:49 -040055#define CONFIG_PCIE1 /* PCIE controller 1 */
56#define CONFIG_PCIE2 /* PCIE controller 2 */
Kumar Galae1c09492010-07-15 16:49:03 -050057#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
Kumar Galae1c09492010-07-15 16:49:03 -050058
Kumar Galae1c09492010-07-15 16:49:03 -050059#define CONFIG_ENV_OVERWRITE
60
Shaohui Xiec6083892011-05-12 18:46:40 +080061#if defined(CONFIG_SPIFLASH)
Shaohui Xiec6083892011-05-12 18:46:40 +080062#elif defined(CONFIG_SDCARD)
Fabio Estevamae8c45e2012-01-11 09:20:50 +000063#define CONFIG_FSL_FIXED_MMC_LOCATION
Shaohui Xiec6083892011-05-12 18:46:40 +080064#define CONFIG_SYS_MMC_ENV_DEV 0
Kumar Galae1c09492010-07-15 16:49:03 -050065#endif
66
67#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
Kumar Galae1c09492010-07-15 16:49:03 -050068
69/*
70 * These can be toggled for performance analysis, otherwise use default.
71 */
72#define CONFIG_SYS_CACHE_STASHING
73#define CONFIG_BACKSIDE_L2_CACHE
74#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
75#define CONFIG_BTB /* toggle branch predition */
York Sun147fde12011-01-10 12:02:58 +000076#define CONFIG_DDR_ECC
Kumar Galae1c09492010-07-15 16:49:03 -050077#ifdef CONFIG_DDR_ECC
78#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
79#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
80#endif
81
82#define CONFIG_ENABLE_36BIT_PHYS
83
84#ifdef CONFIG_PHYS_64BIT
85#define CONFIG_ADDR_MAP
86#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
87#endif
88
York Sun18acc8b2010-09-28 15:20:36 -070089#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
Kumar Galae1c09492010-07-15 16:49:03 -050090#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
91#define CONFIG_SYS_MEMTEST_END 0x00400000
Kumar Galae1c09492010-07-15 16:49:03 -050092
93/*
Shaohui Xie25a2b392011-03-16 10:10:32 +080094 * Config the L3 Cache as L3 SRAM
95 */
96#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
97#ifdef CONFIG_PHYS_64BIT
98#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
99#else
100#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
101#endif
102#define CONFIG_SYS_L3_SIZE (1024 << 10)
103#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
104
Kumar Galae1c09492010-07-15 16:49:03 -0500105#ifdef CONFIG_PHYS_64BIT
106#define CONFIG_SYS_DCSRBAR 0xf0000000
107#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
108#endif
109
110/* EEPROM */
111#define CONFIG_ID_EEPROM
112#define CONFIG_SYS_I2C_EEPROM_NXID
113#define CONFIG_SYS_EEPROM_BUS_NUM 0
114#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
115#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
116
117/*
118 * DDR Setup
119 */
120#define CONFIG_VERY_BIG_RAM
121#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
122#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
123
124#define CONFIG_DIMM_SLOTS_PER_CTLR 1
york0b2bb6d2010-07-02 22:25:59 +0000125#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Kumar Galae1c09492010-07-15 16:49:03 -0500126
127#define CONFIG_DDR_SPD
Kumar Galae1c09492010-07-15 16:49:03 -0500128
Kumar Galae1c09492010-07-15 16:49:03 -0500129#define CONFIG_SYS_SPD_BUS_NUM 1
130#define SPD_EEPROM_ADDRESS1 0x51
131#define SPD_EEPROM_ADDRESS2 0x52
Kumar Galae38209e2011-02-09 02:00:08 +0000132#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
York Sun269c7eb2010-10-18 13:46:49 -0700133#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Kumar Galae1c09492010-07-15 16:49:03 -0500134
135/*
136 * Local Bus Definitions
137 */
138
139/* Set the local bus clock 1/8 of platform clock */
140#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
141
142#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
143#ifdef CONFIG_PHYS_64BIT
144#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
145#else
146#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
147#endif
148
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800149#define CONFIG_SYS_FLASH_BR_PRELIM \
Timur Tabib56570c2012-07-06 07:39:26 +0000150 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800151 | BR_PS_16 | BR_V)
152#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
Kumar Galae1c09492010-07-15 16:49:03 -0500153 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
154
155#define CONFIG_SYS_BR1_PRELIM \
156 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
157#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
158
Kumar Galae1c09492010-07-15 16:49:03 -0500159#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
160#ifdef CONFIG_PHYS_64BIT
161#define PIXIS_BASE_PHYS 0xfffdf0000ull
162#else
163#define PIXIS_BASE_PHYS PIXIS_BASE
164#endif
165
166#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
167#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
168
169#define PIXIS_LBMAP_SWITCH 7
170#define PIXIS_LBMAP_MASK 0xf0
171#define PIXIS_LBMAP_SHIFT 4
172#define PIXIS_LBMAP_ALTBANK 0x40
173
174#define CONFIG_SYS_FLASH_QUIET_TEST
175#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
176
177#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
178#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
181
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200182#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kumar Galae1c09492010-07-15 16:49:03 -0500183
Shaohui Xie25a2b392011-03-16 10:10:32 +0800184#if defined(CONFIG_RAMBOOT_PBL)
185#define CONFIG_SYS_RAMBOOT
186#endif
187
Kumar Galae38209e2011-02-09 02:00:08 +0000188/* Nand Flash */
Kumar Galae38209e2011-02-09 02:00:08 +0000189#ifdef CONFIG_NAND_FSL_ELBC
190#define CONFIG_SYS_NAND_BASE 0xffa00000
191#ifdef CONFIG_PHYS_64BIT
192#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
193#else
194#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
195#endif
196
197#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
198#define CONFIG_SYS_MAX_NAND_DEVICE 1
Kumar Galae38209e2011-02-09 02:00:08 +0000199#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
200
201/* NAND flash config */
202#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
203 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
204 | BR_PS_8 /* Port Size = 8 bit */ \
205 | BR_MS_FCM /* MSEL = FCM */ \
206 | BR_V) /* valid */
207#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
208 | OR_FCM_PGS /* Large Page*/ \
209 | OR_FCM_CSCT \
210 | OR_FCM_CST \
211 | OR_FCM_CHT \
212 | OR_FCM_SCY_1 \
213 | OR_FCM_TRLX \
214 | OR_FCM_EHTR)
215
Miquel Raynald0935362019-10-03 19:50:03 +0200216#ifdef CONFIG_MTD_RAW_NAND
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800217#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
218#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
219#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
220#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
221#else
222#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
223#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
224#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
225#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
226#endif
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800227#else
228#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
229#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
Kumar Galad0af3b92011-08-31 09:50:13 -0500230#endif /* CONFIG_NAND_FSL_ELBC */
Kumar Galae38209e2011-02-09 02:00:08 +0000231
Kumar Galae1c09492010-07-15 16:49:03 -0500232#define CONFIG_SYS_FLASH_EMPTY_INFO
233#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
234#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
235
Kumar Galae1c09492010-07-15 16:49:03 -0500236#define CONFIG_HWCONFIG
237
238/* define to use L1 as initial stack */
239#define CONFIG_L1_INIT_RAM
240#define CONFIG_SYS_INIT_RAM_LOCK
241#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
242#ifdef CONFIG_PHYS_64BIT
243#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
244#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
245/* The assembler doesn't like typecast */
246#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
247 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
248 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
249#else
250#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
251#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
252#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
253#endif
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200254#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Galae1c09492010-07-15 16:49:03 -0500255
Wolfgang Denk0191e472010-10-26 14:34:52 +0200256#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kumar Galae1c09492010-07-15 16:49:03 -0500257#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
258
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530259#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Kumar Galae1c09492010-07-15 16:49:03 -0500260#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
261
262/* Serial Port - controlled on board with jumper J8
263 * open - index 2
264 * shorted - index 1
265 */
Kumar Galae1c09492010-07-15 16:49:03 -0500266#define CONFIG_SYS_NS16550_SERIAL
267#define CONFIG_SYS_NS16550_REG_SIZE 1
268#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
269
270#define CONFIG_SYS_BAUDRATE_TABLE \
271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
272
273#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
274#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
275#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
276#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
277
Kumar Galae1c09492010-07-15 16:49:03 -0500278/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200279#define CONFIG_SYS_I2C
280#define CONFIG_SYS_I2C_FSL
281#define CONFIG_SYS_FSL_I2C_SPEED 400000
282#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
283#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
284#define CONFIG_SYS_FSL_I2C2_SPEED 400000
285#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
286#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
Kumar Galae1c09492010-07-15 16:49:03 -0500287
288/*
289 * RapidIO
290 */
Kumar Gala8975d7a2010-12-30 12:09:53 -0600291#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500292#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600293#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500294#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600295#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500296#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600297#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500298
Kumar Gala8975d7a2010-12-30 12:09:53 -0600299#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500300#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600301#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500302#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600303#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500304#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600305#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500306
307/*
Liu Gang4cc85322012-03-08 00:33:17 +0000308 * for slave u-boot IMAGE instored in master memory space,
309 * PHYS must be aligned based on the SIZE
310 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800311#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
312#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
313#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
314#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Liu Gang85bcd732012-03-08 00:33:20 +0000315/*
Liu Gangd7b17a92012-08-09 05:09:59 +0000316 * for slave UCODE and ENV instored in master memory space,
Liu Gang85bcd732012-03-08 00:33:20 +0000317 * PHYS must be aligned based on the SIZE
318 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800319#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Liu Gang99e0c292012-08-09 05:10:02 +0000320#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
321#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
Liu Gangd7b17a92012-08-09 05:09:59 +0000322
Liu Gangf420aa92012-03-08 00:33:21 +0000323/* slave core release by master*/
Liu Gang99e0c292012-08-09 05:10:02 +0000324#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
325#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
Liu Gang4cc85322012-03-08 00:33:17 +0000326
327/*
Liu Gangb4611ee2012-08-09 05:10:03 +0000328 * SRIO_PCIE_BOOT - SLAVE
Liu Gang1e084582012-03-08 00:33:18 +0000329 */
Liu Gangb4611ee2012-08-09 05:10:03 +0000330#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
331#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
332#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
333 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +0000334#endif
335
336/*
Shaohui Xie58649792011-05-12 18:46:14 +0800337 * eSPI - Enhanced SPI
338 */
Shaohui Xie58649792011-05-12 18:46:14 +0800339
340/*
Kumar Galae1c09492010-07-15 16:49:03 -0500341 * General PCI
342 * Memory space is mapped 1-1, but I/O space must start from 0.
343 */
344
345/* controller 1, direct to uli, tgtid 3, Base address 20000 */
346#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Kumar Galae1c09492010-07-15 16:49:03 -0500347#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500348#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
Kumar Galae1c09492010-07-15 16:49:03 -0500349#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500350
351/* controller 2, Slot 2, tgtid 2, Base address 201000 */
352#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500353#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500354#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
Kumar Galae1c09492010-07-15 16:49:03 -0500355#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500356
357/* controller 3, Slot 1, tgtid 1, Base address 202000 */
Trübenbach, Ralfd8ec2c02011-04-20 13:04:47 +0000358#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500359#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500360#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
Kumar Galae1c09492010-07-15 16:49:03 -0500361#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500362
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500363/* controller 4, Base address 203000 */
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500364#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500365#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500366
Kumar Galae1c09492010-07-15 16:49:03 -0500367/* Qman/Bman */
368#define CONFIG_SYS_BMAN_NUM_PORTALS 10
369#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
370#ifdef CONFIG_PHYS_64BIT
371#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
372#else
373#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
374#endif
375#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500376#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
377#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
378#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
379#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
380#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
381 CONFIG_SYS_BMAN_CENA_SIZE)
382#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
383#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500384#define CONFIG_SYS_QMAN_NUM_PORTALS 10
385#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
386#ifdef CONFIG_PHYS_64BIT
387#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
388#else
389#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
390#endif
391#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500392#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
393#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
394#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
395#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
396#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
397 CONFIG_SYS_QMAN_CENA_SIZE)
398#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
399#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500400
401#define CONFIG_SYS_DPAA_FMAN
402#define CONFIG_SYS_DPAA_PME
403/* Default address of microcode for the Linux Fman driver */
Timur Tabibb763662011-05-03 13:35:11 -0500404#if defined(CONFIG_SPIFLASH)
405/*
406 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
407 * env, so we got 0x110000.
408 */
Zhao Qiang83a90842014-03-21 16:21:44 +0800409#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Timur Tabibb763662011-05-03 13:35:11 -0500410#elif defined(CONFIG_SDCARD)
411/*
412 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530413 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
414 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Timur Tabibb763662011-05-03 13:35:11 -0500415 */
Zhao Qiang83a90842014-03-21 16:21:44 +0800416#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Miquel Raynald0935362019-10-03 19:50:03 +0200417#elif defined(CONFIG_MTD_RAW_NAND)
Zhao Qiang83a90842014-03-21 16:21:44 +0800418#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gangb4611ee2012-08-09 05:10:03 +0000419#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gang1e084582012-03-08 00:33:18 +0000420/*
421 * Slave has no ucode locally, it can fetch this from remote. When implementing
422 * in two corenet boards, slave's ucode could be stored in master's memory
423 * space, the address can be mapped from slave TLB->slave LAW->
Liu Gangb4611ee2012-08-09 05:10:03 +0000424 * slave SRIO or PCIE outbound window->master inbound window->
425 * master LAW->the ucode address in master's memory space.
Liu Gang1e084582012-03-08 00:33:18 +0000426 */
Zhao Qiang83a90842014-03-21 16:21:44 +0800427#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Kumar Galae1c09492010-07-15 16:49:03 -0500428#else
Zhao Qiang83a90842014-03-21 16:21:44 +0800429#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Kumar Galae1c09492010-07-15 16:49:03 -0500430#endif
Timur Tabi275f4bb2011-11-22 09:21:25 -0600431#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
432#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Kumar Galae1c09492010-07-15 16:49:03 -0500433
Kumar Galae1c09492010-07-15 16:49:03 -0500434#ifdef CONFIG_PCI
Hou Zhiqiang8bad9c82019-08-27 11:04:45 +0000435#if !defined(CONFIG_DM_PCI)
436#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhosb4458732013-05-30 07:06:12 +0000437#define CONFIG_PCI_INDIRECT_BRIDGE
Hou Zhiqiang8bad9c82019-08-27 11:04:45 +0000438#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
439#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
440#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
441#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
442#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
443#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
444#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
445#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
446#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
447#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
448#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
449#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
450#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
451#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
452#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
453#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
454#endif
Kumar Galae1c09492010-07-15 16:49:03 -0500455
Kumar Galae1c09492010-07-15 16:49:03 -0500456#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Galae1c09492010-07-15 16:49:03 -0500457#endif /* CONFIG_PCI */
458
459/* SATA */
460#ifdef CONFIG_FSL_SATA_V2
Kumar Galae1c09492010-07-15 16:49:03 -0500461#define CONFIG_SYS_SATA_MAX_DEVICE 2
462#define CONFIG_SATA1
463#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
464#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
465#define CONFIG_SATA2
466#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
467#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
468
469#define CONFIG_LBA48
Kumar Galae1c09492010-07-15 16:49:03 -0500470#endif
471
472#ifdef CONFIG_FMAN_ENET
473#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
474#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
475#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
476#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
477#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
478
Kumar Galae1c09492010-07-15 16:49:03 -0500479#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
480#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
481#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
482#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
483#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
Kumar Galae1c09492010-07-15 16:49:03 -0500484
485#define CONFIG_SYS_TBIPA_VALUE 8
Kumar Galae1c09492010-07-15 16:49:03 -0500486#define CONFIG_ETHPRIME "FM1@DTSEC1"
Kumar Galae1c09492010-07-15 16:49:03 -0500487#endif
488
489/*
490 * Environment
491 */
Kumar Galae1c09492010-07-15 16:49:03 -0500492#define CONFIG_LOADS_ECHO /* echo on for serial download */
493#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
494
495/*
Kumar Galae1c09492010-07-15 16:49:03 -0500496* USB
497*/
ramneek mehresh3d339632012-04-18 19:39:53 +0000498#define CONFIG_HAS_FSL_DR_USB
499#define CONFIG_HAS_FSL_MPH_USB
500
501#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Kumar Galae1c09492010-07-15 16:49:03 -0500502#define CONFIG_USB_EHCI_FSL
503#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
ramneek mehresh3d339632012-04-18 19:39:53 +0000504#endif
Kumar Galae1c09492010-07-15 16:49:03 -0500505
Kumar Galae1c09492010-07-15 16:49:03 -0500506#ifdef CONFIG_MMC
Kumar Galae1c09492010-07-15 16:49:03 -0500507#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
508#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Kumar Galae1c09492010-07-15 16:49:03 -0500509#endif
510
511/*
512 * Miscellaneous configurable options
513 */
Kumar Galae1c09492010-07-15 16:49:03 -0500514#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Galae1c09492010-07-15 16:49:03 -0500515
516/*
517 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500518 * have to be in the first 64 MB of memory, since this is
Kumar Galae1c09492010-07-15 16:49:03 -0500519 * the maximum mapped by the Linux kernel during initialization.
520 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500521#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
522#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Galae1c09492010-07-15 16:49:03 -0500523
Kumar Galae1c09492010-07-15 16:49:03 -0500524#ifdef CONFIG_CMD_KGDB
525#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Galae1c09492010-07-15 16:49:03 -0500526#endif
527
528/*
529 * Environment Configuration
530 */
Joe Hershberger257ff782011-10-13 13:03:47 +0000531#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000532#define CONFIG_BOOTFILE "uImage"
Kumar Galae1c09492010-07-15 16:49:03 -0500533#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
534
535/* default location for tftp and bootm */
536#define CONFIG_LOADADDR 1000000
537
York Sund1bb6022016-11-18 11:26:09 -0800538#ifdef CONFIG_TARGET_P4080DS
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000539#define __USB_PHY_TYPE ulpi
540#else
541#define __USB_PHY_TYPE utmi
542#endif
543
Kumar Galae1c09492010-07-15 16:49:03 -0500544#define CONFIG_EXTRA_ENV_SETTINGS \
Emil Medveb250d372010-08-31 22:57:43 -0500545 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000546 "bank_intlv=cs0_cs1;" \
ramneek mehresh1b57b002013-09-10 17:37:45 +0530547 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
548 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
Kumar Galae1c09492010-07-15 16:49:03 -0500549 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200550 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
551 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Emil Medveb250d372010-08-31 22:57:43 -0500552 "tftpflash=tftpboot $loadaddr $uboot && " \
553 "protect off $ubootaddr +$filesize && " \
554 "erase $ubootaddr +$filesize && " \
555 "cp.b $loadaddr $ubootaddr $filesize && " \
556 "protect on $ubootaddr +$filesize && " \
557 "cmp.b $loadaddr $ubootaddr $filesize\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500558 "consoledev=ttyS0\0" \
559 "ramdiskaddr=2000000\0" \
560 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500561 "fdtaddr=1e00000\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500562 "fdtfile=p4080ds/p4080ds.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500563 "bdev=sda3\0"
Kumar Galae1c09492010-07-15 16:49:03 -0500564
565#define CONFIG_HDBOOT \
566 "setenv bootargs root=/dev/$bdev rw " \
567 "console=$consoledev,$baudrate $othbootargs;" \
568 "tftp $loadaddr $bootfile;" \
569 "tftp $fdtaddr $fdtfile;" \
570 "bootm $loadaddr - $fdtaddr"
571
572#define CONFIG_NFSBOOTCOMMAND \
573 "setenv bootargs root=/dev/nfs rw " \
574 "nfsroot=$serverip:$rootpath " \
575 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
576 "console=$consoledev,$baudrate $othbootargs;" \
577 "tftp $loadaddr $bootfile;" \
578 "tftp $fdtaddr $fdtfile;" \
579 "bootm $loadaddr - $fdtaddr"
580
581#define CONFIG_RAMBOOTCOMMAND \
582 "setenv bootargs root=/dev/ram rw " \
583 "console=$consoledev,$baudrate $othbootargs;" \
584 "tftp $ramdiskaddr $ramdiskfile;" \
585 "tftp $loadaddr $bootfile;" \
586 "tftp $fdtaddr $fdtfile;" \
587 "bootm $loadaddr $ramdiskaddr $fdtaddr"
588
589#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
590
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000591#include <asm/fsl_secure_boot.h>
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000592
Kumar Galae1c09492010-07-15 16:49:03 -0500593#endif /* __CONFIG_H */