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git01.mediatek.com / filogic / uboot / 5ba115901775f2cdde9a4301f1ca55ae257ae4a1 / . / arch / arm / dts / k3-am642-sk-u-boot.dtsi
blob: 69dbe943bdf3452a2b957b453fdd0237c979723b [file] [log] [blame]
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/ {
7 chosen {
8 stdout-path = "serial2:115200n8";
9 tick-timer = &timer1;
10 };
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]11
12 aliases {
13 mmc1 = &sdhci1;
14 };
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]15
16 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]18 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]19};
20
21&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]23 timer1: timer@2400000 {
24 compatible = "ti,omap5430-timer";
25 reg = <0x0 0x2400000 0x0 0x80>;
26 ti,timer-alwon;
Vignesh Raghavendraf113fce2022-03-11 21:23:22 +0530[diff] [blame]27 clock-frequency = <200000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]29 };
30};
31
32&main_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]34 chipid@14 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]36 };
37};
38
39&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]41 main_i2c0_pins_default: main-i2c0-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]43 pinctrl-single,pins = <
44 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
45 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
46 >;
47 };
48};
49
50&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]52 pinctrl-names = "default";
53 pinctrl-0 = <&main_i2c0_pins_default>;
54 clock-frequency = <400000>;
Neil Armstronga47a3f82022-04-27 13:28:12 +0200[diff] [blame]55
56 tps65219: pmic@30 {
57 compatible = "ti,tps65219";
58 reg = <0x30>;
59
60 regulators {
61 buck1_reg: buck1 {
62 regulator-name = "VDD_CORE";
63 regulator-min-microvolt = <750000>;
64 regulator-max-microvolt = <750000>;
65 regulator-boot-on;
66 regulator-always-on;
67 };
68
69 buck2_reg: buck2 {
70 regulator-name = "VCC1V8";
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
73 regulator-boot-on;
74 regulator-always-on;
75 };
76
77 buck3_reg: buck3 {
78 regulator-name = "VDD_LPDDR4";
79 regulator-min-microvolt = <1100000>;
80 regulator-max-microvolt = <1100000>;
81 regulator-boot-on;
82 regulator-always-on;
83 };
84
85 ldo1_reg: ldo1 {
86 regulator-name = "VDDSHV_SD_IO_PMIC";
87 regulator-min-microvolt = <33000000>;
88 regulator-max-microvolt = <33000000>;
89 };
90
91 ldo2_reg: ldo2 {
92 regulator-name = "VDDAR_CORE";
93 regulator-min-microvolt = <850000>;
94 regulator-max-microvolt = <850000>;
95 regulator-boot-on;
96 regulator-always-on;
97 };
98
99 ldo3_reg: ldo3 {
100 regulator-name = "VDDA_1V8";
101 regulator-min-microvolt = <18000000>;
102 regulator-max-microvolt = <18000000>;
103 regulator-boot-on;
104 regulator-always-on;
105 };
106
107 ldo4_reg: ldo4 {
108 regulator-name = "VDD_PHY_2V5";
109 regulator-min-microvolt = <25000000>;
110 regulator-max-microvolt = <25000000>;
111 regulator-boot-on;
112 regulator-always-on;
113 };
114 };
115 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]116};
117
118&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]120};
121
122&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]124};
125
126&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]128};
129
130&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-pre-ram;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]132 k3_sysreset: sysreset-controller {
133 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]134 bootph-pre-ram;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]135 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]136};
137
138&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]140};
141
142&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]144};
145
146&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]148};
149
150&sdhci0 {
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]151 status = "disabled";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]152 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]153};
154
155&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]156 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]157};
158
159&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]160 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]161};
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]162
163&cpsw3g {
164 reg = <0x0 0x8000000 0x0 0x200000>,
165 <0x0 0x43000200 0x0 0x8>;
166 reg-names = "cpsw_nuss", "mac_efuse";
167 /delete-property/ ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]168 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]169
170 cpsw-phy-sel@04044 {
171 compatible = "ti,am64-phy-gmii-sel";
172 reg = <0x0 0x43004044 0x0 0x8>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]173 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]174 };
175
176 ethernet-ports {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]177 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]178 };
179};
180
181&cpsw_port2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]182 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]183};
184
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]185&main_bcdma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]186 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]187};
188
189&main_pktdma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]190 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]191};
192
193&rgmii1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]194 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]195};
196
197&rgmii2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]198 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]199};
200
201&mdio1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]202 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]203};
204
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]205&cpsw3g_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]206 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]207};
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]208
209&main_usb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]210 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]211};
212
213&serdes_ln_ctrl {
214 u-boot,mux-autoprobe;
215};
216
217&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]218 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]219};
220
221&usb0 {
222 dr_mode = "host";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]223 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]224};
225
226&serdes_wiz0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]227 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]228};
229
230&serdes0_usb_link {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]231 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]232};
233
234&serdes0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]235 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]236};
237
238&serdes_refclk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]239 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]240};