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git01.mediatek.com / filogic / uboot / 5ba115901775f2cdde9a4301f1ca55ae257ae4a1 / . / arch / arm / dts / imx8mm-evk-u-boot.dtsi
blob: 13688ec0d0f2620c186f607c2a1975acf671f539 [file] [log] [blame]
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]4 */
5
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]13 };
Clement Faurea93b0d92021-03-25 17:30:33 +0800[diff] [blame]14
15 firmware {
16 optee {
17 compatible = "linaro,optee-tz";
18 method = "smc";
19 };
20 };
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]21};
22
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]23&aips4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]25};
26
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]27&reg_usdhc2_vmmc {
28 u-boot,off-on-delay-us = <20000>;
29};
30
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]31&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]33};
34
35&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]37};
38
39&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]41};
42
43&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]45};
46
47&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]49};
50
51&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]53};
54
55&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]57};
58
59&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]61};
62
63&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]65};
66
67&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]69};
70
71&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]73};
74
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]75&crypto {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]77};
78
79&sec_jr0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]81};
82
83&sec_jr1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]85};
86
87&sec_jr2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]89};
90
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]91&usbmisc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]93};
94
95&usbphynop1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]97};
98
99&usbotg1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]101};
102
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]103&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]105};
106
107&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]109 sd-uhs-sdr104;
110 sd-uhs-ddr50;
Haibo Chen26154952021-03-22 18:55:38 +0800[diff] [blame]111 fsl,signal-voltage-switch-extra-delay-ms = <8>;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]112};
113
114&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]116 mmc-hs400-1_8v;
117 mmc-hs400-enhanced-strobe;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]118};
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]119
120&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]122};
123
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]124&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]126};
127
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]128&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]130};
131
132&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]133 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]134};
135
136&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]138};
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]139
Peng Fana279d682022-05-05 19:05:58 +0800[diff] [blame]140&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-pre-ram;
Peng Fana279d682022-05-05 19:05:58 +0800[diff] [blame]142};
143
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]144&fec1 {
145 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
146};
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]147
148&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]149 bootph-pre-ram;
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]150};