Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _CONFIG_THEADORABLE_H |
| 7 | #define _CONFIG_THEADORABLE_H |
| 8 | |
Tom Rini | 5155665 | 2021-08-21 13:50:14 -0400 | [diff] [blame] | 9 | #include <linux/sizes.h> |
| 10 | |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 11 | /* |
| 12 | * High Level Configuration Options (easy to change) |
| 13 | */ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 17 | * for DDR ECC byte filling in the SPL before loading the main |
| 18 | * U-Boot into it. |
| 19 | */ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 20 | |
| 21 | /* |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 22 | * The debugging version enables USB support via defconfig. |
| 23 | * This version should also enable all other non-production |
| 24 | * interfaces / features. |
| 25 | */ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 26 | |
| 27 | /* I2C */ |
Tom Rini | c188ed4 | 2022-12-04 10:04:09 -0500 | [diff] [blame] | 28 | #define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
Tom Rini | 34e4e86 | 2022-12-04 10:04:10 -0500 | [diff] [blame] | 29 | #define CFG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 30 | |
| 31 | /* USB/EHCI configuration */ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 32 | |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 33 | /* Environment in SPI NOR flash */ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 34 | |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 35 | /* Keep device tree and initrd in lower memory so the kernel can access them */ |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 36 | #define CFG_EXTRA_ENV_SETTINGS \ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 37 | "fdt_high=0x10000000\0" \ |
| 38 | "initrd_high=0x10000000\0" |
| 39 | |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 40 | /* |
Stefan Roese | 1a4e980 | 2016-04-07 10:48:14 +0200 | [diff] [blame] | 41 | * Bootcounter |
| 42 | */ |
Stefan Roese | 1a4e980 | 2016-04-07 10:48:14 +0200 | [diff] [blame] | 43 | /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ |
| 44 | #define BOOTCOUNT_ADDR 0x1000 |
| 45 | |
| 46 | /* |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 47 | * mv-common.h should be defined after CMD configs since it used them |
| 48 | * to enable certain macros |
| 49 | */ |
| 50 | #include "mv-common.h" |
| 51 | |
| 52 | /* |
| 53 | * Memory layout while starting into the bin_hdr via the |
| 54 | * BootROM: |
| 55 | * |
| 56 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) |
| 57 | * 0x4000.4030 bin_hdr start address |
| 58 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) |
| 59 | * 0x4007.fffc BootROM stack top |
| 60 | * |
| 61 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in |
| 62 | * L2 cache thus cannot be used. |
| 63 | */ |
| 64 | |
| 65 | /* SPL */ |
| 66 | /* Defines for SPL */ |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 67 | |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 68 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 69 | #define CFG_SYS_SDRAM_SIZE SZ_2G |
Stefan Roese | 459e064 | 2016-01-20 08:13:29 +0100 | [diff] [blame] | 70 | |
| 71 | #endif /* _CONFIG_THEADORABLE_H */ |