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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese459e0642016-01-20 08:13:29 +01002/*
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese459e0642016-01-20 08:13:29 +01004 */
5
6#ifndef _CONFIG_THEADORABLE_H
7#define _CONFIG_THEADORABLE_H
8
Tom Rini51556652021-08-21 13:50:14 -04009#include <linux/sizes.h>
10
Stefan Roese459e0642016-01-20 08:13:29 +010011/*
12 * High Level Configuration Options (easy to change)
13 */
Stefan Roese459e0642016-01-20 08:13:29 +010014
15/*
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
18 * U-Boot into it.
19 */
Stefan Roese459e0642016-01-20 08:13:29 +010020
21/*
Stefan Roese459e0642016-01-20 08:13:29 +010022 * The debugging version enables USB support via defconfig.
23 * This version should also enable all other non-production
24 * interfaces / features.
25 */
Stefan Roese459e0642016-01-20 08:13:29 +010026
27/* I2C */
Tom Rinic188ed42022-12-04 10:04:09 -050028#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Tom Rini34e4e862022-12-04 10:04:10 -050029#define CFG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese459e0642016-01-20 08:13:29 +010030
31/* USB/EHCI configuration */
Stefan Roese459e0642016-01-20 08:13:29 +010032
Stefan Roese459e0642016-01-20 08:13:29 +010033/* Environment in SPI NOR flash */
Stefan Roese459e0642016-01-20 08:13:29 +010034
Stefan Roese459e0642016-01-20 08:13:29 +010035/* Keep device tree and initrd in lower memory so the kernel can access them */
Tom Rinic9edebe2022-12-04 10:03:50 -050036#define CFG_EXTRA_ENV_SETTINGS \
Stefan Roese459e0642016-01-20 08:13:29 +010037 "fdt_high=0x10000000\0" \
38 "initrd_high=0x10000000\0"
39
Stefan Roese459e0642016-01-20 08:13:29 +010040/*
Stefan Roese1a4e9802016-04-07 10:48:14 +020041 * Bootcounter
42 */
Stefan Roese1a4e9802016-04-07 10:48:14 +020043/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
44#define BOOTCOUNT_ADDR 0x1000
45
46/*
Stefan Roese459e0642016-01-20 08:13:29 +010047 * mv-common.h should be defined after CMD configs since it used them
48 * to enable certain macros
49 */
50#include "mv-common.h"
51
52/*
53 * Memory layout while starting into the bin_hdr via the
54 * BootROM:
55 *
56 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
57 * 0x4000.4030 bin_hdr start address
58 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
59 * 0x4007.fffc BootROM stack top
60 *
61 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
62 * L2 cache thus cannot be used.
63 */
64
65/* SPL */
66/* Defines for SPL */
Stefan Roese459e0642016-01-20 08:13:29 +010067
Stefan Roese459e0642016-01-20 08:13:29 +010068/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Tom Rinibb4dd962022-11-16 13:10:37 -050069#define CFG_SYS_SDRAM_SIZE SZ_2G
Stefan Roese459e0642016-01-20 08:13:29 +010070
71#endif /* _CONFIG_THEADORABLE_H */