| Macpaul Lin | 1cac36e | 2011-10-19 20:41:11 +0000 | [diff] [blame] | 1 | N1213 is a configurable hard/soft core of NDS32's N12 CPU family. |
| 2 | |
| 3 | Features |
| 4 | ======== |
| 5 | |
| 6 | CPU Core |
| 7 | - 16-/32-bit mixable instruction format. |
| 8 | - 32 general-purpose 32-bit registers. |
| 9 | - 8-stage pipeline. |
| 10 | - Dynamic branch prediction. |
| 11 | - 32/64/128/256 BTB. |
| 12 | - Return address stack (RAS). |
| 13 | - Vector interrupts for internal/external. |
| 14 | interrupt controller with 6 hardware interrupt signals. |
| 15 | - 3 HW-level nested interruptions. |
| 16 | - User and super-user mode support. |
| 17 | - Memory-mapped I/O. |
| 18 | - Address space up to 4GB. |
| 19 | |
| 20 | Memory Management Unit |
| 21 | - TLB |
| 22 | - 4/8-entry fully associative iTLB/dTLB. |
| 23 | - 32/64/128-entry 4-way set-associati.ve main TLB. |
| 24 | - TLB locking support |
| 25 | - Optional hardware page table walker. |
| 26 | - Two groups of page size support. |
| 27 | - 4KB & 1MB. |
| 28 | - 8KB & 1MB. |
| 29 | |
| 30 | Memory Subsystem |
| 31 | - I & D cache. |
| 32 | - Virtually indexed and physically tagged. |
| 33 | - Cache size: 8KB/16KB/32KB/64KB. |
| 34 | - Cache line size: 16B/32B. |
| 35 | - Set associativity: 2-way, 4-way or direct-mapped. |
| 36 | - Cache locking support. |
| 37 | - I & D local memory (LM). |
| 38 | - Size: 4KB to 1MB. |
| 39 | - Bank numbers: 1 or 2. |
| 40 | - Optional 1D/2D DMA engine. |
| 41 | - Internal or external to CPU core. |
| 42 | |
| 43 | Bus Interface |
| 44 | - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports. |
| 45 | - Synchronous High speed memory port. |
| 46 | (HSMP): 0, 1 or 2 ports. |
| 47 | |
| 48 | Debug |
| 49 | - JTAG debug interface. |
| 50 | - Embedded debug module (EDM). |
| 51 | - Optional embedded program tracer interface. |
| 52 | |
| 53 | Miscellaneous |
| 54 | - Programmable data endian control. |
| 55 | - Performance monitoring mechanism. |